phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
PHY transceiver driver for QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller present on Qualcomm chipsets. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Vivek Gautam
Kishon Vijay Abraham I
Родитель
e9eef1e596
Коммит
ca04d9d3e1
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@ -439,6 +439,16 @@ config PHY_STIH407_USB
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Enable this support to enable the picoPHY device used by USB2
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and USB3 controllers on STMicroelectronics STiH407 SoC families.
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config PHY_QCOM_QUSB2
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tristate "Qualcomm QUSB2 PHY Driver"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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select GENERIC_PHY
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help
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Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
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controllers on Qualcomm chips. This driver supports the high-speed
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PHY which is usually paired with either the ChipIdea or Synopsys DWC3
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USB IPs on MSM SOCs.
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config PHY_QCOM_UFS
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tristate "Qualcomm UFS PHY driver"
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depends on OF && ARCH_QCOM
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@ -50,6 +50,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
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obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
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obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
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@ -0,0 +1,493 @@
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#define QUSB2PHY_PLL_TEST 0x04
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#define CLK_REF_SEL BIT(7)
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#define QUSB2PHY_PLL_TUNE 0x08
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#define QUSB2PHY_PLL_USER_CTL1 0x0c
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#define QUSB2PHY_PLL_USER_CTL2 0x10
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#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
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#define QUSB2PHY_PLL_PWR_CTRL 0x18
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#define QUSB2PHY_PLL_STATUS 0x38
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#define PLL_LOCKED BIT(5)
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#define QUSB2PHY_PORT_TUNE1 0x80
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#define QUSB2PHY_PORT_TUNE2 0x84
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#define QUSB2PHY_PORT_TUNE3 0x88
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#define QUSB2PHY_PORT_TUNE4 0x8c
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#define QUSB2PHY_PORT_TUNE5 0x90
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#define QUSB2PHY_PORT_TEST2 0x9c
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#define QUSB2PHY_PORT_POWERDOWN 0xb4
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#define CLAMP_N_EN BIT(5)
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#define FREEZIO_N BIT(1)
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#define POWER_DOWN BIT(0)
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#define QUSB2PHY_REFCLK_ENABLE BIT(0)
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#define PHY_CLK_SCHEME_SEL BIT(0)
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struct qusb2_phy_init_tbl {
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unsigned int offset;
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unsigned int val;
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};
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#define QUSB2_PHY_INIT_CFG(o, v) \
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{ \
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.offset = o, \
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.val = v, \
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}
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static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE1, 0xf8),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE2, 0xb3),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE3, 0x83),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE4, 0xc0),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TEST2, 0x14),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
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};
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struct qusb2_phy_cfg {
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const struct qusb2_phy_init_tbl *tbl;
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/* number of entries in the table */
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unsigned int tbl_num;
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/* offset to PHY_CLK_SCHEME register in TCSR map */
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unsigned int clk_scheme_offset;
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};
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static const struct qusb2_phy_cfg msm8996_phy_cfg = {
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.tbl = msm8996_init_tbl,
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.tbl_num = ARRAY_SIZE(msm8996_init_tbl),
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};
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static const char * const qusb2_phy_vreg_names[] = {
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"vdda-pll", "vdda-phy-dpdm",
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};
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#define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
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/**
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* struct qusb2_phy - structure holding qusb2 phy attributes
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*
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* @phy: generic phy
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* @base: iomapped memory space for qubs2 phy
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*
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* @cfg_ahb_clk: AHB2PHY interface clock
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* @ref_clk: phy reference clock
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* @iface_clk: phy interface clock
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* @phy_reset: phy reset control
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* @vregs: regulator supplies bulk data
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*
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* @tcsr: TCSR syscon register map
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* @cell: nvmem cell containing phy tuning value
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*
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* @cfg: phy config data
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* @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
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*/
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struct qusb2_phy {
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struct phy *phy;
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void __iomem *base;
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struct clk *cfg_ahb_clk;
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struct clk *ref_clk;
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struct clk *iface_clk;
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struct reset_control *phy_reset;
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struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
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struct regmap *tcsr;
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struct nvmem_cell *cell;
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const struct qusb2_phy_cfg *cfg;
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bool has_se_clk_scheme;
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};
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static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
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{
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u32 reg;
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reg = readl(base + offset);
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reg |= val;
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writel(reg, base + offset);
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/* Ensure above write is completed */
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readl(base + offset);
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}
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static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
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{
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u32 reg;
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reg = readl(base + offset);
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reg &= ~val;
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writel(reg, base + offset);
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/* Ensure above write is completed */
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readl(base + offset);
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}
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static inline
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void qcom_qusb2_phy_configure(void __iomem *base,
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const struct qusb2_phy_init_tbl tbl[], int num)
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{
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int i;
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for (i = 0; i < num; i++)
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writel(tbl[i].val, base + tbl[i].offset);
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}
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/*
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* Fetches HS Tx tuning value from nvmem and sets the
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* QUSB2PHY_PORT_TUNE2 register.
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* For error case, skip setting the value and use the default value.
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*/
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static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
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{
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struct device *dev = &qphy->phy->dev;
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u8 *val;
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/*
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* Read efuse register having TUNE2 parameter's high nibble.
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* If efuse register shows value as 0x0, or if we fail to find
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* a valid efuse register settings, then use default value
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* as 0xB for high nibble that we have already set while
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* configuring phy.
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*/
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val = nvmem_cell_read(qphy->cell, NULL);
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if (IS_ERR(val) || !val[0]) {
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dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
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return;
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}
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/* Fused TUNE2 value is the higher nibble only */
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qusb2_setbits(qphy->base, QUSB2PHY_PORT_TUNE2, val[0] << 0x4);
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}
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static int qusb2_phy_poweron(struct phy *phy)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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int num = ARRAY_SIZE(qphy->vregs);
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int ret;
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dev_vdbg(&phy->dev, "%s(): Powering-on QUSB2 phy\n", __func__);
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/* turn on regulator supplies */
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ret = regulator_bulk_enable(num, qphy->vregs);
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if (ret)
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return ret;
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ret = clk_prepare_enable(qphy->iface_clk);
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if (ret) {
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dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
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regulator_bulk_disable(num, qphy->vregs);
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return ret;
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}
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return 0;
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}
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static int qusb2_phy_poweroff(struct phy *phy)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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clk_disable_unprepare(qphy->iface_clk);
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regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
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return 0;
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}
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static int qusb2_phy_init(struct phy *phy)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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unsigned int val;
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unsigned int clk_scheme;
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int ret;
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dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
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/* enable ahb interface clock to program phy */
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ret = clk_prepare_enable(qphy->cfg_ahb_clk);
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if (ret) {
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dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
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return ret;
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}
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/* Perform phy reset */
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ret = reset_control_assert(qphy->phy_reset);
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if (ret) {
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dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
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goto disable_ahb_clk;
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}
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/* 100 us delay to keep PHY in reset mode */
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usleep_range(100, 150);
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ret = reset_control_deassert(qphy->phy_reset);
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if (ret) {
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dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
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goto disable_ahb_clk;
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}
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/* Disable the PHY */
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qusb2_setbits(qphy->base, QUSB2PHY_PORT_POWERDOWN,
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CLAMP_N_EN | FREEZIO_N | POWER_DOWN);
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/* save reset value to override reference clock scheme later */
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val = readl(qphy->base + QUSB2PHY_PLL_TEST);
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qcom_qusb2_phy_configure(qphy->base, qphy->cfg->tbl,
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qphy->cfg->tbl_num);
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/* Set efuse value for tuning the PHY */
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qusb2_phy_set_tune2_param(qphy);
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/* Enable the PHY */
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qusb2_clrbits(qphy->base, QUSB2PHY_PORT_POWERDOWN, POWER_DOWN);
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/* Required to get phy pll lock successfully */
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usleep_range(150, 160);
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/* Default is single-ended clock on msm8996 */
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qphy->has_se_clk_scheme = true;
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/*
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* read TCSR_PHY_CLK_SCHEME register to check if single-ended
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* clock scheme is selected. If yes, then disable differential
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* ref_clk and use single-ended clock, otherwise use differential
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* ref_clk only.
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*/
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if (qphy->tcsr) {
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ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
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&clk_scheme);
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if (ret) {
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dev_err(&phy->dev, "failed to read clk scheme reg\n");
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goto assert_phy_reset;
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}
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/* is it a differential clock scheme ? */
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if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
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dev_vdbg(&phy->dev, "%s(): select differential clk\n",
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__func__);
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qphy->has_se_clk_scheme = false;
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} else {
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dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
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__func__);
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}
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}
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if (!qphy->has_se_clk_scheme) {
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val &= ~CLK_REF_SEL;
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ret = clk_prepare_enable(qphy->ref_clk);
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if (ret) {
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dev_err(&phy->dev, "failed to enable ref clk, %d\n",
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ret);
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goto assert_phy_reset;
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}
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} else {
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val |= CLK_REF_SEL;
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}
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writel(val, qphy->base + QUSB2PHY_PLL_TEST);
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/* ensure above write is through */
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readl(qphy->base + QUSB2PHY_PLL_TEST);
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/* Required to get phy pll lock successfully */
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usleep_range(100, 110);
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val = readb(qphy->base + QUSB2PHY_PLL_STATUS);
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if (!(val & PLL_LOCKED)) {
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dev_err(&phy->dev,
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"QUSB2PHY pll lock failed: status reg = %x\n", val);
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ret = -EBUSY;
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goto disable_ref_clk;
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}
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return 0;
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disable_ref_clk:
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if (!qphy->has_se_clk_scheme)
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clk_disable_unprepare(qphy->ref_clk);
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assert_phy_reset:
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reset_control_assert(qphy->phy_reset);
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disable_ahb_clk:
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clk_disable_unprepare(qphy->cfg_ahb_clk);
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return ret;
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}
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static int qusb2_phy_exit(struct phy *phy)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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/* Disable the PHY */
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qusb2_setbits(qphy->base, QUSB2PHY_PORT_POWERDOWN,
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CLAMP_N_EN | FREEZIO_N | POWER_DOWN);
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if (!qphy->has_se_clk_scheme)
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clk_disable_unprepare(qphy->ref_clk);
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reset_control_assert(qphy->phy_reset);
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clk_disable_unprepare(qphy->cfg_ahb_clk);
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return 0;
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}
|
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static const struct phy_ops qusb2_phy_gen_ops = {
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.init = qusb2_phy_init,
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.exit = qusb2_phy_exit,
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.power_on = qusb2_phy_poweron,
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.power_off = qusb2_phy_poweroff,
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.owner = THIS_MODULE,
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};
|
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static const struct of_device_id qusb2_phy_of_match_table[] = {
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||||
{
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.compatible = "qcom,msm8996-qusb2-phy",
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.data = &msm8996_phy_cfg,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
|
||||
|
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static int qusb2_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct qusb2_phy *qphy;
|
||||
struct phy_provider *phy_provider;
|
||||
struct phy *generic_phy;
|
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struct resource *res;
|
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int ret, i;
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int num;
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qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
|
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if (!qphy)
|
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return -ENOMEM;
|
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|
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
qphy->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(qphy->base))
|
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return PTR_ERR(qphy->base);
|
||||
|
||||
qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
|
||||
if (IS_ERR(qphy->cfg_ahb_clk)) {
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||||
ret = PTR_ERR(qphy->cfg_ahb_clk);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
qphy->ref_clk = devm_clk_get(dev, "ref");
|
||||
if (IS_ERR(qphy->ref_clk)) {
|
||||
ret = PTR_ERR(qphy->ref_clk);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "failed to get ref clk, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
qphy->iface_clk = devm_clk_get(dev, "iface");
|
||||
if (IS_ERR(qphy->iface_clk)) {
|
||||
ret = PTR_ERR(qphy->iface_clk);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
return ret;
|
||||
qphy->iface_clk = NULL;
|
||||
dev_dbg(dev, "failed to get iface clk, %d\n", ret);
|
||||
}
|
||||
|
||||
qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
|
||||
if (IS_ERR(qphy->phy_reset)) {
|
||||
dev_err(dev, "failed to get phy core reset\n");
|
||||
return PTR_ERR(qphy->phy_reset);
|
||||
}
|
||||
|
||||
num = ARRAY_SIZE(qphy->vregs);
|
||||
for (i = 0; i < num; i++)
|
||||
qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
|
||||
|
||||
ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get regulator supplies\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get the specific init parameters of QMP phy */
|
||||
qphy->cfg = of_device_get_match_data(dev);
|
||||
|
||||
qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
"qcom,tcsr-syscon");
|
||||
if (IS_ERR(qphy->tcsr)) {
|
||||
dev_dbg(dev, "failed to lookup TCSR regmap\n");
|
||||
qphy->tcsr = NULL;
|
||||
}
|
||||
|
||||
qphy->cell = devm_nvmem_cell_get(dev, NULL);
|
||||
if (IS_ERR(qphy->cell)) {
|
||||
if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
qphy->cell = NULL;
|
||||
dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
|
||||
}
|
||||
|
||||
generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
ret = PTR_ERR(generic_phy);
|
||||
dev_err(dev, "failed to create phy, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
qphy->phy = generic_phy;
|
||||
|
||||
dev_set_drvdata(dev, qphy);
|
||||
phy_set_drvdata(generic_phy, qphy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (!IS_ERR(phy_provider))
|
||||
dev_info(dev, "Registered Qcom-QUSB2 phy\n");
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy_provider);
|
||||
}
|
||||
|
||||
static struct platform_driver qusb2_phy_driver = {
|
||||
.probe = qusb2_phy_probe,
|
||||
.driver = {
|
||||
.name = "qcom-qusb2-phy",
|
||||
.of_match_table = qusb2_phy_of_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(qusb2_phy_driver);
|
||||
|
||||
MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
|
||||
MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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