ARC updates for 4.15-rc1
- More changes for HS48 cores: supporting MMUv5, detecting new micro-arch gizmos - axs10x platform wiring up reset driver merged in this cycle - ARC perf driver optimizations -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaFdirAAoJEGnX8d3iisJe7bcP/iKL3sfCHwzgQQ4jUvm32PfL /YlMXk6+YhboGb1txrEOyot1ZIAFNpHrKLunhkkHSlKxySxRZ29+umWBQfIy7MN/ 2YrBfpCXwugwajA00PD45uv340QJtTa9UkR9WMVH0XDtTtgpUy3rm6Ee1nt6+elF M7BEZgfD5LgMP0eKgHVkZwK3OT/oYm+a5M8bjCdSKuwjtrd4W3ZC9WPv1mZLjAAO S5DDfa+TeufublqJviZzQmLXipFvluBdGbzANJpkAYMnE82vKkrlqAWQSEJ5kwRn 3mbFOze8sFPUlo5uji6Z9Sf2a/G9e3PX5d6xPIQcNaNFxdyVrr4VDLQII6ulJcBj dlS6TPg3/5UerhiGwUnJfIQxlqw/Ebn4RvgzksxX8+ujjjvd2kY3DCFVzjlKaenh Bwo0kyLhCJKHSInKvW4r6W2ZnBW6VWoGST/KYwgZJwTeoxl043BRA2AoNKKiolJJ d5vyonUXjIddUtcwO3vt/xx1lqKf49ZK0Bx8EGDMYHhZwpGt13geZme7b5H975oB uPM+m9vPyiyiD2HziAydvoLT+uCyRSFObHKcQLs+1E+QSw/tzrQgNsMTwhSPtg/g Uwt/KU+cCnLeksGRuB4LgSp/7nbhB6PGVzUeRCo2VVls875TRQxPEjJ1rZ2kd9JO IVpYxDlu+4cKsRDK/EIl =LX+r -----END PGP SIGNATURE----- Merge tag 'arc-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - more changes for HS48 cores: supporting MMUv5, detecting new micro-arch gizmos - axs10x platform wiring up reset driver merged in this cycle - ARC perf driver optimizations * tag 'arc-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: perf: avoid vmalloc backed mmap ARCv2: perf: optimize given that num counters <= 32 ARCv2: perf: tweak overflow interrupt ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer ARCv2: Accomodate HS48 MMUv5 by relaxing MMU ver checking ARC: [plat-axs10x] auto-select AXS101 or AXS103 given the ISA config
This commit is contained in:
Linus Torvalds
Коммит
ca122fe376
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@ -39,7 +39,7 @@ config ARC
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select OF
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select OF_EARLY_FLATTREE
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select OF_RESERVED_MEM
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select PERF_USE_VMALLOC
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select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
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select HAVE_DEBUG_STACKOVERFLOW
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select HAVE_GENERIC_DMA_COHERENT
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select HAVE_KERNEL_GZIP
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@ -16,6 +16,12 @@
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ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
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interrupt-parent = <&mb_intc>;
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creg_rst: reset-controller@11220 {
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compatible = "snps,axs10x-reset";
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#reset-cells = <1>;
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reg = <0x11220 0x4>;
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};
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i2sclk: i2sclk@100a0 {
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compatible = "snps,axs10x-i2s-pll-clock";
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reg = <0x100a0 0x10>;
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@ -73,6 +79,8 @@
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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max-speed = <100>;
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resets = <&creg_rst 5>;
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reset-names = "stmmaceth";
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};
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ehci@0x40000 {
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@ -11,12 +11,14 @@
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/* Build Configuration Registers */
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#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
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#define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
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#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
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#define ARC_REG_CRC_BCR 0x62
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#define ARC_REG_VECBASE_BCR 0x68
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#define ARC_REG_PERIBASE_BCR 0x69
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#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
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#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
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#define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
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#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
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#define ARC_REG_SLC_BCR 0xce
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#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
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@ -32,11 +34,14 @@
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#define ARC_REG_D_UNCACH_BCR 0x6A
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#define ARC_REG_BPU_BCR 0xc0
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#define ARC_REG_ISA_CFG_BCR 0xc1
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#define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
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#define ARC_REG_RTT_BCR 0xF2
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#define ARC_REG_IRQ_BCR 0xF3
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#define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
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#define ARC_REG_SMART_BCR 0xFF
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#define ARC_REG_CLUSTER_BCR 0xcf
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#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
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#define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
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/* Common for ARCompact and ARCv2 status register */
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#define ARC_REG_STATUS32 0x0A
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@ -229,6 +234,32 @@ struct bcr_bpu_arcv2 {
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#endif
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};
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/* Error Protection Build: ECC/Parity */
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struct bcr_erp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
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#else
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unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
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#endif
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};
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/* Error Protection Control */
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struct ctl_erp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
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#else
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unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
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#endif
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};
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struct bcr_lpb {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:16, entries:8, ver:8;
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#else
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unsigned int ver:8, entries:8, pad:16;
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#endif
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};
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struct bcr_generic {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int info:24, ver:8;
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@ -270,7 +301,7 @@ struct cpuinfo_arc {
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struct cpuinfo_arc_ccm iccm, dccm;
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struct {
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unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
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fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
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fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
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debug:1, ap:1, smart:1, rtt:1, pad3:4,
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timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
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} extn;
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@ -336,15 +336,12 @@ static int arc_pmu_add(struct perf_event *event, int flags)
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (__test_and_set_bit(idx, pmu_cpu->used_mask)) {
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idx = find_first_zero_bit(pmu_cpu->used_mask,
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arc_pmu->n_counters);
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if (idx == arc_pmu->n_counters)
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return -EAGAIN;
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idx = ffz(pmu_cpu->used_mask[0]);
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if (idx == arc_pmu->n_counters)
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return -EAGAIN;
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__set_bit(idx, pmu_cpu->used_mask);
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hwc->idx = idx;
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}
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__set_bit(idx, pmu_cpu->used_mask);
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hwc->idx = idx;
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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@ -377,21 +374,22 @@ static irqreturn_t arc_pmu_intr(int irq, void *dev)
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struct perf_sample_data data;
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struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
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struct pt_regs *regs;
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int active_ints;
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unsigned int active_ints;
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int idx;
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arc_pmu_disable(&arc_pmu->pmu);
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active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);
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if (!active_ints)
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goto done;
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regs = get_irq_regs();
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for (idx = 0; idx < arc_pmu->n_counters; idx++) {
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struct perf_event *event = pmu_cpu->act_counter[idx];
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do {
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struct perf_event *event;
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struct hw_perf_event *hwc;
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if (!(active_ints & (1 << idx)))
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continue;
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idx = __ffs(active_ints);
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/* Reset interrupt flag by writing of 1 */
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write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
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@ -404,19 +402,22 @@ static irqreturn_t arc_pmu_intr(int irq, void *dev)
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write_aux_reg(ARC_REG_PCT_INT_CTRL,
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read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
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event = pmu_cpu->act_counter[idx];
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hwc = &event->hw;
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WARN_ON_ONCE(hwc->idx != idx);
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arc_perf_event_update(event, &event->hw, event->hw.idx);
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perf_sample_data_init(&data, 0, hwc->last_period);
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if (!arc_pmu_event_set_period(event))
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continue;
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if (arc_pmu_event_set_period(event)) {
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if (perf_event_overflow(event, &data, regs))
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arc_pmu_stop(event, 0);
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}
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if (perf_event_overflow(event, &data, regs))
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arc_pmu_stop(event, 0);
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}
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active_ints &= ~(1U << idx);
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} while (active_ints);
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done:
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arc_pmu_enable(&arc_pmu->pmu);
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return IRQ_HANDLED;
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@ -461,6 +462,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
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pr_err("This core does not have performance counters!\n");
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return -ENODEV;
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}
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BUILD_BUG_ON(ARC_PERF_MAX_COUNTERS > 32);
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BUG_ON(pct_bcr.c > ARC_PERF_MAX_COUNTERS);
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READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
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@ -199,8 +199,10 @@ static void read_arc_build_cfg_regs(void)
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unsigned int exec_ctrl;
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READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
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cpu->extn.dual_iss_exist = 1;
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cpu->extn.dual_iss_enb = exec_ctrl & 1;
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cpu->extn.dual_enb = exec_ctrl & 1;
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/* dual issue always present for this core */
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cpu->extn.dual = 1;
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}
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}
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@ -253,7 +255,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
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cpu_id, cpu->name, cpu->details,
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is_isa_arcompact() ? "ARCompact" : "ARCv2",
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IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
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IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
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IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
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n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
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IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
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@ -293,11 +295,26 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
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if (cpu->bpu.ver)
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n += scnprintf(buf + n, len - n,
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"BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
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"BPU\t\t: %s%s match, cache:%d, Predict Table:%d",
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IS_AVAIL1(cpu->bpu.full, "full"),
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IS_AVAIL1(!cpu->bpu.full, "partial"),
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cpu->bpu.num_cache, cpu->bpu.num_pred);
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if (is_isa_arcv2()) {
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struct bcr_lpb lpb;
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READ_BCR(ARC_REG_LPB_BUILD, lpb);
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if (lpb.ver) {
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unsigned int ctl;
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ctl = read_aux_reg(ARC_REG_LPB_CTRL);
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n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
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lpb.entries,
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IS_DISABLED_RUN(!ctl));
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}
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}
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n += scnprintf(buf + n, len - n, "\n");
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return buf;
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}
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@ -326,6 +343,24 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
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cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
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cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
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if (is_isa_arcv2()) {
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/* Error Protection: ECC/Parity */
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struct bcr_erp erp;
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READ_BCR(ARC_REG_ERP_BUILD, erp);
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if (erp.ver) {
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struct ctl_erp ctl;
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READ_BCR(ARC_REG_ERP_CTRL, ctl);
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/* inverted bits: 0 means enabled */
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n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
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IS_AVAIL3(erp.ic, !ctl.dpi, "IC "),
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IS_AVAIL3(erp.dc, !ctl.dpd, "DC "),
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IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
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}
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}
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n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
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EF_ARC_OSABI_CURRENT >> 8,
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EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
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|
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@ -762,21 +762,23 @@ void read_decode_mmu_bcr(void)
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tmp = read_aux_reg(ARC_REG_MMU_BCR);
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mmu->ver = (tmp >> 24);
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if (mmu->ver <= 2) {
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mmu2 = (struct bcr_mmu_1_2 *)&tmp;
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mmu->pg_sz_k = TO_KB(0x2000);
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mmu->sets = 1 << mmu2->sets;
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mmu->ways = 1 << mmu2->ways;
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mmu->u_dtlb = mmu2->u_dtlb;
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mmu->u_itlb = mmu2->u_itlb;
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} else if (mmu->ver == 3) {
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mmu3 = (struct bcr_mmu_3 *)&tmp;
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mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
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mmu->sets = 1 << mmu3->sets;
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mmu->ways = 1 << mmu3->ways;
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mmu->u_dtlb = mmu3->u_dtlb;
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mmu->u_itlb = mmu3->u_itlb;
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mmu->sasid = mmu3->sasid;
|
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if (is_isa_arcompact()) {
|
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if (mmu->ver <= 2) {
|
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mmu2 = (struct bcr_mmu_1_2 *)&tmp;
|
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mmu->pg_sz_k = TO_KB(0x2000);
|
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mmu->sets = 1 << mmu2->sets;
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mmu->ways = 1 << mmu2->ways;
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mmu->u_dtlb = mmu2->u_dtlb;
|
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mmu->u_itlb = mmu2->u_itlb;
|
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} else {
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mmu3 = (struct bcr_mmu_3 *)&tmp;
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mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
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mmu->sets = 1 << mmu3->sets;
|
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mmu->ways = 1 << mmu3->ways;
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mmu->u_dtlb = mmu3->u_dtlb;
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mmu->u_itlb = mmu3->u_itlb;
|
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mmu->sasid = mmu3->sasid;
|
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}
|
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} else {
|
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mmu4 = (struct bcr_mmu_4 *)&tmp;
|
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mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
|
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|
|
@ -818,8 +820,9 @@ int pae40_exist_but_not_enab(void)
|
|||
|
||||
void arc_mmu_init(void)
|
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{
|
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char str[256];
|
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
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char str[256];
|
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int compat = 0;
|
||||
|
||||
pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
|
||||
|
||||
|
|
@ -834,15 +837,21 @@ void arc_mmu_init(void)
|
|||
*/
|
||||
BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
|
||||
|
||||
/* For efficiency sake, kernel is compile time built for a MMU ver
|
||||
* This must match the hardware it is running on.
|
||||
* Linux built for MMU V2, if run on MMU V1 will break down because V1
|
||||
* hardware doesn't understand cmds such as WriteNI, or IVUTLB
|
||||
* On the other hand, Linux built for V1 if run on MMU V2 will do
|
||||
* un-needed workarounds to prevent memcpy thrashing.
|
||||
* Similarly MMU V3 has new features which won't work on older MMU
|
||||
/*
|
||||
* Ensure that MMU features assumed by kernel exist in hardware.
|
||||
* For older ARC700 cpus, it has to be exact match, since the MMU
|
||||
* revisions were not backwards compatible (MMUv3 TLB layout changed
|
||||
* so even if kernel for v2 didn't use any new cmds of v3, it would
|
||||
* still not work.
|
||||
* For HS cpus, MMUv4 was baseline and v5 is backwards compatible
|
||||
* (will run older software).
|
||||
*/
|
||||
if (mmu->ver != CONFIG_ARC_MMU_VER) {
|
||||
if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER)
|
||||
compat = 1;
|
||||
else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER)
|
||||
compat = 1;
|
||||
|
||||
if (!compat) {
|
||||
panic("MMU ver %d doesn't match kernel built for %d...\n",
|
||||
mmu->ver, CONFIG_ARC_MMU_VER);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,6 +14,8 @@ menuconfig ARC_PLAT_AXS10X
|
|||
select MIGHT_HAVE_PCI
|
||||
select GENERIC_IRQ_CHIP
|
||||
select GPIOLIB
|
||||
select AXS101 if ISA_ARCOMPACT
|
||||
select AXS103 if ISA_ARCV2
|
||||
help
|
||||
Support for the ARC AXS10x Software Development Platforms.
|
||||
|
||||
|
|
|
|||
|
|
@ -111,13 +111,6 @@ static void __init axs10x_early_init(void)
|
|||
|
||||
axs10x_enable_gpio_intc_wire();
|
||||
|
||||
/*
|
||||
* Reset ethernet IP core.
|
||||
* TODO: get rid of this quirk after axs10x reset driver (or simple
|
||||
* reset driver) will be available in upstream.
|
||||
*/
|
||||
iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
|
||||
|
||||
scnprintf(mb, 32, "MainBoard v%d", mb_rev);
|
||||
axs10x_print_board_ver(CREG_MB_VER, mb);
|
||||
}
|
||||
|
|
|
|||
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