fpga: add altera freeze bridge support
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge framework. A freeze bridge is a bridge that exists in the FPGA fabric to isolate one region of the FPGA from the busses while that one region is being reprogrammed. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alan Tull
Greg Kroah-Hartman
Родитель
e5f8efa5c8
Коммит
ca24a648f5
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@ -47,6 +47,15 @@ config SOCFPGA_FPGA_BRIDGE
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Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
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devices.
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config ALTERA_FREEZE_BRIDGE
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tristate "Altera FPGA Freeze Bridge"
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depends on ARCH_SOCFPGA && FPGA_BRIDGE
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help
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Say Y to enable drivers for Altera FPGA Freeze bridges. A
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freeze bridge is a bridge that exists in the FPGA fabric to
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isolate one region of the FPGA from the busses while that
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region is being reprogrammed.
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endif # FPGA
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endmenu
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@ -12,6 +12,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
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# FPGA Bridge Drivers
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obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
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obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
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obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
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# High Level Interfaces
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obj-$(CONFIG_FPGA_REGION) += fpga-region.o
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@ -0,0 +1,273 @@
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/*
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* FPGA Freeze Bridge Controller
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*
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* Copyright (C) 2016 Altera Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/fpga/fpga-bridge.h>
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#define FREEZE_CSR_STATUS_OFFSET 0
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#define FREEZE_CSR_CTRL_OFFSET 4
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#define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8
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#define FREEZE_CSR_REG_VERSION 12
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#define FREEZE_CSR_SUPPORTED_VERSION 2
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#define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0)
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#define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
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#define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0)
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#define FREEZE_CSR_CTRL_RESET_REQ BIT(1)
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#define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2)
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#define FREEZE_BRIDGE_NAME "freeze"
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struct altera_freeze_br_data {
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struct device *dev;
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void __iomem *base_addr;
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bool enable;
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};
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/*
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* Poll status until status bit is set or we have a timeout.
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*/
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static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
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u32 timeout, u32 req_ack)
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{
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struct device *dev = priv->dev;
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void __iomem *csr_illegal_req_addr = priv->base_addr +
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FREEZE_CSR_ILLEGAL_REQ_OFFSET;
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u32 status, illegal, ctrl;
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int ret = -ETIMEDOUT;
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do {
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illegal = readl(csr_illegal_req_addr);
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if (illegal) {
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dev_err(dev, "illegal request detected 0x%x", illegal);
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writel(1, csr_illegal_req_addr);
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illegal = readl(csr_illegal_req_addr);
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if (illegal)
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dev_err(dev, "illegal request not cleared 0x%x",
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illegal);
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ret = -EINVAL;
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break;
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}
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status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
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dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
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status &= req_ack;
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if (status) {
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ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
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dev_dbg(dev, "%s request %x acknowledged %x %x\n",
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__func__, req_ack, status, ctrl);
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ret = 0;
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break;
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}
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udelay(1);
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} while (timeout--);
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if (ret == -ETIMEDOUT)
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dev_err(dev, "%s timeout waiting for 0x%x\n",
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__func__, req_ack);
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return ret;
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}
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static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
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u32 timeout)
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{
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struct device *dev = priv->dev;
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void __iomem *csr_ctrl_addr = priv->base_addr +
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FREEZE_CSR_CTRL_OFFSET;
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u32 status;
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int ret;
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status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
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dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
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if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
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dev_dbg(dev, "%s bridge already disabled %d\n",
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__func__, status);
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return 0;
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} else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
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dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
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return -EINVAL;
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}
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writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
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ret = altera_freeze_br_req_ack(priv, timeout,
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FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
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if (ret)
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writel(0, csr_ctrl_addr);
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else
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writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
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return ret;
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}
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static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
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u32 timeout)
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{
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struct device *dev = priv->dev;
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void __iomem *csr_ctrl_addr = priv->base_addr +
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FREEZE_CSR_CTRL_OFFSET;
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u32 status;
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int ret;
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writel(0, csr_ctrl_addr);
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status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
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dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
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if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
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dev_dbg(dev, "%s bridge already enabled %d\n",
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__func__, status);
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return 0;
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} else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
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dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
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return -EINVAL;
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}
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writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
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ret = altera_freeze_br_req_ack(priv, timeout,
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FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
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status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
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dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
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writel(0, csr_ctrl_addr);
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return ret;
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}
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/*
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* enable = 1 : allow traffic through the bridge
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* enable = 0 : disable traffic through the bridge
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*/
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static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
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bool enable)
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{
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struct altera_freeze_br_data *priv = bridge->priv;
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struct fpga_image_info *info = bridge->info;
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u32 timeout = 0;
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int ret;
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if (enable) {
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if (info)
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timeout = info->enable_timeout_us;
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ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
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} else {
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if (info)
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timeout = info->disable_timeout_us;
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ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
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}
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if (!ret)
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priv->enable = enable;
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return ret;
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}
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static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
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{
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struct altera_freeze_br_data *priv = bridge->priv;
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return priv->enable;
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}
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static struct fpga_bridge_ops altera_freeze_br_br_ops = {
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.enable_set = altera_freeze_br_enable_set,
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.enable_show = altera_freeze_br_enable_show,
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};
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static const struct of_device_id altera_freeze_br_of_match[] = {
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{ .compatible = "altr,freeze-bridge-controller", },
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{},
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};
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MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
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static int altera_freeze_br_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct altera_freeze_br_data *priv;
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struct resource *res;
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u32 status, revision;
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if (!np)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base_addr = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base_addr))
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return PTR_ERR(priv->base_addr);
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status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
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if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
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priv->enable = 1;
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revision = readl(priv->base_addr + FREEZE_CSR_REG_VERSION);
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if (revision != FREEZE_CSR_SUPPORTED_VERSION)
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dev_warn(dev,
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"%s Freeze Controller unexpected revision %d != %d\n",
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__func__, revision, FREEZE_CSR_SUPPORTED_VERSION);
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return fpga_bridge_register(dev, FREEZE_BRIDGE_NAME,
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&altera_freeze_br_br_ops, priv);
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}
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static int altera_freeze_br_remove(struct platform_device *pdev)
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{
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fpga_bridge_unregister(&pdev->dev);
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return 0;
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}
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static struct platform_driver altera_freeze_br_driver = {
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.probe = altera_freeze_br_probe,
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.remove = altera_freeze_br_remove,
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.driver = {
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.name = "altera_freeze_br",
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.of_match_table = of_match_ptr(altera_freeze_br_of_match),
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},
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};
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module_platform_driver(altera_freeze_br_driver);
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MODULE_DESCRIPTION("Altera Freeze Bridge");
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MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
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MODULE_LICENSE("GPL v2");
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