mlx4_core: Clean up enabling of SENSE_PORT for older (ConnectX-1/-2) HCAs
Instead of having a hard-coded "PCI device ID != 0x1003" (which obviously breaks as newer devices with ID != 0x1003 become available), instead let's set a flag in our PCI device table for the older devices where we're supposed to force using SENSE_PORT. This also avoids enabling SENSE_PORT for virtual functions by mistake. Signed-off-by: Roland Dreier <roland@purestorage.com>
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@ -297,8 +297,8 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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mlx4_dbg(dev, "Steering mode is: %s\n",
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mlx4_steering_mode_str(dev->caps.steering_mode));
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/* Sense port always allowed on supported devices for ConnectX1 and 2 */
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if (dev->pdev->device != 0x1003)
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/* Sense port always allowed on supported devices for ConnectX-1 and -2 */
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if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
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dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
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dev->caps.log_num_macs = log_num_mac;
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@ -2314,29 +2314,29 @@ int mlx4_restart_one(struct pci_dev *pdev)
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static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
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/* MT25408 "Hermon" SDR */
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{ PCI_VDEVICE(MELLANOX, 0x6340), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25408 "Hermon" DDR */
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{ PCI_VDEVICE(MELLANOX, 0x634a), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25408 "Hermon" QDR */
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{ PCI_VDEVICE(MELLANOX, 0x6354), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25408 "Hermon" DDR PCIe gen2 */
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{ PCI_VDEVICE(MELLANOX, 0x6732), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25408 "Hermon" QDR PCIe gen2 */
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{ PCI_VDEVICE(MELLANOX, 0x673c), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25408 "Hermon" EN 10GigE */
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{ PCI_VDEVICE(MELLANOX, 0x6368), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25408 "Hermon" EN 10GigE PCIe gen2 */
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{ PCI_VDEVICE(MELLANOX, 0x6750), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25458 ConnectX EN 10GBASE-T 10GigE */
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{ PCI_VDEVICE(MELLANOX, 0x6372), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
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{ PCI_VDEVICE(MELLANOX, 0x675a), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT26468 ConnectX EN 10GigE PCIe gen2*/
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{ PCI_VDEVICE(MELLANOX, 0x6764), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
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{ PCI_VDEVICE(MELLANOX, 0x6746), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT26478 ConnectX2 40GigE PCIe gen2 */
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{ PCI_VDEVICE(MELLANOX, 0x676e), 0 },
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{ PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
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/* MT25400 Family [ConnectX-2 Virtual Function] */
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{ PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
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/* MT27500 Family [ConnectX-3] */
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@ -770,6 +770,7 @@ struct _rule_hw {
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enum {
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MLX4_PCI_DEV_IS_VF = 1 << 0,
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MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
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};
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struct mlx4_priv {
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