Merge series "add driver to support firmware loading on Cirrus Logic DSPs" from Simon Trimmer <simont@opensource.cirrus.com>:
This series of patches gradually separates the ASoC specific wm_adsp
code from that required to manage firmware in Cirrus Logic DSPs.
The series starts with renaming, progresses to splitting the
functionality before finally moving the independent functionality into
drivers/firmware so that it can be used by both the existing ASoC
wm_adsp and new non-audio parts.
Charles Keepax (3):
ASoC: wm_adsp: Move check for control existence
ASoC: wm_adsp: Switch to using wm_coeff_read_ctrl for compressed
buffers
ASoC: wm_adsp: Move sys_config_size to wm_adsp
Simon Trimmer (13):
ASoC: wm_adsp: Remove use of snd_ctl_elem_type_t
ASoC: wm_adsp: Cancel ongoing work when removing controls
ASoC: wm_adsp: Rename generic DSP support
ASoC: wm_adsp: Introduce cs_dsp logging macros
ASoC: wm_adsp: Separate some ASoC and generic functions
ASoC: wm_adsp: Split DSP power operations into helper functions
ASoC: wm_adsp: Separate generic cs_dsp_coeff_ctl handling
ASoC: wm_adsp: Move check of dsp->running to better place
ASoC: wm_adsp: Pass firmware names as parameters when starting DSP
core
ASoC: wm_adsp: move firmware loading to client
ASoC: wm_adsp: Split out struct cs_dsp from struct wm_adsp
ASoC: wm_adsp: Separate wm_adsp specifics in cs_dsp_client_ops
firmware: cs_dsp: add driver to support firmware loading on Cirrus
Logic DSPs
MAINTAINERS | 11 +
drivers/firmware/Kconfig | 1 +
drivers/firmware/Makefile | 1 +
drivers/firmware/cirrus/Kconfig | 5 +
drivers/firmware/cirrus/Makefile | 3 +
drivers/firmware/cirrus/cs_dsp.c | 3109 ++++++++++++++++
include/linux/firmware/cirrus/cs_dsp.h | 242 ++
.../linux/firmware/cirrus}/wmfw.h | 8 +-
sound/soc/codecs/Kconfig | 1 +
sound/soc/codecs/cs47l15.c | 22 +-
sound/soc/codecs/cs47l24.c | 20 +-
sound/soc/codecs/cs47l35.c | 24 +-
sound/soc/codecs/cs47l85.c | 32 +-
sound/soc/codecs/cs47l90.c | 34 +-
sound/soc/codecs/cs47l92.c | 20 +-
sound/soc/codecs/madera.c | 18 +-
sound/soc/codecs/wm2200.c | 30 +-
sound/soc/codecs/wm5102.c | 16 +-
sound/soc/codecs/wm5110.c | 24 +-
sound/soc/codecs/wm_adsp.c | 3188 ++---------------
sound/soc/codecs/wm_adsp.h | 105 +-
21 files changed, 3794 insertions(+), 3120 deletions(-)
create mode 100644 drivers/firmware/cirrus/Kconfig
create mode 100644 drivers/firmware/cirrus/Makefile
create mode 100644 drivers/firmware/cirrus/cs_dsp.c
create mode 100644 include/linux/firmware/cirrus/cs_dsp.h
rename {sound/soc/codecs => include/linux/firmware/cirrus}/wmfw.h (91%)
--
2.33.0
This commit is contained in:
Mark Brown
Коммит
ca4c040d4a
11
MAINTAINERS
11
MAINTAINERS
|
|
@ -4445,6 +4445,17 @@ L: patches@opensource.cirrus.com
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S: Maintained
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F: sound/soc/codecs/cs*
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CIRRUS LOGIC DSP FIRMWARE DRIVER
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M: Simon Trimmer <simont@opensource.cirrus.com>
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M: Charles Keepax <ckeepax@opensource.cirrus.com>
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M: Richard Fitzgerald <rf@opensource.cirrus.com>
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L: patches@opensource.cirrus.com
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S: Supported
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W: https://github.com/CirrusLogic/linux-drivers/wiki
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T: git https://github.com/CirrusLogic/linux-drivers.git
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F: drivers/firmware/cirrus/*
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F: include/linux/firmware/cirrus/*
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CIRRUS LOGIC EP93XX ETHERNET DRIVER
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M: Hartley Sweeten <hsweeten@visionengravers.com>
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L: netdev@vger.kernel.org
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@ -298,6 +298,7 @@ config TURRIS_MOX_RWTM
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source "drivers/firmware/arm_ffa/Kconfig"
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source "drivers/firmware/broadcom/Kconfig"
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source "drivers/firmware/cirrus/Kconfig"
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source "drivers/firmware/google/Kconfig"
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source "drivers/firmware/efi/Kconfig"
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source "drivers/firmware/imx/Kconfig"
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@ -28,6 +28,7 @@ obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o
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obj-y += arm_ffa/
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obj-y += arm_scmi/
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obj-y += broadcom/
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obj-y += cirrus/
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obj-y += meson/
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obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
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obj-$(CONFIG_EFI) += efi/
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config CS_DSP
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tristate
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default n
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-$(CONFIG_CS_DSP) += cs_dsp.o
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,242 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* cs_dsp.h -- Cirrus Logic DSP firmware support
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*
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* Based on sound/soc/codecs/wm_adsp.h
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*
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* Copyright 2012 Wolfson Microelectronics plc
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* Copyright (C) 2015-2021 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*/
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#ifndef __CS_DSP_H
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#define __CS_DSP_H
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#define CS_ADSP2_REGION_0 BIT(0)
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#define CS_ADSP2_REGION_1 BIT(1)
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#define CS_ADSP2_REGION_2 BIT(2)
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#define CS_ADSP2_REGION_3 BIT(3)
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#define CS_ADSP2_REGION_4 BIT(4)
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#define CS_ADSP2_REGION_5 BIT(5)
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#define CS_ADSP2_REGION_6 BIT(6)
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#define CS_ADSP2_REGION_7 BIT(7)
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#define CS_ADSP2_REGION_8 BIT(8)
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#define CS_ADSP2_REGION_9 BIT(9)
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#define CS_ADSP2_REGION_1_9 (CS_ADSP2_REGION_1 | \
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CS_ADSP2_REGION_2 | CS_ADSP2_REGION_3 | \
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CS_ADSP2_REGION_4 | CS_ADSP2_REGION_5 | \
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CS_ADSP2_REGION_6 | CS_ADSP2_REGION_7 | \
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CS_ADSP2_REGION_8 | CS_ADSP2_REGION_9)
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#define CS_ADSP2_REGION_ALL (CS_ADSP2_REGION_0 | CS_ADSP2_REGION_1_9)
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#define CS_DSP_DATA_WORD_SIZE 3
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#define CS_DSP_ACKED_CTL_TIMEOUT_MS 100
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#define CS_DSP_ACKED_CTL_N_QUICKPOLLS 10
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#define CS_DSP_ACKED_CTL_MIN_VALUE 0
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#define CS_DSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
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/**
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* struct cs_dsp_region - Describes a logical memory region in DSP address space
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* @type: Memory region type
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* @base: Address of region
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*/
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struct cs_dsp_region {
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int type;
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unsigned int base;
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};
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/**
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* struct cs_dsp_alg_region - Describes a logical algorithm region in DSP address space
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* @list: List node for internal use
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* @alg: Algorithm id
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* @type: Memory region type
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* @base: Address of region
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*/
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struct cs_dsp_alg_region {
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struct list_head list;
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unsigned int alg;
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int type;
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unsigned int base;
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};
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/**
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* struct cs_dsp_coeff_ctl - Describes a coefficient control
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* @fw_name: Name of the firmware
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* @subname: Name of the control parsed from the WMFW
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* @subname_len: Length of subname
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* @alg_region: Logical region associated with this control
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* @dsp: DSP instance associated with this control
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* @enabled: Flag indicating whether control is enabled
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* @list: List node for internal use
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* @cache: Cached value of the control
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* @offset: Offset of control within alg_region
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* @len: Length of the cached value
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* @set: Flag indicating the value has been written by the user
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* @flags: Bitfield of WMFW_CTL_FLAG_ control flags defined in wmfw.h
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* @type: One of the WMFW_CTL_TYPE_ control types defined in wmfw.h
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* @priv: For use by the client
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*/
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struct cs_dsp_coeff_ctl {
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const char *fw_name;
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/* Subname is needed to match with firmware */
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const char *subname;
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unsigned int subname_len;
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struct cs_dsp_alg_region alg_region;
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struct cs_dsp *dsp;
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unsigned int enabled:1;
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struct list_head list;
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void *cache;
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unsigned int offset;
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size_t len;
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unsigned int set:1;
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unsigned int flags;
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unsigned int type;
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void *priv;
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};
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struct cs_dsp_ops;
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struct cs_dsp_client_ops;
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/**
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* struct cs_dsp - Configuration and state of a Cirrus Logic DSP
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* @name: The name of the DSP instance
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* @rev: Revision of the DSP
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* @num: DSP instance number
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* @type: Type of DSP
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* @dev: Driver model representation of the device
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* @regmap: Register map of the device
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* @ops: Function pointers for internal callbacks
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* @client_ops: Function pointers for client callbacks
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* @base: Address of the DSP registers
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* @base_sysinfo: Address of the sysinfo register (Halo only)
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* @sysclk_reg: Address of the sysclk register (ADSP1 only)
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* @sysclk_mask: Mask of frequency bits within sysclk register (ADSP1 only)
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* @sysclk_shift: Shift of frequency bits within sysclk register (ADSP1 only)
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* @alg_regions: List of currently loaded algorithm regions
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* @fw_file_name: Filename of the current firmware
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* @fw_name: Name of the current firmware
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* @fw_id: ID of the current firmware, obtained from the wmfw
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* @fw_id_version: Version of the firmware, obtained from the wmfw
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* @fw_vendor_id: Vendor of the firmware, obtained from the wmfw
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* @mem: DSP memory region descriptions
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* @num_mems: Number of memory regions in this DSP
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* @fw_ver: Version of the wmfw file format
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* @booted: Flag indicating DSP has been configured
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* @running: Flag indicating DSP is executing firmware
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* @ctl_list: Controls defined within the loaded DSP firmware
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* @lock_regions: Enable MPU traps on specified memory regions
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* @pwr_lock: Lock used to serialize accesses
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* @debugfs_root: Debugfs directory for this DSP instance
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* @wmfw_file_name: Filename of the currently loaded firmware
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* @bin_file_name: Filename of the currently loaded coefficients
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*/
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struct cs_dsp {
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const char *name;
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int rev;
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int num;
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int type;
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struct device *dev;
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struct regmap *regmap;
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const struct cs_dsp_ops *ops;
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const struct cs_dsp_client_ops *client_ops;
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unsigned int base;
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unsigned int base_sysinfo;
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unsigned int sysclk_reg;
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unsigned int sysclk_mask;
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unsigned int sysclk_shift;
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struct list_head alg_regions;
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const char *fw_name;
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unsigned int fw_id;
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unsigned int fw_id_version;
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unsigned int fw_vendor_id;
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const struct cs_dsp_region *mem;
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int num_mems;
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int fw_ver;
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bool booted;
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bool running;
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struct list_head ctl_list;
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struct mutex pwr_lock;
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unsigned int lock_regions;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs_root;
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char *wmfw_file_name;
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char *bin_file_name;
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#endif
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};
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/**
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* struct cs_dsp_client_ops - client callbacks
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* @control_add: Called under the pwr_lock when a control is created
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* @control_remove: Called under the pwr_lock when a control is destroyed
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* @post_run: Called under the pwr_lock by cs_dsp_run()
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* @post_stop: Called under the pwr_lock by cs_dsp_stop()
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* @watchdog_expired: Called when a watchdog expiry is detected
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*
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* These callbacks give the cs_dsp client an opportunity to respond to events
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* or to perform actions atomically.
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*/
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struct cs_dsp_client_ops {
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int (*control_add)(struct cs_dsp_coeff_ctl *ctl);
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void (*control_remove)(struct cs_dsp_coeff_ctl *ctl);
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int (*post_run)(struct cs_dsp *dsp);
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void (*post_stop)(struct cs_dsp *dsp);
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void (*watchdog_expired)(struct cs_dsp *dsp);
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};
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int cs_dsp_adsp1_init(struct cs_dsp *dsp);
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int cs_dsp_adsp2_init(struct cs_dsp *dsp);
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int cs_dsp_halo_init(struct cs_dsp *dsp);
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int cs_dsp_adsp1_power_up(struct cs_dsp *dsp,
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const struct firmware *wmfw_firmware, char *wmfw_filename,
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const struct firmware *coeff_firmware, char *coeff_filename,
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const char *fw_name);
|
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void cs_dsp_adsp1_power_down(struct cs_dsp *dsp);
|
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int cs_dsp_power_up(struct cs_dsp *dsp,
|
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const struct firmware *wmfw_firmware, char *wmfw_filename,
|
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const struct firmware *coeff_firmware, char *coeff_filename,
|
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const char *fw_name);
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void cs_dsp_power_down(struct cs_dsp *dsp);
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int cs_dsp_run(struct cs_dsp *dsp);
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void cs_dsp_stop(struct cs_dsp *dsp);
|
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|
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void cs_dsp_remove(struct cs_dsp *dsp);
|
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|
||||
int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq);
|
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void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp);
|
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void cs_dsp_halo_bus_error(struct cs_dsp *dsp);
|
||||
void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp);
|
||||
|
||||
void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root);
|
||||
void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp);
|
||||
|
||||
int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int event_id);
|
||||
int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, const void *buf, size_t len);
|
||||
int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, void *buf, size_t len);
|
||||
struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type,
|
||||
unsigned int alg);
|
||||
|
||||
int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr,
|
||||
unsigned int num_words, __be32 *data);
|
||||
int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data);
|
||||
int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data);
|
||||
void cs_dsp_remove_padding(u32 *buf, int nwords);
|
||||
|
||||
struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp,
|
||||
int type, unsigned int id);
|
||||
|
||||
const char *cs_dsp_mem_region_name(unsigned int type);
|
||||
|
||||
#endif
|
||||
|
|
@ -23,10 +23,12 @@
|
|||
#define WMFW_CTL_FLAG_WRITEABLE 0x0002
|
||||
#define WMFW_CTL_FLAG_READABLE 0x0001
|
||||
|
||||
#define WMFW_CTL_TYPE_BYTES 0x0004 /* byte control */
|
||||
|
||||
/* Non-ALSA coefficient types start at 0x1000 */
|
||||
#define WMFW_CTL_TYPE_ACKED ((__force snd_ctl_elem_type_t)0x1000) /* acked control */
|
||||
#define WMFW_CTL_TYPE_HOSTEVENT ((__force snd_ctl_elem_type_t)0x1001) /* event control */
|
||||
#define WMFW_CTL_TYPE_HOST_BUFFER ((__force snd_ctl_elem_type_t)0x1002) /* host buffer pointer */
|
||||
#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */
|
||||
#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */
|
||||
#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */
|
||||
|
||||
struct wmfw_header {
|
||||
char magic[4];
|
||||
|
|
@ -333,6 +333,7 @@ config SND_SOC_WM_HUBS
|
|||
|
||||
config SND_SOC_WM_ADSP
|
||||
tristate
|
||||
select CS_DSP
|
||||
select SND_SOC_COMPRESS
|
||||
default y if SND_SOC_MADERA=y
|
||||
default y if SND_SOC_CS47L24=y
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ struct cs47l15 {
|
|||
bool in1_lp_mode;
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l15_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region cs47l15_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
|
||||
|
|
@ -1402,18 +1402,18 @@ static int cs47l15_probe(struct platform_device *pdev)
|
|||
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
|
||||
|
||||
cs47l15->core.adsp[0].part = "cs47l15";
|
||||
cs47l15->core.adsp[0].num = 1;
|
||||
cs47l15->core.adsp[0].type = WMFW_ADSP2;
|
||||
cs47l15->core.adsp[0].rev = 2;
|
||||
cs47l15->core.adsp[0].dev = madera->dev;
|
||||
cs47l15->core.adsp[0].regmap = madera->regmap_32bit;
|
||||
cs47l15->core.adsp[0].cs_dsp.num = 1;
|
||||
cs47l15->core.adsp[0].cs_dsp.type = WMFW_ADSP2;
|
||||
cs47l15->core.adsp[0].cs_dsp.rev = 2;
|
||||
cs47l15->core.adsp[0].cs_dsp.dev = madera->dev;
|
||||
cs47l15->core.adsp[0].cs_dsp.regmap = madera->regmap_32bit;
|
||||
|
||||
cs47l15->core.adsp[0].base = MADERA_DSP1_CONFIG_1;
|
||||
cs47l15->core.adsp[0].mem = cs47l15_dsp1_regions;
|
||||
cs47l15->core.adsp[0].num_mems = ARRAY_SIZE(cs47l15_dsp1_regions);
|
||||
cs47l15->core.adsp[0].cs_dsp.base = MADERA_DSP1_CONFIG_1;
|
||||
cs47l15->core.adsp[0].cs_dsp.mem = cs47l15_dsp1_regions;
|
||||
cs47l15->core.adsp[0].cs_dsp.num_mems = ARRAY_SIZE(cs47l15_dsp1_regions);
|
||||
|
||||
cs47l15->core.adsp[0].lock_regions =
|
||||
WM_ADSP2_REGION_1 | WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3;
|
||||
cs47l15->core.adsp[0].cs_dsp.lock_regions =
|
||||
CS_ADSP2_REGION_1 | CS_ADSP2_REGION_2 | CS_ADSP2_REGION_3;
|
||||
|
||||
ret = wm_adsp2_init(&cs47l15->core.adsp[0]);
|
||||
if (ret != 0)
|
||||
|
|
|
|||
|
|
@ -37,21 +37,21 @@ struct cs47l24_priv {
|
|||
struct arizona_fll fll[2];
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l24_dsp2_regions[] = {
|
||||
static const struct cs_dsp_region cs47l24_dsp2_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x280000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x290000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x2a8000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l24_dsp3_regions[] = {
|
||||
static const struct cs_dsp_region cs47l24_dsp3_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x380000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x390000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x3a8000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region *cs47l24_dsp_regions[] = {
|
||||
static const struct cs_dsp_region *cs47l24_dsp_regions[] = {
|
||||
cs47l24_dsp2_regions,
|
||||
cs47l24_dsp3_regions,
|
||||
};
|
||||
|
|
@ -1234,15 +1234,15 @@ static int cs47l24_probe(struct platform_device *pdev)
|
|||
|
||||
for (i = 1; i <= 2; i++) {
|
||||
cs47l24->core.adsp[i].part = "cs47l24";
|
||||
cs47l24->core.adsp[i].num = i + 1;
|
||||
cs47l24->core.adsp[i].type = WMFW_ADSP2;
|
||||
cs47l24->core.adsp[i].dev = arizona->dev;
|
||||
cs47l24->core.adsp[i].regmap = arizona->regmap;
|
||||
cs47l24->core.adsp[i].cs_dsp.num = i + 1;
|
||||
cs47l24->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
|
||||
cs47l24->core.adsp[i].cs_dsp.dev = arizona->dev;
|
||||
cs47l24->core.adsp[i].cs_dsp.regmap = arizona->regmap;
|
||||
|
||||
cs47l24->core.adsp[i].base = ARIZONA_DSP1_CONTROL_1 +
|
||||
cs47l24->core.adsp[i].cs_dsp.base = ARIZONA_DSP1_CONTROL_1 +
|
||||
(0x100 * i);
|
||||
cs47l24->core.adsp[i].mem = cs47l24_dsp_regions[i - 1];
|
||||
cs47l24->core.adsp[i].num_mems =
|
||||
cs47l24->core.adsp[i].cs_dsp.mem = cs47l24_dsp_regions[i - 1];
|
||||
cs47l24->core.adsp[i].cs_dsp.num_mems =
|
||||
ARRAY_SIZE(cs47l24_dsp2_regions);
|
||||
|
||||
ret = wm_adsp2_init(&cs47l24->core.adsp[i]);
|
||||
|
|
|
|||
|
|
@ -37,28 +37,28 @@ struct cs47l35 {
|
|||
struct madera_fll fll;
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l35_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region cs47l35_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l35_dsp2_regions[] = {
|
||||
static const struct cs_dsp_region cs47l35_dsp2_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l35_dsp3_regions[] = {
|
||||
static const struct cs_dsp_region cs47l35_dsp3_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region *cs47l35_dsp_regions[] = {
|
||||
static const struct cs_dsp_region *cs47l35_dsp_regions[] = {
|
||||
cs47l35_dsp1_regions,
|
||||
cs47l35_dsp2_regions,
|
||||
cs47l35_dsp3_regions,
|
||||
|
|
@ -1686,15 +1686,15 @@ static int cs47l35_probe(struct platform_device *pdev)
|
|||
|
||||
for (i = 0; i < CS47L35_NUM_ADSP; i++) {
|
||||
cs47l35->core.adsp[i].part = "cs47l35";
|
||||
cs47l35->core.adsp[i].num = i + 1;
|
||||
cs47l35->core.adsp[i].type = WMFW_ADSP2;
|
||||
cs47l35->core.adsp[i].rev = 1;
|
||||
cs47l35->core.adsp[i].dev = madera->dev;
|
||||
cs47l35->core.adsp[i].regmap = madera->regmap_32bit;
|
||||
cs47l35->core.adsp[i].cs_dsp.num = i + 1;
|
||||
cs47l35->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
|
||||
cs47l35->core.adsp[i].cs_dsp.rev = 1;
|
||||
cs47l35->core.adsp[i].cs_dsp.dev = madera->dev;
|
||||
cs47l35->core.adsp[i].cs_dsp.regmap = madera->regmap_32bit;
|
||||
|
||||
cs47l35->core.adsp[i].base = wm_adsp2_control_bases[i];
|
||||
cs47l35->core.adsp[i].mem = cs47l35_dsp_regions[i];
|
||||
cs47l35->core.adsp[i].num_mems =
|
||||
cs47l35->core.adsp[i].cs_dsp.base = wm_adsp2_control_bases[i];
|
||||
cs47l35->core.adsp[i].cs_dsp.mem = cs47l35_dsp_regions[i];
|
||||
cs47l35->core.adsp[i].cs_dsp.num_mems =
|
||||
ARRAY_SIZE(cs47l35_dsp1_regions);
|
||||
|
||||
ret = wm_adsp2_init(&cs47l35->core.adsp[i]);
|
||||
|
|
|
|||
|
|
@ -37,56 +37,56 @@ struct cs47l85 {
|
|||
struct madera_fll fll[3];
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp2_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp2_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp3_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp3_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp4_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp4_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x260000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x220000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x240000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp5_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp5_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x280000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x2e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x2a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x2c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp6_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp6_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x360000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x320000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x340000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l85_dsp7_regions[] = {
|
||||
static const struct cs_dsp_region cs47l85_dsp7_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x380000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x3e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x3a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x3c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region *cs47l85_dsp_regions[] = {
|
||||
static const struct cs_dsp_region *cs47l85_dsp_regions[] = {
|
||||
cs47l85_dsp1_regions,
|
||||
cs47l85_dsp2_regions,
|
||||
cs47l85_dsp3_regions,
|
||||
|
|
@ -2632,15 +2632,15 @@ static int cs47l85_probe(struct platform_device *pdev)
|
|||
|
||||
for (i = 0; i < CS47L85_NUM_ADSP; i++) {
|
||||
cs47l85->core.adsp[i].part = "cs47l85";
|
||||
cs47l85->core.adsp[i].num = i + 1;
|
||||
cs47l85->core.adsp[i].type = WMFW_ADSP2;
|
||||
cs47l85->core.adsp[i].rev = 1;
|
||||
cs47l85->core.adsp[i].dev = madera->dev;
|
||||
cs47l85->core.adsp[i].regmap = madera->regmap_32bit;
|
||||
cs47l85->core.adsp[i].cs_dsp.num = i + 1;
|
||||
cs47l85->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
|
||||
cs47l85->core.adsp[i].cs_dsp.rev = 1;
|
||||
cs47l85->core.adsp[i].cs_dsp.dev = madera->dev;
|
||||
cs47l85->core.adsp[i].cs_dsp.regmap = madera->regmap_32bit;
|
||||
|
||||
cs47l85->core.adsp[i].base = wm_adsp2_control_bases[i];
|
||||
cs47l85->core.adsp[i].mem = cs47l85_dsp_regions[i];
|
||||
cs47l85->core.adsp[i].num_mems =
|
||||
cs47l85->core.adsp[i].cs_dsp.base = wm_adsp2_control_bases[i];
|
||||
cs47l85->core.adsp[i].cs_dsp.mem = cs47l85_dsp_regions[i];
|
||||
cs47l85->core.adsp[i].cs_dsp.num_mems =
|
||||
ARRAY_SIZE(cs47l85_dsp1_regions);
|
||||
|
||||
ret = wm_adsp2_init(&cs47l85->core.adsp[i]);
|
||||
|
|
|
|||
|
|
@ -37,56 +37,56 @@ struct cs47l90 {
|
|||
struct madera_fll fll[3];
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp2_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp2_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp3_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp3_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp4_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp4_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x260000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x220000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x240000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp5_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp5_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x280000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x2e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x2a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x2c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp6_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp6_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x360000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x320000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x340000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l90_dsp7_regions[] = {
|
||||
static const struct cs_dsp_region cs47l90_dsp7_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x380000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x3e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x3a0000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x3c0000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region *cs47l90_dsp_regions[] = {
|
||||
static const struct cs_dsp_region *cs47l90_dsp_regions[] = {
|
||||
cs47l90_dsp1_regions,
|
||||
cs47l90_dsp2_regions,
|
||||
cs47l90_dsp3_regions,
|
||||
|
|
@ -2543,18 +2543,18 @@ static int cs47l90_probe(struct platform_device *pdev)
|
|||
|
||||
for (i = 0; i < CS47L90_NUM_ADSP; i++) {
|
||||
cs47l90->core.adsp[i].part = "cs47l90";
|
||||
cs47l90->core.adsp[i].num = i + 1;
|
||||
cs47l90->core.adsp[i].type = WMFW_ADSP2;
|
||||
cs47l90->core.adsp[i].rev = 2;
|
||||
cs47l90->core.adsp[i].dev = madera->dev;
|
||||
cs47l90->core.adsp[i].regmap = madera->regmap_32bit;
|
||||
cs47l90->core.adsp[i].cs_dsp.num = i + 1;
|
||||
cs47l90->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
|
||||
cs47l90->core.adsp[i].cs_dsp.rev = 2;
|
||||
cs47l90->core.adsp[i].cs_dsp.dev = madera->dev;
|
||||
cs47l90->core.adsp[i].cs_dsp.regmap = madera->regmap_32bit;
|
||||
|
||||
cs47l90->core.adsp[i].base = cs47l90_dsp_control_bases[i];
|
||||
cs47l90->core.adsp[i].mem = cs47l90_dsp_regions[i];
|
||||
cs47l90->core.adsp[i].num_mems =
|
||||
cs47l90->core.adsp[i].cs_dsp.base = cs47l90_dsp_control_bases[i];
|
||||
cs47l90->core.adsp[i].cs_dsp.mem = cs47l90_dsp_regions[i];
|
||||
cs47l90->core.adsp[i].cs_dsp.num_mems =
|
||||
ARRAY_SIZE(cs47l90_dsp1_regions);
|
||||
|
||||
cs47l90->core.adsp[i].lock_regions = WM_ADSP2_REGION_1_9;
|
||||
cs47l90->core.adsp[i].cs_dsp.lock_regions = CS_ADSP2_REGION_1_9;
|
||||
|
||||
ret = wm_adsp2_init(&cs47l90->core.adsp[i]);
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ struct cs47l92 {
|
|||
struct madera_fll fll[2];
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region cs47l92_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region cs47l92_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
|
||||
|
|
@ -2002,17 +2002,17 @@ static int cs47l92_probe(struct platform_device *pdev)
|
|||
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
|
||||
|
||||
cs47l92->core.adsp[0].part = "cs47l92";
|
||||
cs47l92->core.adsp[0].num = 1;
|
||||
cs47l92->core.adsp[0].type = WMFW_ADSP2;
|
||||
cs47l92->core.adsp[0].rev = 2;
|
||||
cs47l92->core.adsp[0].dev = madera->dev;
|
||||
cs47l92->core.adsp[0].regmap = madera->regmap_32bit;
|
||||
cs47l92->core.adsp[0].cs_dsp.num = 1;
|
||||
cs47l92->core.adsp[0].cs_dsp.type = WMFW_ADSP2;
|
||||
cs47l92->core.adsp[0].cs_dsp.rev = 2;
|
||||
cs47l92->core.adsp[0].cs_dsp.dev = madera->dev;
|
||||
cs47l92->core.adsp[0].cs_dsp.regmap = madera->regmap_32bit;
|
||||
|
||||
cs47l92->core.adsp[0].base = MADERA_DSP1_CONFIG_1;
|
||||
cs47l92->core.adsp[0].mem = cs47l92_dsp1_regions;
|
||||
cs47l92->core.adsp[0].num_mems = ARRAY_SIZE(cs47l92_dsp1_regions);
|
||||
cs47l92->core.adsp[0].cs_dsp.base = MADERA_DSP1_CONFIG_1;
|
||||
cs47l92->core.adsp[0].cs_dsp.mem = cs47l92_dsp1_regions;
|
||||
cs47l92->core.adsp[0].cs_dsp.num_mems = ARRAY_SIZE(cs47l92_dsp1_regions);
|
||||
|
||||
cs47l92->core.adsp[0].lock_regions = WM_ADSP2_REGION_1_9;
|
||||
cs47l92->core.adsp[0].cs_dsp.lock_regions = CS_ADSP2_REGION_1_9;
|
||||
|
||||
ret = wm_adsp2_init(&cs47l92->core.adsp[0]);
|
||||
if (ret != 0)
|
||||
|
|
|
|||
|
|
@ -905,7 +905,7 @@ static int madera_adsp_rate_put(struct snd_kcontrol *kcontrol,
|
|||
*/
|
||||
mutex_lock(&priv->rate_lock);
|
||||
|
||||
if (!madera_can_change_grp_rate(priv, priv->adsp[adsp_num].base)) {
|
||||
if (!madera_can_change_grp_rate(priv, priv->adsp[adsp_num].cs_dsp.base)) {
|
||||
dev_warn(priv->madera->dev,
|
||||
"Cannot change '%s' while in use by active audio paths\n",
|
||||
kcontrol->id.name);
|
||||
|
|
@ -964,7 +964,7 @@ static int madera_write_adsp_clk_setting(struct madera_priv *priv,
|
|||
unsigned int mask = MADERA_DSP_RATE_MASK;
|
||||
int ret;
|
||||
|
||||
val = priv->adsp_rate_cache[dsp->num - 1] << MADERA_DSP_RATE_SHIFT;
|
||||
val = priv->adsp_rate_cache[dsp->cs_dsp.num - 1] << MADERA_DSP_RATE_SHIFT;
|
||||
|
||||
switch (priv->madera->type) {
|
||||
case CS47L35:
|
||||
|
|
@ -978,15 +978,15 @@ static int madera_write_adsp_clk_setting(struct madera_priv *priv,
|
|||
/* Configure exact dsp frequency */
|
||||
dev_dbg(priv->madera->dev, "Set DSP frequency to 0x%x\n", freq);
|
||||
|
||||
ret = regmap_write(dsp->regmap,
|
||||
dsp->base + MADERA_DSP_CONFIG_2_OFFS, freq);
|
||||
ret = regmap_write(dsp->cs_dsp.regmap,
|
||||
dsp->cs_dsp.base + MADERA_DSP_CONFIG_2_OFFS, freq);
|
||||
if (ret)
|
||||
goto err;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(dsp->regmap,
|
||||
dsp->base + MADERA_DSP_CONFIG_1_OFFS,
|
||||
ret = regmap_update_bits(dsp->cs_dsp.regmap,
|
||||
dsp->cs_dsp.base + MADERA_DSP_CONFIG_1_OFFS,
|
||||
mask, val);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
|
@ -996,7 +996,7 @@ static int madera_write_adsp_clk_setting(struct madera_priv *priv,
|
|||
return 0;
|
||||
|
||||
err:
|
||||
dev_err(dsp->dev, "Failed to set DSP%d clock: %d\n", dsp->num, ret);
|
||||
dev_err(dsp->cs_dsp.dev, "Failed to set DSP%d clock: %d\n", dsp->cs_dsp.num, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1018,7 +1018,7 @@ int madera_set_adsp_clk(struct madera_priv *priv, int dsp_num,
|
|||
* changes are locked out by the domain_group_ref reference count.
|
||||
*/
|
||||
|
||||
ret = regmap_read(dsp->regmap, dsp->base, &cur);
|
||||
ret = regmap_read(dsp->cs_dsp.regmap, dsp->cs_dsp.base, &cur);
|
||||
if (ret) {
|
||||
dev_err(madera->dev,
|
||||
"Failed to read current DSP rate: %d\n", ret);
|
||||
|
|
@ -1027,7 +1027,7 @@ int madera_set_adsp_clk(struct madera_priv *priv, int dsp_num,
|
|||
|
||||
cur &= MADERA_DSP_RATE_MASK;
|
||||
|
||||
new = priv->adsp_rate_cache[dsp->num - 1] << MADERA_DSP_RATE_SHIFT;
|
||||
new = priv->adsp_rate_cache[dsp->cs_dsp.num - 1] << MADERA_DSP_RATE_SHIFT;
|
||||
|
||||
if (new == cur) {
|
||||
dev_dbg(madera->dev, "DSP rate not changed\n");
|
||||
|
|
|
|||
|
|
@ -145,13 +145,13 @@ static const struct regmap_range_cfg wm2200_ranges[] = {
|
|||
.window_start = WM2200_DSP2_ZM_0, .window_len = 1024, },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region wm2200_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region wm2200_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP1_PM, .base = WM2200_DSP1_PM_BASE },
|
||||
{ .type = WMFW_ADSP1_DM, .base = WM2200_DSP1_DM_BASE },
|
||||
{ .type = WMFW_ADSP1_ZM, .base = WM2200_DSP1_ZM_BASE },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region wm2200_dsp2_regions[] = {
|
||||
static const struct cs_dsp_region wm2200_dsp2_regions[] = {
|
||||
{ .type = WMFW_ADSP1_PM, .base = WM2200_DSP2_PM_BASE },
|
||||
{ .type = WMFW_ADSP1_DM, .base = WM2200_DSP2_DM_BASE },
|
||||
{ .type = WMFW_ADSP1_ZM, .base = WM2200_DSP2_ZM_BASE },
|
||||
|
|
@ -2202,23 +2202,23 @@ static int wm2200_i2c_probe(struct i2c_client *i2c,
|
|||
}
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
wm2200->dsp[i].type = WMFW_ADSP1;
|
||||
wm2200->dsp[i].cs_dsp.type = WMFW_ADSP1;
|
||||
wm2200->dsp[i].part = "wm2200";
|
||||
wm2200->dsp[i].num = i + 1;
|
||||
wm2200->dsp[i].dev = &i2c->dev;
|
||||
wm2200->dsp[i].regmap = wm2200->regmap;
|
||||
wm2200->dsp[i].sysclk_reg = WM2200_CLOCKING_3;
|
||||
wm2200->dsp[i].sysclk_mask = WM2200_SYSCLK_FREQ_MASK;
|
||||
wm2200->dsp[i].sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT;
|
||||
wm2200->dsp[i].cs_dsp.num = i + 1;
|
||||
wm2200->dsp[i].cs_dsp.dev = &i2c->dev;
|
||||
wm2200->dsp[i].cs_dsp.regmap = wm2200->regmap;
|
||||
wm2200->dsp[i].cs_dsp.sysclk_reg = WM2200_CLOCKING_3;
|
||||
wm2200->dsp[i].cs_dsp.sysclk_mask = WM2200_SYSCLK_FREQ_MASK;
|
||||
wm2200->dsp[i].cs_dsp.sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT;
|
||||
}
|
||||
|
||||
wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1;
|
||||
wm2200->dsp[0].mem = wm2200_dsp1_regions;
|
||||
wm2200->dsp[0].num_mems = ARRAY_SIZE(wm2200_dsp1_regions);
|
||||
wm2200->dsp[0].cs_dsp.base = WM2200_DSP1_CONTROL_1;
|
||||
wm2200->dsp[0].cs_dsp.mem = wm2200_dsp1_regions;
|
||||
wm2200->dsp[0].cs_dsp.num_mems = ARRAY_SIZE(wm2200_dsp1_regions);
|
||||
|
||||
wm2200->dsp[1].base = WM2200_DSP2_CONTROL_1;
|
||||
wm2200->dsp[1].mem = wm2200_dsp2_regions;
|
||||
wm2200->dsp[1].num_mems = ARRAY_SIZE(wm2200_dsp2_regions);
|
||||
wm2200->dsp[1].cs_dsp.base = WM2200_DSP2_CONTROL_1;
|
||||
wm2200->dsp[1].cs_dsp.mem = wm2200_dsp2_regions;
|
||||
wm2200->dsp[1].cs_dsp.num_mems = ARRAY_SIZE(wm2200_dsp2_regions);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wm2200->dsp); i++)
|
||||
wm_adsp1_init(&wm2200->dsp[i]);
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
|
|||
static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
|
||||
static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
|
||||
|
||||
static const struct wm_adsp_region wm5102_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region wm5102_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x180000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x190000 },
|
||||
|
|
@ -2046,13 +2046,13 @@ static int wm5102_probe(struct platform_device *pdev)
|
|||
arizona_init_dvfs(&wm5102->core);
|
||||
|
||||
wm5102->core.adsp[0].part = "wm5102";
|
||||
wm5102->core.adsp[0].num = 1;
|
||||
wm5102->core.adsp[0].type = WMFW_ADSP2;
|
||||
wm5102->core.adsp[0].base = ARIZONA_DSP1_CONTROL_1;
|
||||
wm5102->core.adsp[0].dev = arizona->dev;
|
||||
wm5102->core.adsp[0].regmap = arizona->regmap;
|
||||
wm5102->core.adsp[0].mem = wm5102_dsp1_regions;
|
||||
wm5102->core.adsp[0].num_mems = ARRAY_SIZE(wm5102_dsp1_regions);
|
||||
wm5102->core.adsp[0].cs_dsp.num = 1;
|
||||
wm5102->core.adsp[0].cs_dsp.type = WMFW_ADSP2;
|
||||
wm5102->core.adsp[0].cs_dsp.base = ARIZONA_DSP1_CONTROL_1;
|
||||
wm5102->core.adsp[0].cs_dsp.dev = arizona->dev;
|
||||
wm5102->core.adsp[0].cs_dsp.regmap = arizona->regmap;
|
||||
wm5102->core.adsp[0].cs_dsp.mem = wm5102_dsp1_regions;
|
||||
wm5102->core.adsp[0].cs_dsp.num_mems = ARRAY_SIZE(wm5102_dsp1_regions);
|
||||
|
||||
ret = wm_adsp2_init(&wm5102->core.adsp[0]);
|
||||
if (ret != 0)
|
||||
|
|
|
|||
|
|
@ -45,35 +45,35 @@ struct wm5110_priv {
|
|||
unsigned int in_pga_cache[6];
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region wm5110_dsp1_regions[] = {
|
||||
static const struct cs_dsp_region wm5110_dsp1_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x180000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x190000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x1a8000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region wm5110_dsp2_regions[] = {
|
||||
static const struct cs_dsp_region wm5110_dsp2_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x280000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x290000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x2a8000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region wm5110_dsp3_regions[] = {
|
||||
static const struct cs_dsp_region wm5110_dsp3_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x380000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x390000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x3a8000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region wm5110_dsp4_regions[] = {
|
||||
static const struct cs_dsp_region wm5110_dsp4_regions[] = {
|
||||
{ .type = WMFW_ADSP2_PM, .base = 0x400000 },
|
||||
{ .type = WMFW_ADSP2_ZM, .base = 0x480000 },
|
||||
{ .type = WMFW_ADSP2_XM, .base = 0x490000 },
|
||||
{ .type = WMFW_ADSP2_YM, .base = 0x4a8000 },
|
||||
};
|
||||
|
||||
static const struct wm_adsp_region *wm5110_dsp_regions[] = {
|
||||
static const struct cs_dsp_region *wm5110_dsp_regions[] = {
|
||||
wm5110_dsp1_regions,
|
||||
wm5110_dsp2_regions,
|
||||
wm5110_dsp3_regions,
|
||||
|
|
@ -2409,15 +2409,15 @@ static int wm5110_probe(struct platform_device *pdev)
|
|||
|
||||
for (i = 0; i < WM5110_NUM_ADSP; i++) {
|
||||
wm5110->core.adsp[i].part = "wm5110";
|
||||
wm5110->core.adsp[i].num = i + 1;
|
||||
wm5110->core.adsp[i].type = WMFW_ADSP2;
|
||||
wm5110->core.adsp[i].dev = arizona->dev;
|
||||
wm5110->core.adsp[i].regmap = arizona->regmap;
|
||||
wm5110->core.adsp[i].cs_dsp.num = i + 1;
|
||||
wm5110->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
|
||||
wm5110->core.adsp[i].cs_dsp.dev = arizona->dev;
|
||||
wm5110->core.adsp[i].cs_dsp.regmap = arizona->regmap;
|
||||
|
||||
wm5110->core.adsp[i].base = ARIZONA_DSP1_CONTROL_1
|
||||
wm5110->core.adsp[i].cs_dsp.base = ARIZONA_DSP1_CONTROL_1
|
||||
+ (0x100 * i);
|
||||
wm5110->core.adsp[i].mem = wm5110_dsp_regions[i];
|
||||
wm5110->core.adsp[i].num_mems
|
||||
wm5110->core.adsp[i].cs_dsp.mem = wm5110_dsp_regions[i];
|
||||
wm5110->core.adsp[i].cs_dsp.num_mems
|
||||
= ARRAY_SIZE(wm5110_dsp1_regions);
|
||||
|
||||
ret = wm_adsp2_init(&wm5110->core.adsp[i]);
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -10,128 +10,37 @@
|
|||
#ifndef __WM_ADSP_H
|
||||
#define __WM_ADSP_H
|
||||
|
||||
#include <linux/firmware/cirrus/cs_dsp.h>
|
||||
#include <linux/firmware/cirrus/wmfw.h>
|
||||
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dapm.h>
|
||||
#include <sound/compress_driver.h>
|
||||
|
||||
#include "wmfw.h"
|
||||
|
||||
/* Return values for wm_adsp_compr_handle_irq */
|
||||
#define WM_ADSP_COMPR_OK 0
|
||||
#define WM_ADSP_COMPR_VOICE_TRIGGER 1
|
||||
|
||||
#define WM_ADSP2_REGION_0 BIT(0)
|
||||
#define WM_ADSP2_REGION_1 BIT(1)
|
||||
#define WM_ADSP2_REGION_2 BIT(2)
|
||||
#define WM_ADSP2_REGION_3 BIT(3)
|
||||
#define WM_ADSP2_REGION_4 BIT(4)
|
||||
#define WM_ADSP2_REGION_5 BIT(5)
|
||||
#define WM_ADSP2_REGION_6 BIT(6)
|
||||
#define WM_ADSP2_REGION_7 BIT(7)
|
||||
#define WM_ADSP2_REGION_8 BIT(8)
|
||||
#define WM_ADSP2_REGION_9 BIT(9)
|
||||
#define WM_ADSP2_REGION_1_9 (WM_ADSP2_REGION_1 | \
|
||||
WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \
|
||||
WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | \
|
||||
WM_ADSP2_REGION_6 | WM_ADSP2_REGION_7 | \
|
||||
WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9)
|
||||
#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9)
|
||||
|
||||
struct wm_adsp_region {
|
||||
int type;
|
||||
unsigned int base;
|
||||
};
|
||||
|
||||
struct wm_adsp_alg_region {
|
||||
struct list_head list;
|
||||
unsigned int alg;
|
||||
int type;
|
||||
unsigned int base;
|
||||
};
|
||||
|
||||
struct wm_adsp_compr;
|
||||
struct wm_adsp_compr_buf;
|
||||
struct wm_adsp_ops;
|
||||
|
||||
struct wm_adsp {
|
||||
struct cs_dsp cs_dsp;
|
||||
const char *part;
|
||||
const char *name;
|
||||
const char *fwf_name;
|
||||
int rev;
|
||||
int num;
|
||||
int type;
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct snd_soc_component *component;
|
||||
|
||||
const struct wm_adsp_ops *ops;
|
||||
|
||||
unsigned int base;
|
||||
unsigned int base_sysinfo;
|
||||
unsigned int sysclk_reg;
|
||||
unsigned int sysclk_mask;
|
||||
unsigned int sysclk_shift;
|
||||
|
||||
struct list_head alg_regions;
|
||||
|
||||
unsigned int fw_id;
|
||||
unsigned int fw_id_version;
|
||||
unsigned int fw_vendor_id;
|
||||
|
||||
const struct wm_adsp_region *mem;
|
||||
int num_mems;
|
||||
unsigned int sys_config_size;
|
||||
|
||||
int fw;
|
||||
int fw_ver;
|
||||
|
||||
bool preloaded;
|
||||
bool booted;
|
||||
bool running;
|
||||
bool fatal_error;
|
||||
|
||||
struct list_head ctl_list;
|
||||
|
||||
struct work_struct boot_work;
|
||||
|
||||
bool preloaded;
|
||||
bool fatal_error;
|
||||
|
||||
struct list_head compr_list;
|
||||
struct list_head buffer_list;
|
||||
|
||||
struct mutex pwr_lock;
|
||||
|
||||
unsigned int lock_regions;
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *debugfs_root;
|
||||
char *wmfw_file_name;
|
||||
char *bin_file_name;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
struct wm_adsp_ops {
|
||||
unsigned int sys_config_size;
|
||||
|
||||
bool (*validate_version)(struct wm_adsp *dsp, unsigned int version);
|
||||
unsigned int (*parse_sizes)(struct wm_adsp *dsp,
|
||||
const char * const file,
|
||||
unsigned int pos,
|
||||
const struct firmware *firmware);
|
||||
int (*setup_algs)(struct wm_adsp *dsp);
|
||||
unsigned int (*region_to_reg)(struct wm_adsp_region const *mem,
|
||||
unsigned int offset);
|
||||
|
||||
void (*show_fw_status)(struct wm_adsp *dsp);
|
||||
void (*stop_watchdog)(struct wm_adsp *dsp);
|
||||
|
||||
int (*enable_memory)(struct wm_adsp *dsp);
|
||||
void (*disable_memory)(struct wm_adsp *dsp);
|
||||
int (*lock_memory)(struct wm_adsp *dsp, unsigned int lock_regions);
|
||||
|
||||
int (*enable_core)(struct wm_adsp *dsp);
|
||||
void (*disable_core)(struct wm_adsp *dsp);
|
||||
|
||||
int (*start_core)(struct wm_adsp *dsp);
|
||||
void (*stop_core)(struct wm_adsp *dsp);
|
||||
};
|
||||
|
||||
#define WM_ADSP1(wname, num) \
|
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|
|
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Ссылка в новой задаче