powerpc/44x: Support 16K/64K base page sizes on 44x
This adds support for 16k and 64k page sizes on PowerPC 44x processors. The PGDIR table is much smaller than a page when using 16k or 64k pages (512 and 32 bytes respectively) so we allocate the PGDIR with kzalloc() instead of __get_free_pages(). One PTE table covers rather a large memory area when using 16k or 64k pages (32MB or 512MB respectively), so we can easily put FIXMAP and PKMAP in the area covered by one PTE table. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Vladimir Panfilov <pvr@emcraft.com> Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Ilya Yanok
Paul Mackerras
Родитель
6ca4f7494b
Коммит
ca9153a3a2
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@ -405,23 +405,53 @@ config PPC_HAS_HASH_64K
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depends on PPC64
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default n
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config PPC_64K_PAGES
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bool "64k page size"
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depends on PPC64
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select PPC_HAS_HASH_64K
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choice
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prompt "Page size"
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default PPC_4K_PAGES
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help
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This option changes the kernel logical page size to 64k. On machines
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without processor support for 64k pages, the kernel will simulate
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them by loading each individual 4k page on demand transparently,
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while on hardware with such support, it will be used to map
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normal application pages.
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Select the kernel logical page size. Increasing the page size
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will reduce software overhead at each page boundary, allow
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hardware prefetch mechanisms to be more effective, and allow
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larger dma transfers increasing IO efficiency and reducing
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overhead. However the utilization of memory will increase.
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For example, each cached file will using a multiple of the
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page size to hold its contents and the difference between the
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end of file and the end of page is wasted.
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Some dedicated systems, such as software raid serving with
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accelerated calculations, have shown significant increases.
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If you configure a 64 bit kernel for 64k pages but the
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processor does not support them, then the kernel will simulate
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them with 4k pages, loading them on demand, but with the
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reduced software overhead and larger internal fragmentation.
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For the 32 bit kernel, a large page option will not be offered
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unless it is supported by the configured processor.
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If unsure, choose 4K_PAGES.
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config PPC_4K_PAGES
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bool "4k page size"
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config PPC_16K_PAGES
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bool "16k page size" if 44x
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config PPC_64K_PAGES
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bool "64k page size" if 44x || PPC_STD_MMU_64
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select PPC_HAS_HASH_64K if PPC_STD_MMU_64
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endchoice
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config FORCE_MAX_ZONEORDER
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int "Maximum zone order"
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range 9 64 if PPC_64K_PAGES
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default "9" if PPC_64K_PAGES
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range 13 64 if PPC64 && !PPC_64K_PAGES
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default "13" if PPC64 && !PPC_64K_PAGES
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range 9 64 if PPC_STD_MMU_64 && PPC_64K_PAGES
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default "9" if PPC_STD_MMU_64 && PPC_64K_PAGES
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range 13 64 if PPC_STD_MMU_64 && !PPC_64K_PAGES
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default "13" if PPC_STD_MMU_64 && !PPC_64K_PAGES
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range 9 64 if PPC_STD_MMU_32 && PPC_16K_PAGES
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default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES
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range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES
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default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES
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range 11 64
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default "11"
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help
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@ -441,7 +471,7 @@ config FORCE_MAX_ZONEORDER
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config PPC_SUBPAGE_PROT
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bool "Support setting protections for 4k subpages"
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depends on PPC_64K_PAGES
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depends on PPC_STD_MMU_64 && PPC_64K_PAGES
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help
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This option adds support for a system call to allow user programs
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to set access permissions (read/write, readonly, or no access)
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@ -38,9 +38,24 @@ extern pte_t *pkmap_page_table;
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* easily, subsequent pte tables have to be allocated in one physical
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* chunk of RAM.
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*/
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#define LAST_PKMAP (1 << PTE_SHIFT)
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#define LAST_PKMAP_MASK (LAST_PKMAP-1)
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/*
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* We use one full pte table with 4K pages. And with 16K/64K pages pte
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* table covers enough memory (32MB and 512MB resp.) that both FIXMAP
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* and PKMAP can be placed in single pte table. We use 1024 pages for
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* PKMAP in case of 16K/64K pages.
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*/
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#ifdef CONFIG_PPC_4K_PAGES
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#define PKMAP_ORDER PTE_SHIFT
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#else
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#define PKMAP_ORDER 10
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#endif
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#define LAST_PKMAP (1 << PKMAP_ORDER)
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#ifndef CONFIG_PPC_4K_PAGES
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#define PKMAP_BASE (FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1))
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#else
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#define PKMAP_BASE ((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)
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#endif
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#define LAST_PKMAP_MASK (LAST_PKMAP-1)
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#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
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#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
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@ -4,6 +4,8 @@
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* PPC440 support
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*/
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#include <asm/page.h>
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#define PPC44x_MMUCR_TID 0x000000ff
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#define PPC44x_MMUCR_STS 0x00010000
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@ -74,4 +76,19 @@ typedef struct {
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/* Size of the TLBs used for pinning in lowmem */
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#define PPC_PIN_SIZE (1 << 28) /* 256M */
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#if (PAGE_SHIFT == 12)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_4K
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#elif (PAGE_SHIFT == 14)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_16K
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#elif (PAGE_SHIFT == 16)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_64K
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#else
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#error "Unsupported PAGE_SIZE"
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#endif
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#define PPC44x_PGD_OFF_SHIFT (32 - PGDIR_SHIFT + PGD_T_LOG2)
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#define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2)
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#define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
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#define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT)
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#endif /* _ASM_POWERPC_MMU_44X_H_ */
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@ -19,12 +19,15 @@
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#include <asm/kdump.h>
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/*
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* On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
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* On regular PPC32 page size is 4K (but we support 4K/16K/64K pages
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* on PPC44x). For PPC64 we support either 4K or 64K software
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* page size. When using 64K pages however, whether we are really supporting
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* 64K pages in HW or not is irrelevant to those definitions.
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*/
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#ifdef CONFIG_PPC_64K_PAGES
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#if defined(CONFIG_PPC_64K_PAGES)
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#define PAGE_SHIFT 16
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#elif defined(CONFIG_PPC_16K_PAGES)
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#define PAGE_SHIFT 14
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#else
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#define PAGE_SHIFT 12
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#endif
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@ -151,7 +154,7 @@ typedef struct { pte_basic_t pte; } pte_t;
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/* 64k pages additionally define a bigger "real PTE" type that gathers
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* the "second half" part of the PTE for pseudo 64k pages
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*/
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#ifdef CONFIG_PPC_64K_PAGES
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#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
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typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
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#else
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typedef struct { pte_t pte; } real_pte_t;
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@ -191,10 +194,10 @@ typedef pte_basic_t pte_t;
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#define pte_val(x) (x)
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#define __pte(x) (x)
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#ifdef CONFIG_PPC_64K_PAGES
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#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
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typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
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#else
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typedef unsigned long real_pte_t;
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typedef pte_t real_pte_t;
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#endif
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@ -19,6 +19,8 @@
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#define PTE_FLAGS_OFFSET 0
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#endif
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#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
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#ifndef __ASSEMBLY__
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/*
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* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
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@ -26,10 +28,8 @@
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*/
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#ifdef CONFIG_PTE_64BIT
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typedef unsigned long long pte_basic_t;
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#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */
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#else
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typedef unsigned long pte_basic_t;
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#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
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#endif
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struct page;
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@ -39,6 +39,9 @@ extern void copy_page(void *to, void *from);
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#include <asm-generic/page.h>
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#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
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#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PAGE_32_H */
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@ -380,6 +380,10 @@ int main(void)
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DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
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DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
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#endif
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#ifdef CONFIG_44x
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DEFINE(PGD_T_LOG2, PGD_T_LOG2);
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DEFINE(PTE_T_LOG2, PTE_T_LOG2);
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#endif
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return 0;
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}
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@ -402,12 +402,14 @@ interrupt_base:
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rlwimi r13,r12,10,30,30
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/* Load the PTE */
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rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
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/* Compute pgdir/pmd offset */
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rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
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lwzx r11, r12, r11 /* Get pgd/pmd entry */
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rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
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/* Compute pte address */
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rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
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lwz r11, 0(r12) /* Get high word of pte entry */
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lwz r12, 4(r12) /* Get low word of pte entry */
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@ -496,12 +498,14 @@ tlb_44x_patch_hwater_D:
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/* Make up the required permissions */
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
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rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
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/* Compute pgdir/pmd offset */
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rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
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lwzx r11, r12, r11 /* Get pgd/pmd entry */
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rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
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/* Compute pte address */
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rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
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lwz r11, 0(r12) /* Get high word of pte entry */
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lwz r12, 4(r12) /* Get low word of pte entry */
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@ -565,15 +569,16 @@ tlb_44x_patch_hwater_I:
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*/
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finish_tlb_load:
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/* Combine RPN & ERPN an write WS 0 */
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rlwimi r11,r12,0,0,19
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rlwimi r11,r12,0,0,31-PAGE_SHIFT
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tlbwe r11,r13,PPC44x_TLB_XLAT
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/*
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* Create WS1. This is the faulting address (EPN),
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* page size, and valid flag.
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*/
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li r11,PPC44x_TLB_VALID | PPC44x_TLB_4K
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rlwimi r10,r11,0,20,31 /* Insert valid and page size*/
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li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
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/* Insert valid and page size */
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rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
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tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
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/* And WS 2 */
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@ -645,12 +650,12 @@ _GLOBAL(set_context)
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* goes at the beginning of the data segment, which is page-aligned.
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*/
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.data
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.align 12
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.align PAGE_SHIFT
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.globl sdata
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sdata:
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.globl empty_zero_page
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empty_zero_page:
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.space 4096
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.space PAGE_SIZE
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/*
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* To support >32-bit physical addresses, we use an 8KB pgdir.
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@ -426,8 +426,8 @@ _GLOBAL(__flush_dcache_icache)
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BEGIN_FTR_SECTION
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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rlwinm r3,r3,0,0,19 /* Get page base address */
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li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
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rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
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li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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@ -467,8 +467,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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rlwinm r0,r10,0,28,26 /* clear DR */
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mtmsr r0
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isync
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rlwinm r3,r3,0,0,19 /* Get page base address */
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li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
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rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
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li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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@ -492,7 +492,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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* void clear_pages(void *page, int order) ;
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*/
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_GLOBAL(clear_pages)
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li r0,4096/L1_CACHE_BYTES
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li r0,PAGE_SIZE/L1_CACHE_BYTES
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slw r0,r0,r4
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mtctr r0
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#ifdef CONFIG_8xx
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@ -550,7 +550,7 @@ _GLOBAL(copy_page)
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dcbt r5,r4
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li r11,L1_CACHE_BYTES+4
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#endif /* MAX_COPY_PREFETCH */
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li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
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li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
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crclr 4*cr0+eq
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2:
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mtctr r0
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@ -68,24 +68,29 @@ extern unsigned long p_mapped_by_tlbcam(unsigned long pa);
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#define p_mapped_by_tlbcam(x) (0UL)
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#endif /* HAVE_TLBCAM */
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#ifdef CONFIG_PTE_64BIT
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/* Some processors use an 8kB pgdir because they have 8-byte Linux PTEs. */
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#define PGDIR_ORDER 1
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#else
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#define PGDIR_ORDER 0
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#endif
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#define PGDIR_ORDER (32 + PGD_T_LOG2 - PGDIR_SHIFT)
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pgd_t *pgd_alloc(struct mm_struct *mm)
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{
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pgd_t *ret;
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ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGDIR_ORDER);
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/* pgdir take page or two with 4K pages and a page fraction otherwise */
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#ifndef CONFIG_PPC_4K_PAGES
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ret = (pgd_t *)kzalloc(1 << PGDIR_ORDER, GFP_KERNEL);
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#else
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ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
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PGDIR_ORDER - PAGE_SHIFT);
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#endif
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return ret;
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}
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void pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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free_pages((unsigned long)pgd, PGDIR_ORDER);
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#ifndef CONFIG_PPC_4K_PAGES
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kfree((void *)pgd);
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#else
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free_pages((unsigned long)pgd, PGDIR_ORDER - PAGE_SHIFT);
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#endif
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}
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__init_refok pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
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@ -385,7 +390,7 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
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#endif /* CONFIG_DEBUG_PAGEALLOC */
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static int fixmaps;
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unsigned long FIXADDR_TOP = 0xfffff000;
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unsigned long FIXADDR_TOP = (-PAGE_SIZE);
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EXPORT_SYMBOL(FIXADDR_TOP);
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void __set_fixmap (enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags)
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@ -212,7 +212,7 @@ config PPC_MMU_NOHASH
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config PPC_MM_SLICES
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bool
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default y if HUGETLB_PAGE || PPC_64K_PAGES
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default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES)
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default n
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config VIRT_CPU_ACCOUNTING
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Загрузка…
Ссылка в новой задаче