drm/i915: fixup interlaced vertical timings confusion, part 1
We have a pretty decent confusion about vertical timings of interlaced modes. Peter Ross has written a patch that makes interlace modes work on a lot more platforms/output combinations by doubling the vertical timings. The issue with that patch is that core drm _does_ support specifying whether we want these vertical timings in fields or frames, we just haven't managed to consistently use this facility. The relavant function is drm_mode_set_crtcinfo, which fills in the crtc timing information. The first thing to note is that the drm core keeps interlaced modes in frames, but displays modelines in fields. So when the crtc modeset helper copies over the mode into adjusted_mode it will already contain vertical timings in half-frames. The result is that the fixup code in intel_crtc_mode_fixup doesn't actually do anything (in most cases at least). Now gen3+ natively supports interlaced modes and wants the vertical timings in frames. Which is what sdvo already fixes up, at least under some conditions. There are a few other place that demand vertical timings in fields but never actually deal with interlaced modes, so use frame timings for consistency, too. These are: - lvds panel, - dvo encoders - dvo is the only way gen2 could support interlaced mode, but currently we don't support any encoders that do. - tv out - despite that the tv dac sends out an interlaced signal it expects a progressive mode pipe configuration. All these encoders enforce progressive modes by resetting interlace_allowed. Hence we always want crtc vertical timings in frames. Enforce this in our crtc mode_fixup function and rip out any redudant timing computations from the encoders' mode_fixup function. v2-4: Adjust the vertical timings a bit. v5: Split out the 'subtract-one for interlaced' fixes. v6: Clarify issues around tv-out and gen2. Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Christopher Egert <cme3000@gmail.com> Tested-by: Alfonso Fiore <alfonso.fiore@gmail.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3437,10 +3437,7 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
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return false;
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}
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/* XXX some encoders set the crtcinfo, others don't.
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* Obviously we need some form of conflict resolution here...
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*/
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if (adjusted_mode->crtc_htotal == 0)
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/* All interlaced capable intel hw wants timings in frames. */
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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return true;
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@ -157,7 +157,6 @@ static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
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C(vsync_end);
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C(vtotal);
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C(clock);
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drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
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#undef C
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}
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@ -264,7 +264,7 @@ i830_activate_pipe_a(struct drm_device *dev)
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DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
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mode = drm_mode_duplicate(dev, &vesa_640x480);
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drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
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drm_mode_set_crtcinfo(mode, 0);
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if (!drm_crtc_helper_set_mode(&crtc->base, mode,
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crtc->base.x, crtc->base.y,
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crtc->base.fb))
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@ -48,7 +48,7 @@ intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
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adjusted_mode->clock = fixed_mode->clock;
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drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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}
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/* adjusted_mode has been preset to be the panel's fixed mode */
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@ -944,7 +944,6 @@ intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
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intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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return true;
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}
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@ -1240,7 +1240,7 @@ intel_tv_detect(struct drm_connector *connector, bool force)
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int type;
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mode = reported_modes[0];
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drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V);
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drm_mode_set_crtcinfo(&mode, 0);
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if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) {
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type = intel_tv_detect_type(intel_tv, connector);
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