Merge tag 'drm-intel-next-fixes-2017-07-11' of git://anongit.freedesktop.org/git/drm-intel into drm-next
drm/i915 fixes for v4.13-rc1 * tag 'drm-intel-next-fixes-2017-07-11' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Make DP-MST connector info work drm/i915/gvt: Use fence error from GVT request for workload status drm/i915/gvt: remove scheduler_mutex in per-engine workload_thread drm/i915/gvt: Revert "drm/i915/gvt: Fix possible recursive locking issue" drm/i915/gvt: Audit the command buffer address drm/i915/gvt: Fix a memory leak in intel_gvt_init_gtt() drm/i915/fbdev: Check for existence of ifbdev->vma before operations drm/i915: Hold RPM wakelock while initializing OA buffer drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing Programming drm/i915/cfl: Fix Workarounds. drm/i915: Avoid undefined behaviour of "u32 >> 32" drm/i915: reintroduce VLV/CHV PFI programming power domain workaround drm/i915: Fix an error checking test drm/i915: Disable MSI for all pre-gen5 drm/i915/gvt: Make function dpy_reg_mmio_readx safe drm/i915/gvt: Don't read ADPA_CRT_HOTPLUG_MONITOR from host drm/i915/gvt: Set initial PORT_CLK_SEL vreg for BDW drm/i915/gvt: Fix inconsistent locks holding sequence drm/i915/gvt: Fix possible recursive locking issue
This commit is contained in:
Dave Airlie
Коммит
caa164e373
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@ -2536,6 +2536,11 @@ static int scan_workload(struct intel_vgpu_workload *workload)
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gma_head == gma_tail)
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return 0;
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if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
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ret = -EINVAL;
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goto out;
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}
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ret = ip_gma_set(&s, gma_head);
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if (ret)
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goto out;
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@ -2579,6 +2584,11 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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s.rb_va = wa_ctx->indirect_ctx.shadow_va;
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s.workload = workload;
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if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
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ret = -EINVAL;
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goto out;
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}
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ret = ip_gma_set(&s, gma_head);
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if (ret)
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goto out;
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@ -197,6 +197,12 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
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(PORT_B << TRANS_DDI_PORT_SHIFT) |
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TRANS_DDI_FUNC_ENABLE);
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if (IS_BROADWELL(dev_priv)) {
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vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) &=
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~PORT_CLK_SEL_MASK;
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vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) |=
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PORT_CLK_SEL_LCPLL_810;
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}
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
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@ -211,6 +217,12 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
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(PORT_C << TRANS_DDI_PORT_SHIFT) |
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TRANS_DDI_FUNC_ENABLE);
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if (IS_BROADWELL(dev_priv)) {
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vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) &=
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~PORT_CLK_SEL_MASK;
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vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) |=
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PORT_CLK_SEL_LCPLL_810;
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}
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
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vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
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@ -225,6 +237,12 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
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(PORT_D << TRANS_DDI_PORT_SHIFT) |
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TRANS_DDI_FUNC_ENABLE);
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if (IS_BROADWELL(dev_priv)) {
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vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) &=
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~PORT_CLK_SEL_MASK;
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vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) |=
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PORT_CLK_SEL_LCPLL_810;
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}
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
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vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
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@ -244,6 +262,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
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}
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/* Clear host CRT status, so guest couldn't detect this host CRT. */
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if (IS_BROADWELL(dev_priv))
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vgpu_vreg(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
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}
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static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
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@ -2259,6 +2259,8 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
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ret = setup_spt_oos(gvt);
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if (ret) {
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gvt_err("fail to initialize SPT oos\n");
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dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
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__free_page(gvt->gtt.scratch_ggtt_page);
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return ret;
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}
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}
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@ -367,21 +367,24 @@ static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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*(u32 *)p_data = (1 << 17);
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return 0;
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}
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switch (offset) {
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case 0xe651c:
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case 0xe661c:
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case 0xe671c:
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case 0xe681c:
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vgpu_vreg(vgpu, offset) = 1 << 17;
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break;
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case 0xe6c04:
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vgpu_vreg(vgpu, offset) = 0x3;
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break;
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case 0xe6e1c:
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vgpu_vreg(vgpu, offset) = 0x2f << 16;
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break;
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default:
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return -EINVAL;
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}
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static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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*(u32 *)p_data = 3;
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return 0;
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}
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static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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*(u32 *)p_data = (0x2f << 16);
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read_vreg(vgpu, offset, p_data, bytes);
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return 0;
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}
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@ -1925,7 +1928,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
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dp_aux_ch_ctl_mmio_write);
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MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write);
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MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
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MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
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MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
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@ -2011,8 +2014,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL);
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MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL);
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MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL);
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MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
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PORTA_HOTPLUG_STATUS_MASK
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@ -232,16 +232,20 @@ static void gvt_cache_destroy(struct intel_vgpu *vgpu)
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struct device *dev = mdev_dev(vgpu->vdev.mdev);
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unsigned long gfn;
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mutex_lock(&vgpu->vdev.cache_lock);
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while ((node = rb_first(&vgpu->vdev.cache))) {
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for (;;) {
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mutex_lock(&vgpu->vdev.cache_lock);
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node = rb_first(&vgpu->vdev.cache);
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if (!node) {
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mutex_unlock(&vgpu->vdev.cache_lock);
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break;
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}
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dma = rb_entry(node, struct gvt_dma, node);
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gvt_dma_unmap_iova(vgpu, dma->iova);
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gfn = dma->gfn;
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vfio_unpin_pages(dev, &gfn, 1);
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__gvt_cache_remove_entry(vgpu, dma);
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mutex_unlock(&vgpu->vdev.cache_lock);
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vfio_unpin_pages(dev, &gfn, 1);
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}
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mutex_unlock(&vgpu->vdev.cache_lock);
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}
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static struct intel_vgpu_type *intel_gvt_find_vgpu_type(struct intel_gvt *gvt,
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@ -174,15 +174,6 @@ static int shadow_context_status_change(struct notifier_block *nb,
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atomic_set(&workload->shadow_ctx_active, 1);
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break;
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case INTEL_CONTEXT_SCHEDULE_OUT:
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/* If the status is -EINPROGRESS means this workload
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* doesn't meet any issue during dispatching so when
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* get the SCHEDULE_OUT set the status to be zero for
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* good. If the status is NOT -EINPROGRESS means there
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* is something wrong happened during dispatching and
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* the status should not be set to zero
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*/
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if (workload->status == -EINPROGRESS)
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workload->status = 0;
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atomic_set(&workload->shadow_ctx_active, 0);
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break;
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default:
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@ -427,6 +418,18 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
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wait_event(workload->shadow_ctx_status_wq,
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!atomic_read(&workload->shadow_ctx_active));
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/* If this request caused GPU hang, req->fence.error will
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* be set to -EIO. Use -EIO to set workload status so
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* that when this request caused GPU hang, didn't trigger
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* context switch interrupt to guest.
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*/
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if (likely(workload->status == -EINPROGRESS)) {
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if (workload->req->fence.error == -EIO)
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workload->status = -EIO;
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else
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workload->status = 0;
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}
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i915_gem_request_put(fetch_and_zero(&workload->req));
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if (!workload->status && !vgpu->resetting) {
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@ -464,8 +467,6 @@ struct workload_thread_param {
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int ring_id;
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};
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static DEFINE_MUTEX(scheduler_mutex);
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static int workload_thread(void *priv)
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{
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struct workload_thread_param *p = (struct workload_thread_param *)priv;
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@ -497,8 +498,6 @@ static int workload_thread(void *priv)
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if (!workload)
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break;
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mutex_lock(&scheduler_mutex);
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gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
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workload->ring_id, workload,
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workload->vgpu->id);
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@ -537,9 +536,6 @@ complete:
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FORCEWAKE_ALL);
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intel_runtime_pm_put(gvt->dev_priv);
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mutex_unlock(&scheduler_mutex);
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}
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return 0;
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}
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|
|
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|||
|
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@ -3083,7 +3083,7 @@ static void intel_connector_info(struct seq_file *m,
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connector->display_info.cea_rev);
|
||||
}
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||||
|
||||
if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
|
||||
if (!intel_encoder)
|
||||
return;
|
||||
|
||||
switch (connector->connector_type) {
|
||||
|
|
|
|||
|
|
@ -1132,10 +1132,12 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
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|||
* and the registers being closely associated.
|
||||
*
|
||||
* According to chipset errata, on the 965GM, MSI interrupts may
|
||||
* be lost or delayed, but we use them anyways to avoid
|
||||
* stuck interrupts on some machines.
|
||||
* be lost or delayed, and was defeatured. MSI interrupts seem to
|
||||
* get lost on g4x as well, and interrupt delivery seems to stay
|
||||
* properly dead afterwards. So we'll just disable them for all
|
||||
* pre-gen5 chipsets.
|
||||
*/
|
||||
if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
|
||||
if (INTEL_GEN(dev_priv) >= 5) {
|
||||
if (pci_enable_msi(pdev) < 0)
|
||||
DRM_DEBUG_DRIVER("can't enable MSI");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -288,20 +288,26 @@ static int eb_create(struct i915_execbuffer *eb)
|
|||
* direct lookup.
|
||||
*/
|
||||
do {
|
||||
unsigned int flags;
|
||||
|
||||
/* While we can still reduce the allocation size, don't
|
||||
* raise a warning and allow the allocation to fail.
|
||||
* On the last pass though, we want to try as hard
|
||||
* as possible to perform the allocation and warn
|
||||
* if it fails.
|
||||
*/
|
||||
flags = GFP_TEMPORARY;
|
||||
if (size > 1)
|
||||
flags |= __GFP_NORETRY | __GFP_NOWARN;
|
||||
|
||||
eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
|
||||
GFP_TEMPORARY |
|
||||
__GFP_NORETRY |
|
||||
__GFP_NOWARN);
|
||||
flags);
|
||||
if (eb->buckets)
|
||||
break;
|
||||
} while (--size);
|
||||
|
||||
if (unlikely(!eb->buckets)) {
|
||||
eb->buckets = kzalloc(sizeof(struct hlist_head),
|
||||
GFP_TEMPORARY);
|
||||
if (unlikely(!eb->buckets))
|
||||
return -ENOMEM;
|
||||
}
|
||||
if (unlikely(!size))
|
||||
return -ENOMEM;
|
||||
|
||||
eb->lut_size = size;
|
||||
} else {
|
||||
|
|
@ -452,7 +458,7 @@ eb_add_vma(struct i915_execbuffer *eb,
|
|||
return err;
|
||||
}
|
||||
|
||||
if (eb->lut_size >= 0) {
|
||||
if (eb->lut_size > 0) {
|
||||
vma->exec_handle = entry->handle;
|
||||
hlist_add_head(&vma->exec_node,
|
||||
&eb->buckets[hash_32(entry->handle,
|
||||
|
|
@ -894,7 +900,7 @@ static void eb_release_vmas(const struct i915_execbuffer *eb)
|
|||
static void eb_reset_vmas(const struct i915_execbuffer *eb)
|
||||
{
|
||||
eb_release_vmas(eb);
|
||||
if (eb->lut_size >= 0)
|
||||
if (eb->lut_size > 0)
|
||||
memset(eb->buckets, 0,
|
||||
sizeof(struct hlist_head) << eb->lut_size);
|
||||
}
|
||||
|
|
@ -903,7 +909,7 @@ static void eb_destroy(const struct i915_execbuffer *eb)
|
|||
{
|
||||
GEM_BUG_ON(eb->reloc_cache.rq);
|
||||
|
||||
if (eb->lut_size >= 0)
|
||||
if (eb->lut_size > 0)
|
||||
kfree(eb->buckets);
|
||||
}
|
||||
|
||||
|
|
@ -2180,8 +2186,11 @@ i915_gem_do_execbuffer(struct drm_device *dev,
|
|||
}
|
||||
}
|
||||
|
||||
if (eb_create(&eb))
|
||||
return -ENOMEM;
|
||||
err = eb_create(&eb);
|
||||
if (err)
|
||||
goto err_out_fence;
|
||||
|
||||
GEM_BUG_ON(!eb.lut_size);
|
||||
|
||||
/*
|
||||
* Take a local wakeref for preparing to dispatch the execbuf as
|
||||
|
|
@ -2340,6 +2349,7 @@ err_unlock:
|
|||
err_rpm:
|
||||
intel_runtime_pm_put(eb.i915);
|
||||
eb_destroy(&eb);
|
||||
err_out_fence:
|
||||
if (out_fence_fd != -1)
|
||||
put_unused_fd(out_fence_fd);
|
||||
err_in_fence:
|
||||
|
|
|
|||
|
|
@ -2067,10 +2067,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = alloc_oa_buffer(dev_priv);
|
||||
if (ret)
|
||||
goto err_oa_buf_alloc;
|
||||
|
||||
/* PRM - observability performance counters:
|
||||
*
|
||||
* OACONTROL, performance counter enable, note:
|
||||
|
|
@ -2086,6 +2082,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
|
|||
intel_runtime_pm_get(dev_priv);
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
|
||||
ret = alloc_oa_buffer(dev_priv);
|
||||
if (ret)
|
||||
goto err_oa_buf_alloc;
|
||||
|
||||
ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv);
|
||||
if (ret)
|
||||
goto err_enable;
|
||||
|
|
@ -2097,11 +2097,11 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
|
|||
return 0;
|
||||
|
||||
err_enable:
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
free_oa_buffer(dev_priv);
|
||||
|
||||
err_oa_buf_alloc:
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
if (stream->ctx)
|
||||
oa_put_render_ctx_id(stream);
|
||||
|
||||
|
|
|
|||
|
|
@ -1802,7 +1802,7 @@ enum skl_disp_power_wells {
|
|||
#define POST_CURSOR_2(x) ((x) << 6)
|
||||
#define POST_CURSOR_2_MASK (0x3F << 6)
|
||||
#define CURSOR_COEFF(x) ((x) << 0)
|
||||
#define CURSOR_COEFF_MASK (0x3F << 6)
|
||||
#define CURSOR_COEFF_MASK (0x3F << 0)
|
||||
|
||||
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
|
||||
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
|
||||
|
|
|
|||
|
|
@ -491,6 +491,14 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
int cdclk = cdclk_state->cdclk;
|
||||
u32 val, cmd;
|
||||
|
||||
/* There are cases where we can end up here with power domains
|
||||
* off and a CDCLK frequency other than the minimum, like when
|
||||
* issuing a modeset without actually changing any display after
|
||||
* a system suspend. So grab the PIPE-A domain, which covers
|
||||
* the HW blocks needed for the following programming.
|
||||
*/
|
||||
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
|
||||
|
||||
if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
|
||||
cmd = 2;
|
||||
else if (cdclk == 266667)
|
||||
|
|
@ -549,6 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
intel_update_cdclk(dev_priv);
|
||||
|
||||
vlv_program_pfi_credits(dev_priv);
|
||||
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
|
||||
}
|
||||
|
||||
static void chv_set_cdclk(struct drm_i915_private *dev_priv,
|
||||
|
|
@ -568,6 +578,14 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
return;
|
||||
}
|
||||
|
||||
/* There are cases where we can end up here with power domains
|
||||
* off and a CDCLK frequency other than the minimum, like when
|
||||
* issuing a modeset without actually changing any display after
|
||||
* a system suspend. So grab the PIPE-A domain, which covers
|
||||
* the HW blocks needed for the following programming.
|
||||
*/
|
||||
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
|
||||
|
||||
/*
|
||||
* Specs are full of misinformation, but testing on actual
|
||||
* hardware has shown that we just need to write the desired
|
||||
|
|
@ -590,6 +608,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
intel_update_cdclk(dev_priv);
|
||||
|
||||
vlv_program_pfi_credits(dev_priv);
|
||||
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
|
||||
}
|
||||
|
||||
static int bdw_calc_cdclk(int max_pixclk)
|
||||
|
|
|
|||
|
|
@ -821,9 +821,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
|
|||
I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
|
||||
GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
|
||||
|
||||
/* WaDisableKillLogic:bxt,skl,kbl,cfl */
|
||||
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
||||
ECOCHK_DIS_TLB);
|
||||
/* WaDisableKillLogic:bxt,skl,kbl */
|
||||
if (!IS_COFFEELAKE(dev_priv))
|
||||
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
||||
ECOCHK_DIS_TLB);
|
||||
|
||||
/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
|
||||
/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
|
||||
|
|
@ -894,10 +895,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
|
|||
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
||||
HDC_FORCE_NON_COHERENT);
|
||||
|
||||
/* WaDisableHDCInvalidation:skl,bxt,kbl */
|
||||
if (!IS_COFFEELAKE(dev_priv))
|
||||
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
||||
BDW_DISABLE_HDC_INVALIDATION);
|
||||
/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
|
||||
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
||||
BDW_DISABLE_HDC_INVALIDATION);
|
||||
|
||||
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
|
||||
if (IS_SKYLAKE(dev_priv) ||
|
||||
|
|
|
|||
|
|
@ -535,14 +535,15 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev)
|
|||
|
||||
drm_fb_helper_fini(&ifbdev->helper);
|
||||
|
||||
if (ifbdev->fb) {
|
||||
if (ifbdev->vma) {
|
||||
mutex_lock(&ifbdev->helper.dev->struct_mutex);
|
||||
intel_unpin_fb_vma(ifbdev->vma);
|
||||
mutex_unlock(&ifbdev->helper.dev->struct_mutex);
|
||||
|
||||
drm_framebuffer_remove(&ifbdev->fb->base);
|
||||
}
|
||||
|
||||
if (ifbdev->fb)
|
||||
drm_framebuffer_remove(&ifbdev->fb->base);
|
||||
|
||||
kfree(ifbdev);
|
||||
}
|
||||
|
||||
|
|
@ -765,7 +766,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
|
|||
struct intel_fbdev *ifbdev = dev_priv->fbdev;
|
||||
struct fb_info *info;
|
||||
|
||||
if (!ifbdev || !ifbdev->fb)
|
||||
if (!ifbdev || !ifbdev->vma)
|
||||
return;
|
||||
|
||||
info = ifbdev->helper.fbdev;
|
||||
|
|
@ -812,7 +813,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
|
|||
{
|
||||
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
|
||||
|
||||
if (ifbdev && ifbdev->fb)
|
||||
if (ifbdev && ifbdev->vma)
|
||||
drm_fb_helper_hotplug_event(&ifbdev->helper);
|
||||
}
|
||||
|
||||
|
|
@ -824,7 +825,7 @@ void intel_fbdev_restore_mode(struct drm_device *dev)
|
|||
return;
|
||||
|
||||
intel_fbdev_sync(ifbdev);
|
||||
if (!ifbdev->fb)
|
||||
if (!ifbdev->vma)
|
||||
return;
|
||||
|
||||
if (drm_fb_helper_restore_fbdev_mode_unlocked(&ifbdev->helper) == 0)
|
||||
|
|
|
|||
|
|
@ -246,9 +246,9 @@ static int igt_dmabuf_export_vmap(void *arg)
|
|||
i915_gem_object_put(obj);
|
||||
|
||||
ptr = dma_buf_vmap(dmabuf);
|
||||
if (IS_ERR(ptr)) {
|
||||
err = PTR_ERR(ptr);
|
||||
pr_err("dma_buf_vmap failed with err=%d\n", err);
|
||||
if (!ptr) {
|
||||
pr_err("dma_buf_vmap failed\n");
|
||||
err = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
|
|||
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