Merge branch 'fixes-for-3.9' into next/fixes-non-critical
This is a branch of fixes that originally were scheduled for 3.8 but due to the request from Linus to hold back on all but the most critical of fixes, we're re-queueing them for 3.9 here. * fixes-for-3.9: ARM: dts: imx6: fix fec ptp clock slow 10 time ARM: highbank: mask cluster id from cpu_logical_map ARM: scu: mask cluster id from cpu_logical_map ARM: scu: add empty scu_enable for !CONFIG_SMP ARM: at91/at91sam9x5.dtsi: fix usart3 TXD ARM: at91: at91sam9x5: fix usart3 pinctrl name ARM: EXYNOS: Fix crash on soft reset on EXYNOS5440 ARM: dts: fix tick and alarm irq numbers for exynos5440 ARM: dts: fix compatible value for exynos pinctrl ARM: dts: Fix compatible value of pinctrl module on EXYNOS5440 ARM: S3C24XX: fix uninitialized variable warning mfd/vexpress: vexpress_sysreg_setup must not be __init ARM: ux500: Fix u9540 booting issues arm: mvebu: i2c come back in defconfig arm: plat-orion: fix printing of "MPP config unavailable on this hardware" Dove: activate GPIO interrupts in DT ARM: ux500: add spin_unlock(&master_lock). ARM: ux500: Disable Power Supply and Battery Management by default Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
cae617b64c
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@ -7,9 +7,9 @@ on-chip controllers onto these pads.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
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- "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
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- "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
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- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
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- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
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- reg: Base address of the pin controller hardware module and length of
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the address space it occupies.
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@ -142,7 +142,7 @@ the following format 'pinctrl{n}' where n is a unique number for the alias.
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Example: A pin-controller node with pin banks:
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,pinctrl-exynos4210";
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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@ -185,7 +185,7 @@ Example: A pin-controller node with pin banks:
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Example 1: A pin-controller node with pin groups.
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,pinctrl-exynos4210";
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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@ -230,7 +230,7 @@ Example 1: A pin-controller node with pin groups.
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Example 2: A pin-controller node with external wakeup interrupt controller node.
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,pinctrl-exynos4210";
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>
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@ -197,9 +197,9 @@
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};
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usart3 {
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pinctrl_uart3: usart3-0 {
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pinctrl_usart3: usart3-0 {
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atmel,pins =
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<2 23 0x2 0x1 /* PC22 periph B with pullup */
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<2 22 0x2 0x1 /* PC22 periph B with pullup */
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2 23 0x2 0x0>; /* PC23 periph B */
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};
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@ -93,6 +93,7 @@
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reg = <0xd0400 0x20>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <12>, <13>, <14>, <60>;
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};
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@ -103,6 +104,7 @@
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reg = <0xd0420 0x20>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <61>;
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};
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@ -48,13 +48,13 @@
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,pinctrl-exynos4210";
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,pinctrl-exynos4210";
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>;
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@ -66,7 +66,7 @@
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};
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pinctrl_2: pinctrl@03860000 {
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compatible = "samsung,pinctrl-exynos4210";
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x03860000 0x1000>;
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};
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@ -37,13 +37,13 @@
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,pinctrl-exynos4x12";
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,pinctrl-exynos4x12";
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>;
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@ -55,14 +55,14 @@
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};
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pinctrl_2: pinctrl@03860000 {
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compatible = "samsung,pinctrl-exynos4x12";
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <10 0>;
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};
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pinctrl_3: pinctrl@106E0000 {
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compatible = "samsung,pinctrl-exynos4x12";
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x106E0000 0x1000>;
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interrupts = <0 72 0>;
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};
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@ -86,7 +86,7 @@
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};
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pinctrl {
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compatible = "samsung,pinctrl-exynos5440";
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compatible = "samsung,exynos5440-pinctrl";
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reg = <0xE0000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -154,6 +154,6 @@
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rtc {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <0 16 0>, <0 17 0>;
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interrupts = <0 17 0>, <0 16 0>;
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};
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};
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@ -866,7 +866,7 @@
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compatible = "fsl,imx6q-fec";
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reg = <0x02188000 0x4000>;
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interrupts = <0 118 0x04 0 119 0x04>;
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clocks = <&clks 117>, <&clks 117>, <&clks 177>;
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clocks = <&clks 117>, <&clks 117>, <&clks 190>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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@ -33,6 +33,8 @@ CONFIG_MVNETA=y
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CONFIG_MARVELL_PHY=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_I2C=y
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CONFIG_I2C_MV64XXX=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_SYSFS=y
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@ -66,9 +66,9 @@ CONFIG_SPI=y
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CONFIG_SPI_PL022=y
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CONFIG_GPIO_STMPE=y
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CONFIG_GPIO_TC3589X=y
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CONFIG_POWER_SUPPLY=y
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CONFIG_AB8500_BM=y
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CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
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# CONFIG_POWER_SUPPLY is not set
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# CONFIG_AB8500_BM is not set
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# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set
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CONFIG_THERMAL=y
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CONFIG_CPU_THERMAL=y
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CONFIG_MFD_STMPE=y
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@ -7,8 +7,14 @@
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#ifndef __ASSEMBLER__
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unsigned int scu_get_core_count(void __iomem *);
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void scu_enable(void __iomem *);
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int scu_power_mode(void __iomem *, unsigned int);
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#ifdef CONFIG_SMP
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void scu_enable(void __iomem *scu_base);
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#else
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static inline void scu_enable(void __iomem *scu_base) {}
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#endif
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#endif
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#endif
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@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
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int scu_power_mode(void __iomem *scu_base, unsigned int mode)
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{
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unsigned int val;
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int cpu = cpu_logical_map(smp_processor_id());
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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if (mode > 3 || mode == 1 || cpu > 3)
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return -EINVAL;
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@ -299,6 +299,7 @@ void exynos4_restart(char mode, const char *cmd)
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void exynos5_restart(char mode, const char *cmd)
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{
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struct device_node *np;
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u32 val;
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void __iomem *addr;
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@ -306,8 +307,9 @@ void exynos5_restart(char mode, const char *cmd)
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val = 0x1;
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addr = EXYNOS_SWRESET;
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} else if (of_machine_is_compatible("samsung,exynos5440")) {
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val = (0x10 << 20) | (0x1 << 16);
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addr = EXYNOS5440_SWRESET;
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
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addr = of_iomap(np, 0) + 0xcc;
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val = (0xfff << 20) | (0x1 << 16);
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} else {
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pr_err("%s: cannot support non-DT\n", __func__);
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return;
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@ -1031,8 +1033,8 @@ static int __init exynos_init_irq_eint(void)
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* interrupt support code here can be completely removed.
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*/
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static const struct of_device_id exynos_pinctrl_ids[] = {
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{ .compatible = "samsung,pinctrl-exynos4210", },
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{ .compatible = "samsung,pinctrl-exynos4x12", },
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{ .compatible = "samsung,exynos4210-pinctrl", },
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{ .compatible = "samsung,exynos4x12-pinctrl", },
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};
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struct device_node *pctrl_np, *wkup_np;
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const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
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@ -28,6 +28,7 @@
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#include <asm/arch_timer.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/arm_timer.h>
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@ -59,7 +60,7 @@ static void __init highbank_scu_map_io(void)
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void highbank_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
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writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
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__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
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outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
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@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
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static inline void highbank_set_core_pwr(void)
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{
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int cpu = cpu_logical_map(smp_processor_id());
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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if (scu_base_addr)
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scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
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else
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@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
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static inline void highbank_clear_core_pwr(void)
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{
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int cpu = cpu_logical_map(smp_processor_id());
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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if (scu_base_addr)
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scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
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else
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@ -197,7 +197,7 @@ static unsigned long s3c24xx_read_idcode_v4(void)
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static void s3c24xx_default_idle(void)
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{
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unsigned long tmp;
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unsigned long tmp = 0;
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int i;
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/* idle the system by using the idle mode which will wait for an
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|
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@ -71,13 +71,11 @@ void __init ux500_init_irq(void)
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* Init clocks here so that they are available for system timer
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* initialization.
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*/
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if (cpu_is_u8500_family())
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if (cpu_is_u8500_family() || cpu_is_u9540())
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db8500_prcmu_early_init();
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|
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if (cpu_is_u8500_family())
|
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if (cpu_is_u8500_family() || cpu_is_u9540())
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u8500_clk_init();
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else if (cpu_is_u9540())
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u9540_clk_init();
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else if (cpu_is_u8540())
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u8540_clk_init();
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}
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|
|
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@ -40,8 +40,10 @@ static inline int ux500_enter_idle(struct cpuidle_device *dev,
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goto wfi;
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/* decouple the gic from the A9 cores */
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if (prcmu_gic_decouple())
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if (prcmu_gic_decouple()) {
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spin_unlock(&master_lock);
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goto out;
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}
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/* If an error occur, we will have to recouple the gic
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* manually */
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|
|
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@ -49,7 +49,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
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"number (%u)\n", num);
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continue;
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}
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if (variant_mask & !(*mpp_list & variant_mask)) {
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if (variant_mask && !(*mpp_list & variant_mask)) {
|
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printk(KERN_WARNING
|
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"orion_mpp_conf: requested MPP%u config "
|
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"unavailable on this hardware\n", num);
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|
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@ -3023,9 +3023,9 @@ static __init int samsung_gpiolib_init(void)
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*/
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struct device_node *pctrl_np;
|
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static const struct of_device_id exynos_pinctrl_ids[] = {
|
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{ .compatible = "samsung,pinctrl-exynos4210", },
|
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{ .compatible = "samsung,pinctrl-exynos4x12", },
|
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{ .compatible = "samsung,pinctrl-exynos5440", },
|
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{ .compatible = "samsung,exynos4210-pinctrl", },
|
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{ .compatible = "samsung,exynos4x12-pinctrl", },
|
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{ .compatible = "samsung,exynos5440-pinctrl", },
|
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};
|
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for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
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if (pctrl_np && of_device_is_available(pctrl_np))
|
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|
|
|
|||
|
|
@ -313,7 +313,7 @@ static void vexpress_sysreg_config_complete(unsigned long data)
|
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}
|
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|
||||
|
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void __init vexpress_sysreg_setup(struct device_node *node)
|
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void vexpress_sysreg_setup(struct device_node *node)
|
||||
{
|
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if (WARN_ON(!vexpress_sysreg_base))
|
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return;
|
||||
|
|
|
|||
|
|
@ -947,9 +947,9 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id samsung_pinctrl_dt_match[] = {
|
||||
{ .compatible = "samsung,pinctrl-exynos4210",
|
||||
{ .compatible = "samsung,exynos4210-pinctrl",
|
||||
.data = (void *)exynos4210_pin_ctrl },
|
||||
{ .compatible = "samsung,pinctrl-exynos4x12",
|
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{ .compatible = "samsung,exynos4x12-pinctrl",
|
||||
.data = (void *)exynos4x12_pin_ctrl },
|
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{},
|
||||
};
|
||||
|
|
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