ASoC: cs35l41: Move cs35l41_set_cspl_mbox_cmd to shared code
This function is used to control the DSP Firmware for cs35l41, and will be needed by the cs35l41 hda driver, when firmware support is added. Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220509214703.4482-7-vitalyr@opensource.cirrus.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Stefan Binding
Takashi Iwai
Родитель
de8cab7b38
Коммит
caf7c1f1de
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@ -801,6 +801,24 @@ struct cs35l41_otp_map_element_t {
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u32 word_offset;
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};
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enum cs35l41_cspl_mbox_status {
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CSPL_MBOX_STS_RUNNING = 0,
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CSPL_MBOX_STS_PAUSED = 1,
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CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
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};
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enum cs35l41_cspl_mbox_cmd {
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CSPL_MBOX_CMD_NONE = 0,
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CSPL_MBOX_CMD_PAUSE = 1,
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CSPL_MBOX_CMD_RESUME = 2,
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CSPL_MBOX_CMD_REINIT = 3,
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CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
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CSPL_MBOX_CMD_HIBERNATE = 5,
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CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
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CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
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CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
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};
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/*
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* IRQs
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*/
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@ -859,6 +877,8 @@ int cs35l41_set_channels(struct device *dev, struct regmap *reg,
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unsigned int tx_num, unsigned int *tx_slot,
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unsigned int rx_num, unsigned int *rx_slot);
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int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg);
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int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
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enum cs35l41_cspl_mbox_cmd cmd);
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int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
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struct cs35l41_hw_cfg *hw_cfg);
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bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type);
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@ -1206,6 +1206,63 @@ int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg)
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}
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EXPORT_SYMBOL_GPL(cs35l41_gpio_config);
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static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd,
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enum cs35l41_cspl_mbox_status sts)
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{
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switch (cmd) {
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case CSPL_MBOX_CMD_NONE:
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case CSPL_MBOX_CMD_UNKNOWN_CMD:
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return true;
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case CSPL_MBOX_CMD_PAUSE:
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case CSPL_MBOX_CMD_OUT_OF_HIBERNATE:
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return (sts == CSPL_MBOX_STS_PAUSED);
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case CSPL_MBOX_CMD_RESUME:
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return (sts == CSPL_MBOX_STS_RUNNING);
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case CSPL_MBOX_CMD_REINIT:
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return (sts == CSPL_MBOX_STS_RUNNING);
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case CSPL_MBOX_CMD_STOP_PRE_REINIT:
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return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT);
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default:
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return false;
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}
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}
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int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
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enum cs35l41_cspl_mbox_cmd cmd)
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{
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unsigned int sts = 0, i;
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int ret;
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// Set mailbox cmd
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ret = regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd);
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if (ret < 0) {
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if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
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dev_err(dev, "Failed to write MBOX: %d\n", ret);
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return ret;
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}
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// Read mailbox status and verify it is appropriate for the given cmd
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for (i = 0; i < 5; i++) {
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usleep_range(1000, 1100);
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ret = regmap_read(regmap, CS35L41_DSP_MBOX_2, &sts);
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if (ret < 0) {
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dev_err(dev, "Failed to read MBOX STS: %d\n", ret);
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continue;
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}
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if (!cs35l41_check_cspl_mbox_sts(cmd, sts))
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dev_dbg(dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts);
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else
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return 0;
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}
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dev_err(dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts);
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return -ENOMSG;
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}
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EXPORT_SYMBOL_GPL(cs35l41_set_cspl_mbox_cmd);
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MODULE_DESCRIPTION("CS35L41 library");
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MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
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MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>");
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@ -208,67 +208,6 @@ static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
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}
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}
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static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd,
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enum cs35l41_cspl_mbox_status sts)
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{
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switch (cmd) {
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case CSPL_MBOX_CMD_NONE:
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case CSPL_MBOX_CMD_UNKNOWN_CMD:
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return true;
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case CSPL_MBOX_CMD_PAUSE:
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case CSPL_MBOX_CMD_OUT_OF_HIBERNATE:
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return (sts == CSPL_MBOX_STS_PAUSED);
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case CSPL_MBOX_CMD_RESUME:
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return (sts == CSPL_MBOX_STS_RUNNING);
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case CSPL_MBOX_CMD_REINIT:
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return (sts == CSPL_MBOX_STS_RUNNING);
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case CSPL_MBOX_CMD_STOP_PRE_REINIT:
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return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT);
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default:
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return false;
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}
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}
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static int cs35l41_set_cspl_mbox_cmd(struct cs35l41_private *cs35l41,
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enum cs35l41_cspl_mbox_cmd cmd)
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{
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unsigned int sts = 0, i;
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int ret;
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// Set mailbox cmd
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ret = regmap_write(cs35l41->regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd);
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if (ret < 0) {
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if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
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dev_err(cs35l41->dev, "Failed to write MBOX: %d\n", ret);
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return ret;
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}
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// Read mailbox status and verify it is appropriate for the given cmd
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for (i = 0; i < 5; i++) {
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usleep_range(1000, 1100);
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ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &sts);
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if (ret < 0) {
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dev_err(cs35l41->dev, "Failed to read MBOX STS: %d\n", ret);
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continue;
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}
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if (!cs35l41_check_cspl_mbox_sts(cmd, sts)) {
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dev_dbg(cs35l41->dev,
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"[%u] cmd %u returned invalid sts %u",
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i, cmd, sts);
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} else {
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return 0;
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}
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}
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dev_err(cs35l41->dev,
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"Failed to set mailbox cmd %u (status %u)\n",
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cmd, sts);
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return -ENOMSG;
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}
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static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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@ -299,9 +238,11 @@ static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
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return -EINVAL;
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}
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return cs35l41_set_cspl_mbox_cmd(cs35l41, CSPL_MBOX_CMD_RESUME);
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return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
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CSPL_MBOX_CMD_RESUME);
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case SND_SOC_DAPM_PRE_PMD:
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return cs35l41_set_cspl_mbox_cmd(cs35l41, CSPL_MBOX_CMD_PAUSE);
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return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
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CSPL_MBOX_CMD_PAUSE);
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default:
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return 0;
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}
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@ -1475,7 +1416,7 @@ static int cs35l41_exit_hibernate(struct cs35l41_private *cs35l41)
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dev_dbg(cs35l41->dev, "Exit hibernate\n");
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for (j = 0; j < wake_retries; j++) {
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ret = cs35l41_set_cspl_mbox_cmd(cs35l41,
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ret = cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
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CSPL_MBOX_CMD_OUT_OF_HIBERNATE);
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if (!ret)
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break;
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@ -23,24 +23,6 @@
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extern const struct dev_pm_ops cs35l41_pm_ops;
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enum cs35l41_cspl_mbox_status {
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CSPL_MBOX_STS_RUNNING = 0,
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CSPL_MBOX_STS_PAUSED = 1,
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CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
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};
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enum cs35l41_cspl_mbox_cmd {
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CSPL_MBOX_CMD_NONE = 0,
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CSPL_MBOX_CMD_PAUSE = 1,
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CSPL_MBOX_CMD_RESUME = 2,
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CSPL_MBOX_CMD_REINIT = 3,
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CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
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CSPL_MBOX_CMD_HIBERNATE = 5,
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CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
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CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
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CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
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};
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struct cs35l41_private {
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struct wm_adsp dsp; /* needs to be first member */
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struct snd_soc_codec *codec;
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