ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate
DRA7 supports only CSWR for CPU, MPU power domains. Core power domain supports upto INA. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -39,6 +39,7 @@
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#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
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#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
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/*
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@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = DRA7XX_PRM_CORE_INST,
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.prcm_partition = DRA7XX_PRM_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.pwrsts = PWRSTS_INA_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 5,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* core_nret_bank */
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@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = {
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.name = "cpu0_pwrdm",
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.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
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.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
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@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = {
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.name = "cpu1_pwrdm",
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.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
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.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
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@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = {
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.prcm_offs = DRA7XX_PRM_MPU_INST,
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.prcm_partition = DRA7XX_PRM_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* mpu_l2 */
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