serial: imx: implement rts delaying for rs485
This adds support for delays between assertion of RTS (which is supposed to enable the rs485 transmitter) and sending as well as between the last send char and deassertionof RTS. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20200714093012.21621-2-uwe@kleine-koenig.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Uwe Kleine-König
Greg Kroah-Hartman
Родитель
23a98b6eb8
Коммит
cb1a609236
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@ -188,6 +188,13 @@ struct imx_uart_data {
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enum imx_uart_type devtype;
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};
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enum imx_tx_state {
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OFF,
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WAIT_AFTER_RTS,
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SEND,
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WAIT_AFTER_SEND,
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};
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struct imx_port {
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struct uart_port port;
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struct timer_list timer;
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@ -224,6 +231,11 @@ struct imx_port {
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unsigned int dma_tx_nents;
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unsigned int saved_reg[10];
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bool context_saved;
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enum imx_tx_state tx_state;
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unsigned long tx_state_next_change;
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struct timer_list trigger_start_tx;
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struct timer_list trigger_stop_tx;
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};
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struct imx_port_ucrs {
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@ -427,7 +439,10 @@ static void imx_uart_start_rx(struct uart_port *port)
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static void imx_uart_stop_tx(struct uart_port *port)
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{
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struct imx_port *sport = (struct imx_port *)port;
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u32 ucr1;
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u32 ucr1, ucr4, usr2;
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if (sport->tx_state == OFF)
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return;
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/*
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* We are maybe in the SMP context, so if the DMA TX thread is running
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@ -439,21 +454,46 @@ static void imx_uart_stop_tx(struct uart_port *port)
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ucr1 = imx_uart_readl(sport, UCR1);
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imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
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/* in rs485 mode disable transmitter if shifter is empty */
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if (port->rs485.flags & SER_RS485_ENABLED &&
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imx_uart_readl(sport, USR2) & USR2_TXDC) {
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u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
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if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
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imx_uart_rts_active(sport, &ucr2);
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else
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imx_uart_rts_inactive(sport, &ucr2);
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imx_uart_writel(sport, ucr2, UCR2);
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usr2 = imx_uart_readl(sport, USR2);
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if (!(usr2 & USR2_TXDC)) {
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/* The shifter is still busy, so retry once TC triggers */
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return;
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}
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imx_uart_start_rx(port);
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ucr4 = imx_uart_readl(sport, UCR4);
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ucr4 &= ~UCR4_TCEN;
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imx_uart_writel(sport, ucr4, UCR4);
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ucr4 = imx_uart_readl(sport, UCR4);
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ucr4 &= ~UCR4_TCEN;
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imx_uart_writel(sport, ucr4, UCR4);
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/* in rs485 mode disable transmitter */
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if (port->rs485.flags & SER_RS485_ENABLED) {
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if (sport->tx_state == SEND) {
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sport->tx_state = WAIT_AFTER_SEND;
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sport->tx_state_next_change =
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jiffies + DIV_ROUND_UP(port->rs485.delay_rts_after_send * HZ, 1000);
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}
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if (sport->tx_state == WAIT_AFTER_RTS ||
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(sport->tx_state == WAIT_AFTER_SEND &&
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time_after_eq(jiffies, sport->tx_state_next_change))) {
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u32 ucr2;
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del_timer(&sport->trigger_start_tx);
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ucr2 = imx_uart_readl(sport, UCR2);
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if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
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imx_uart_rts_active(sport, &ucr2);
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else
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imx_uart_rts_inactive(sport, &ucr2);
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imx_uart_writel(sport, ucr2, UCR2);
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imx_uart_start_rx(port);
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sport->tx_state = OFF;
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} else if (sport->tx_state == WAIT_AFTER_SEND) {
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mod_timer(&sport->trigger_stop_tx, sport->tx_state_next_change);
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}
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} else {
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sport->tx_state = OFF;
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}
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}
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@ -651,28 +691,53 @@ static void imx_uart_start_tx(struct uart_port *port)
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if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
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return;
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/*
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* We cannot simply do nothing here if sport->tx_state == SEND already
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* because UCR1_TXMPTYEN might already have been cleared in
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* imx_uart_stop_tx(), but tx_state is still SEND.
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*/
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if (port->rs485.flags & SER_RS485_ENABLED) {
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u32 ucr2;
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if (sport->tx_state == OFF) {
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u32 ucr2 = imx_uart_readl(sport, UCR2);
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if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
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imx_uart_rts_active(sport, &ucr2);
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else
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imx_uart_rts_inactive(sport, &ucr2);
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imx_uart_writel(sport, ucr2, UCR2);
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ucr2 = imx_uart_readl(sport, UCR2);
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if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
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imx_uart_rts_active(sport, &ucr2);
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else
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imx_uart_rts_inactive(sport, &ucr2);
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imx_uart_writel(sport, ucr2, UCR2);
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if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
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imx_uart_stop_rx(port);
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if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
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imx_uart_stop_rx(port);
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/*
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* Enable transmitter and shifter empty irq only if DMA is off.
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* In the DMA case this is done in the tx-callback.
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*/
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if (!sport->dma_is_enabled) {
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u32 ucr4 = imx_uart_readl(sport, UCR4);
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ucr4 |= UCR4_TCEN;
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imx_uart_writel(sport, ucr4, UCR4);
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sport->tx_state = WAIT_AFTER_RTS;
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sport->tx_state_next_change =
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jiffies + DIV_ROUND_UP(port->rs485.delay_rts_before_send * HZ, 1000);
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}
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if (sport->tx_state == WAIT_AFTER_SEND ||
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(sport->tx_state == WAIT_AFTER_RTS &&
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time_after_eq(jiffies, sport->tx_state_next_change))) {
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del_timer(&sport->trigger_stop_tx);
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/*
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* Enable transmitter and shifter empty irq only if DMA
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* is off. In the DMA case this is done in the
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* tx-callback.
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*/
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if (!sport->dma_is_enabled) {
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u32 ucr4 = imx_uart_readl(sport, UCR4);
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ucr4 |= UCR4_TCEN;
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imx_uart_writel(sport, ucr4, UCR4);
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}
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sport->tx_state = SEND;
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} else if (sport->tx_state == WAIT_AFTER_RTS) {
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mod_timer(&sport->trigger_start_tx, sport->tx_state_next_change);
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return;
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}
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} else {
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sport->tx_state = SEND;
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}
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if (!sport->dma_is_enabled) {
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@ -1630,7 +1695,6 @@ imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
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if (termios->c_cflag & CRTSCTS)
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ucr2 &= ~UCR2_IRTS;
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if (termios->c_cflag & CSTOPB)
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ucr2 |= UCR2_STPB;
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if (termios->c_cflag & PARENB) {
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@ -1857,10 +1921,6 @@ static int imx_uart_rs485_config(struct uart_port *port,
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struct imx_port *sport = (struct imx_port *)port;
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u32 ucr2;
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/* unimplemented */
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rs485conf->delay_rts_before_send = 0;
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rs485conf->delay_rts_after_send = 0;
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/* RTS is required to control the transmitter */
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if (!sport->have_rtscts && !sport->have_rtsgpio)
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rs485conf->flags &= ~SER_RS485_ENABLED;
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@ -2223,6 +2283,28 @@ static void imx_uart_probe_pdata(struct imx_port *sport,
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sport->have_rtscts = 1;
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}
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static void imx_trigger_start_tx(struct timer_list *t)
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{
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struct imx_port *sport = from_timer(sport, t, trigger_start_tx);
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unsigned long flags;
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spin_lock_irqsave(&sport->port.lock, flags);
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if (sport->tx_state == WAIT_AFTER_RTS)
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imx_uart_start_tx(&sport->port);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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}
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static void imx_trigger_stop_tx(struct timer_list *t)
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{
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struct imx_port *sport = from_timer(sport, t, trigger_stop_tx);
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unsigned long flags;
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spin_lock_irqsave(&sport->port.lock, flags);
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if (sport->tx_state == WAIT_AFTER_SEND)
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imx_uart_stop_tx(&sport->port);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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}
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static int imx_uart_probe(struct platform_device *pdev)
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{
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struct imx_port *sport;
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@ -2369,6 +2451,9 @@ static int imx_uart_probe(struct platform_device *pdev)
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clk_disable_unprepare(sport->clk_ipg);
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timer_setup(&sport->trigger_start_tx, imx_trigger_start_tx, 0);
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timer_setup(&sport->trigger_stop_tx, imx_trigger_stop_tx, 0);
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/*
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* Allocate the IRQ(s) i.MX1 has three interrupts whereas later
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* chips only have one interrupt.
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