perf/x86: Add Intel Westmere-EX uncore support
The Westmere-EX uncore is similar to the Nehalem-EX uncore. The differences are: - Westmere-EX uncore has 10 instances of Cbox. The MSRs for Cbox8 and Cbox9 in the Westmere-EX aren't contiguous with Cbox 0~7. - The fvid field in the ZDP_CTL_FVC register in the Mbox is different. It's 5 bits in the Nehalem-EX, 6 bits in the Westmere-EX. Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1344229882-3907-3-git-send-email-zheng.z.yan@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Yan, Zheng
Thomas Gleixner
Родитель
ebb6cc0359
Коммит
cb37af7712
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@ -901,16 +901,21 @@ static struct attribute_group nhmex_uncore_cbox_format_group = {
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.attrs = nhmex_uncore_cbox_formats_attr,
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};
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/* msr offset for each instance of cbox */
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static unsigned nhmex_cbox_msr_offsets[] = {
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0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
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};
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static struct intel_uncore_type nhmex_uncore_cbox = {
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.name = "cbox",
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.num_counters = 6,
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.num_boxes = 8,
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.num_boxes = 10,
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.perf_ctr_bits = 48,
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.event_ctl = NHMEX_C0_MSR_PMON_EV_SEL0,
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.perf_ctr = NHMEX_C0_MSR_PMON_CTR0,
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.event_mask = NHMEX_PMON_RAW_EVENT_MASK,
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.box_ctl = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
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.msr_offset = NHMEX_C_MSR_OFFSET,
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.msr_offsets = nhmex_cbox_msr_offsets,
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.pair_ctr_ctl = 1,
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.ops = &nhmex_uncore_ops,
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.format_group = &nhmex_uncore_cbox_format_group
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@ -1138,6 +1143,9 @@ static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
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EVENT_EXTRA_END
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};
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/* Nehalem-EX or Westmere-EX ? */
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bool uncore_nhmex;
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static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
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{
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struct intel_uncore_extra_reg *er;
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@ -1167,18 +1175,29 @@ static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64
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return false;
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/* mask of the shared fields */
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mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
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if (uncore_nhmex)
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mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
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else
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mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK;
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er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
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raw_spin_lock_irqsave(&er->lock, flags);
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/* add mask of the non-shared field if it's in use */
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if (__BITS_VALUE(atomic_read(&er->ref), idx, 8))
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mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
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if (uncore_nhmex)
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mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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else
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mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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}
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if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
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atomic_add(1 << (idx * 8), &er->ref);
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mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
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NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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if (uncore_nhmex)
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mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
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NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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else
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mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK |
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WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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er->config &= ~mask;
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er->config |= (config & mask);
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ret = true;
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@ -1212,7 +1231,10 @@ u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
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/* get the non-shared control bits and shift them */
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idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
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config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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if (uncore_nhmex)
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config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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else
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config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
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if (new_idx > orig_idx) {
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idx = new_idx - orig_idx;
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config <<= 3 * idx;
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@ -1222,6 +1244,10 @@ u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
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}
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/* add the shared control bits back */
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if (uncore_nhmex)
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config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
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else
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config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
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config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
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if (modify) {
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/* adjust the main event selector */
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@ -1480,6 +1506,12 @@ static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
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{ /* end: all zeroes */ },
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};
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static struct uncore_event_desc wsmex_uncore_mbox_events[] = {
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INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x5000"),
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INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x5040"),
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{ /* end: all zeroes */ },
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};
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static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
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NHMEX_UNCORE_OPS_COMMON_INIT(),
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.enable_event = nhmex_mbox_msr_enable_event,
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@ -2791,7 +2823,13 @@ static int __init uncore_cpu_init(void)
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snbep_uncore_cbox.num_boxes = max_cores;
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msr_uncores = snbep_msr_uncores;
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break;
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case 46:
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case 46: /* Nehalem-EX */
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uncore_nhmex = true;
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case 47: /* Westmere-EX aka. Xeon E7 */
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if (!uncore_nhmex)
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nhmex_uncore_mbox.event_descs = wsmex_uncore_mbox_events;
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if (nhmex_uncore_cbox.num_boxes > max_cores)
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nhmex_uncore_cbox.num_boxes = max_cores;
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msr_uncores = nhmex_msr_uncores;
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break;
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default:
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@ -276,18 +276,12 @@
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NHMEX_M_PMON_CTL_INC_SEL_MASK | \
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NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK 0x1f
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#define NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK (0x7 << 5)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK (0x7 << 8)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR (1 << 23)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK \
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(NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK | \
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NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK | \
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NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK | \
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NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 11) - 1) | (1 << 23))
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#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n)))
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#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 12) - 1) | (1 << 24))
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#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (12 + 3 * (n)))
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/*
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* use the 9~13 bits to select event If the 7th bit is not set,
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* otherwise use the 19~21 bits to select event.
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@ -369,6 +363,7 @@ struct intel_uncore_type {
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unsigned num_shared_regs:8;
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unsigned single_fixed:1;
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unsigned pair_ctr_ctl:1;
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unsigned *msr_offsets;
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struct event_constraint unconstrainted;
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struct event_constraint *constraints;
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struct intel_uncore_pmu *pmus;
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@ -486,29 +481,31 @@ unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
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return idx * 8 + box->pmu->type->perf_ctr;
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}
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static inline
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unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
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static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
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{
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struct intel_uncore_pmu *pmu = box->pmu;
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return pmu->type->msr_offsets ?
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pmu->type->msr_offsets[pmu->pmu_idx] :
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pmu->type->msr_offset * pmu->pmu_idx;
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}
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static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
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{
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if (!box->pmu->type->box_ctl)
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return 0;
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return box->pmu->type->box_ctl +
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box->pmu->type->msr_offset * box->pmu->pmu_idx;
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return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
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}
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static inline
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unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
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static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
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{
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if (!box->pmu->type->fixed_ctl)
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return 0;
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return box->pmu->type->fixed_ctl +
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box->pmu->type->msr_offset * box->pmu->pmu_idx;
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return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
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}
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static inline
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unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
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static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr +
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box->pmu->type->msr_offset * box->pmu->pmu_idx;
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return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
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}
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static inline
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@ -516,7 +513,7 @@ unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
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{
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return box->pmu->type->event_ctl +
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(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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box->pmu->type->msr_offset * box->pmu->pmu_idx;
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uncore_msr_box_offset(box);
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}
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static inline
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@ -524,7 +521,7 @@ unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
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{
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return box->pmu->type->perf_ctr +
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(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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box->pmu->type->msr_offset * box->pmu->pmu_idx;
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uncore_msr_box_offset(box);
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}
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static inline
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