net: ipa: add IPA v5.0 configuration data
Add the configuration data required for IPA v5.0, which is used in the SDX65 SoC. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder
Jakub Kicinski
Родитель
faf0678ec8
Коммит
cb7550b443
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@ -7,7 +7,7 @@ IPA_REG_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
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# Some IPA versions can reuse another set of GSI register definitions.
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GSI_REG_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11 5.0
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IPA_DATA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11
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IPA_DATA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
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obj-$(CONFIG_QCOM_IPA) += ipa.o
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@ -0,0 +1,481 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2023 Linaro Ltd. */
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#include <linux/log2.h>
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#include "../gsi.h"
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#include "../ipa_data.h"
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#include "../ipa_endpoint.h"
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#include "../ipa_mem.h"
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/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */
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enum ipa_resource_type {
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/* Source resource types; first must have value 0 */
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IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
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IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
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IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
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/* Destination resource types; first must have value 0 */
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IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
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IPA_RESOURCE_TYPE_DST_DPS_DMARS,
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IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
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};
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/* Resource groups used for an SoC having IPA v5.0 */
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enum ipa_rsrc_group_id {
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/* Source resource group identifiers */
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IPA_RSRC_GROUP_SRC_UL = 0,
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IPA_RSRC_GROUP_SRC_DL,
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IPA_RSRC_GROUP_SRC_UNUSED_2,
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IPA_RSRC_GROUP_SRC_UNUSED_3,
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IPA_RSRC_GROUP_SRC_URLLC,
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IPA_RSRC_GROUP_SRC_U_RX_QC,
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IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
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/* Destination resource group identifiers */
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IPA_RSRC_GROUP_DST_UL = 0,
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IPA_RSRC_GROUP_DST_DL,
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IPA_RSRC_GROUP_DST_DMA,
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IPA_RSRC_GROUP_DST_QDSS,
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IPA_RSRC_GROUP_DST_CV2X,
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IPA_RSRC_GROUP_DST_UC,
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IPA_RSRC_GROUP_DST_DRB_IP,
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IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
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};
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/* QSB configuration data for an SoC having IPA v5.0 */
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static const struct ipa_qsb_data ipa_qsb_data[] = {
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[IPA_QSB_MASTER_DDR] = {
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.max_writes = 0,
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.max_reads = 0, /* no limit (hardware max) */
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.max_reads_beats = 0,
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},
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[IPA_QSB_MASTER_PCIE] = {
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.max_writes = 0,
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.max_reads = 0, /* no limit (hardware max) */
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.max_reads_beats = 0,
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},
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};
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/* Endpoint configuration data for an SoC having IPA v5.0 */
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static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
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[IPA_ENDPOINT_AP_COMMAND_TX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 12,
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.endpoint_id = 14,
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.toward_ipa = true,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 20,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_SRC_UL,
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.dma_mode = true,
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.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
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.tx = {
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.seq_type = IPA_SEQ_DMA,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_LAN_RX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 13,
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.endpoint_id = 16,
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.toward_ipa = false,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 9,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_DST_UL,
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.aggregation = true,
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.status_enable = true,
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.rx = {
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.buffer_size = 8192,
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.pad_align = ilog2(sizeof(u32)),
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.aggr_time_limit = 500,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_MODEM_TX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 11,
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.endpoint_id = 2,
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.toward_ipa = true,
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.channel = {
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.tre_count = 512,
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.event_count = 512,
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.tlv_count = 25,
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},
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.endpoint = {
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.filter_support = true,
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.config = {
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.resource_group = IPA_RSRC_GROUP_SRC_UL,
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.checksum = true,
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.qmap = true,
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.status_enable = true,
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.tx = {
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.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
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.status_endpoint =
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IPA_ENDPOINT_MODEM_AP_RX,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_MODEM_RX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 1,
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.endpoint_id = 23,
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.toward_ipa = false,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 9,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_DST_DL,
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.checksum = true,
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.qmap = true,
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.aggregation = true,
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.rx = {
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.buffer_size = 8192,
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.aggr_time_limit = 500,
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.aggr_close_eof = true,
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},
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},
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},
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},
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[IPA_ENDPOINT_MODEM_AP_TX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 0,
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.endpoint_id = 12,
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.toward_ipa = true,
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.endpoint = {
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.filter_support = true,
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},
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},
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[IPA_ENDPOINT_MODEM_AP_RX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 7,
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.endpoint_id = 21,
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.toward_ipa = false,
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},
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[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 2,
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.endpoint_id = 15,
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.toward_ipa = true,
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.endpoint = {
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.filter_support = true,
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},
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},
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};
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/* Source resource configuration data for an SoC having IPA v5.0 */
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static const struct ipa_resource ipa_resource_src[] = {
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[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL] = {
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.min = 3, .max = 9,
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},
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.limits[IPA_RSRC_GROUP_SRC_DL] = {
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.min = 4, .max = 10,
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},
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.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
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.min = 1, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
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.min = 0, .max = 63,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL] = {
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.min = 9, .max = 9,
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},
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.limits[IPA_RSRC_GROUP_SRC_DL] = {
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.min = 12, .max = 12,
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},
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.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
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.min = 10, .max = 10,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
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.limits[IPA_RSRC_GROUP_SRC_UL] = {
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.min = 9, .max = 9,
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},
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.limits[IPA_RSRC_GROUP_SRC_DL] = {
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.min = 24, .max = 24,
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},
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.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
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.min = 20, .max = 20,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_DL] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
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.min = 1, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
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.min = 0, .max = 63,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
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.limits[IPA_RSRC_GROUP_SRC_UL] = {
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.min = 22, .max = 22,
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},
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.limits[IPA_RSRC_GROUP_SRC_DL] = {
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.min = 16, .max = 16,
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},
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.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
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.min = 16, .max = 16,
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},
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},
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};
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/* Destination resource configuration data for an SoC having IPA v5.0 */
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static const struct ipa_resource ipa_resource_dst[] = {
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[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
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.limits[IPA_RSRC_GROUP_DST_UL] = {
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.min = 6, .max = 6,
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},
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.limits[IPA_RSRC_GROUP_DST_DL] = {
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.min = 5, .max = 5,
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},
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.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
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.min = 39, .max = 39,
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},
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},
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[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
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.limits[IPA_RSRC_GROUP_DST_UL] = {
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.min = 0, .max = 3,
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},
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.limits[IPA_RSRC_GROUP_DST_DL] = {
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.min = 0, .max = 3,
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},
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},
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[IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
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.limits[IPA_RSRC_GROUP_DST_UL] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_DST_DL] = {
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.min = 0, .max = 63,
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},
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},
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};
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/* Resource configuration data for an SoC having IPA v5.0 */
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static const struct ipa_resource_data ipa_resource_data = {
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.rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
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.rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
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.resource_src_count = ARRAY_SIZE(ipa_resource_src),
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.resource_src = ipa_resource_src,
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.resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
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.resource_dst = ipa_resource_dst,
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};
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/* IPA-resident memory region data for an SoC having IPA v5.0 */
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static const struct ipa_mem ipa_mem_local_data[] = {
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{
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.id = IPA_MEM_UC_EVENT_RING,
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.offset = 0x0000,
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.size = 0x1000,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_UC_SHARED,
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.offset = 0x1000,
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.size = 0x0080,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_UC_INFO,
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.offset = 0x1080,
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.size = 0x0200,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_V4_FILTER_HASHED,
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.offset = 0x1288,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V4_FILTER,
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.offset = 0x1308,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_FILTER_HASHED,
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.offset = 0x1388,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_FILTER,
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.offset = 0x1408,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V4_ROUTE_HASHED,
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.offset = 0x1488,
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.size = 0x0098,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V4_ROUTE,
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.offset = 0x1528,
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.size = 0x0098,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_ROUTE_HASHED,
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.offset = 0x15c8,
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.size = 0x0098,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_ROUTE,
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.offset = 0x1668,
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.size = 0x0098,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_MODEM_HEADER,
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.offset = 0x1708,
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.size = 0x0240,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_AP_HEADER,
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.offset = 0x1948,
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.size = 0x01e0,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_MODEM_PROC_CTX,
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.offset = 0x1b40,
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.size = 0x0b20,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_AP_PROC_CTX,
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.offset = 0x2660,
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.size = 0x0200,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_STATS_QUOTA_MODEM,
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.offset = 0x2868,
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.size = 0x0060,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_STATS_QUOTA_AP,
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.offset = 0x28c8,
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.size = 0x0048,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_AP_V4_FILTER,
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.offset = 0x2918,
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.size = 0x0118,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_AP_V6_FILTER,
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.offset = 0x2aa0,
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.size = 0x0228,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_STATS_FILTER_ROUTE,
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.offset = 0x2cd0,
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.size = 0x0ba0,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_STATS_DROP,
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.offset = 0x3870,
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.size = 0x0020,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_MODEM,
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.offset = 0x3898,
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.size = 0x0d48,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_NAT_TABLE,
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.offset = 0x45e0,
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.size = 0x0900,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_PDN_CONFIG,
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.offset = 0x4ee8,
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.size = 0x0100,
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.canary_count = 2,
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},
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};
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/* Memory configuration data for an SoC having IPA v5.0 */
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static const struct ipa_mem_data ipa_mem_data = {
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.local_count = ARRAY_SIZE(ipa_mem_local_data),
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.local = ipa_mem_local_data,
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.imem_addr = 0x14688000,
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.imem_size = 0x00003000,
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.smem_id = 497,
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.smem_size = 0x00009000,
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};
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/* Interconnect rates are in 1000 byte/second units */
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static const struct ipa_interconnect_data ipa_interconnect_data[] = {
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{
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.name = "memory",
|
||||
.peak_bandwidth = 1900000, /* 1.9 GBps */
|
||||
.average_bandwidth = 600000, /* 600 MBps */
|
||||
},
|
||||
/* Average rate is unused for the next interconnect */
|
||||
{
|
||||
.name = "config",
|
||||
.peak_bandwidth = 76800, /* 76.8 MBps */
|
||||
.average_bandwidth = 0, /* unused */
|
||||
},
|
||||
};
|
||||
|
||||
/* Clock and interconnect configuration data for an SoC having IPA v5.0 */
|
||||
static const struct ipa_power_data ipa_power_data = {
|
||||
.core_clock_rate = 120 * 1000 * 1000, /* Hz */
|
||||
.interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
|
||||
.interconnect_data = ipa_interconnect_data,
|
||||
};
|
||||
|
||||
/* Configuration data for an SoC having IPA v5.0. */
|
||||
const struct ipa_data ipa_data_v5_0 = {
|
||||
.version = IPA_VERSION_5_0,
|
||||
.qsb_count = ARRAY_SIZE(ipa_qsb_data),
|
||||
.qsb_data = ipa_qsb_data,
|
||||
.modem_route_count = 11,
|
||||
.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
|
||||
.endpoint_data = ipa_gsi_endpoint_data,
|
||||
.resource_data = &ipa_resource_data,
|
||||
.mem_data = &ipa_mem_data,
|
||||
.power_data = &ipa_power_data,
|
||||
};
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2019-2022 Linaro Ltd.
|
||||
* Copyright (C) 2019-2023 Linaro Ltd.
|
||||
*/
|
||||
#ifndef _IPA_DATA_H_
|
||||
#define _IPA_DATA_H_
|
||||
|
|
@ -249,5 +249,6 @@ extern const struct ipa_data ipa_data_v4_5;
|
|||
extern const struct ipa_data ipa_data_v4_7;
|
||||
extern const struct ipa_data ipa_data_v4_9;
|
||||
extern const struct ipa_data ipa_data_v4_11;
|
||||
extern const struct ipa_data ipa_data_v5_0;
|
||||
|
||||
#endif /* _IPA_DATA_H_ */
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
|
|||
} else if (ipa->version < IPA_VERSION_4_5) {
|
||||
val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS);
|
||||
} else {
|
||||
/* For IPA v4.5 FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */
|
||||
/* For IPA v4.5+ FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */
|
||||
}
|
||||
|
||||
val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS);
|
||||
|
|
@ -684,6 +684,10 @@ static const struct of_device_id ipa_match[] = {
|
|||
.compatible = "qcom,sc7280-ipa",
|
||||
.data = &ipa_data_v4_11,
|
||||
},
|
||||
{
|
||||
.compatible = "qcom,sdx65-ipa",
|
||||
.data = &ipa_data_v5_0,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ipa_match);
|
||||
|
|
|
|||
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