pinctrl: bcm: make use of raw_spinlock variants
The bcm pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Родитель
a9ee6bd44c
Коммит
cb96a66243
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@ -99,7 +99,7 @@ struct iproc_gpio {
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void __iomem *base;
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void __iomem *io_ctrl;
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spinlock_t lock;
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raw_spinlock_t lock;
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struct gpio_chip gc;
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unsigned num_banks;
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@ -221,9 +221,9 @@ static void iproc_gpio_irq_mask(struct irq_data *d)
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_gpio_irq_set_mask(d, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void iproc_gpio_irq_unmask(struct irq_data *d)
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@ -232,9 +232,9 @@ static void iproc_gpio_irq_unmask(struct irq_data *d)
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_gpio_irq_set_mask(d, true);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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@ -274,13 +274,13 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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return -EINVAL;
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}
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
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level_triggered);
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iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
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iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
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rising_or_high);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev,
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"gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
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@ -328,9 +328,9 @@ static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
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@ -343,10 +343,10 @@ static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
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iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
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@ -358,9 +358,9 @@ static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
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}
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@ -461,7 +461,7 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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if (disable) {
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iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false);
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@ -471,7 +471,7 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
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iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true);
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
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@ -483,10 +483,10 @@ static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
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*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
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@ -515,7 +515,7 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
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dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
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strength);
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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strength = (strength / 2) - 1;
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for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
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val = readl(base + offset);
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@ -524,7 +524,7 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
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writel(val, base + offset);
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offset += 4;
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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@ -548,7 +548,7 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
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shift = IPROC_GPIO_SHIFT(gpio);
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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*strength = 0;
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for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
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val = readl(base + offset) & BIT(shift);
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@ -559,7 +559,7 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
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/* convert to mA */
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*strength = (*strength + 1) * 2;
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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@ -769,7 +769,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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spin_lock_init(&chip->lock);
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raw_spin_lock_init(&chip->lock);
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gc = &chip->gc;
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gc->base = -1;
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@ -73,7 +73,7 @@ struct nsp_gpio {
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctldesc;
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struct irq_domain *irq_domain;
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spinlock_t lock;
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raw_spinlock_t lock;
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};
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enum base_type {
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@ -203,9 +203,9 @@ static void nsp_gpio_irq_mask(struct irq_data *d)
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_gpio_irq_set_mask(d, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void nsp_gpio_irq_unmask(struct irq_data *d)
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@ -213,9 +213,9 @@ static void nsp_gpio_irq_unmask(struct irq_data *d)
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_gpio_irq_set_mask(d, true);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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@ -226,7 +226,7 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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bool falling;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
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level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
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@ -250,13 +250,13 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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default:
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dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
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type);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return -EINVAL;
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}
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nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
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nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
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level_low ? "true" : "false", falling ? "true" : "false");
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@ -295,9 +295,9 @@ static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
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return 0;
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@ -309,10 +309,10 @@ static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
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nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
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return 0;
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@ -323,9 +323,9 @@ static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
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struct nsp_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
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}
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@ -381,10 +381,10 @@ static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
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nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
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gpio, pull_up, pull_down);
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@ -396,10 +396,10 @@ static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
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*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
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@ -417,7 +417,7 @@ static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
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offset = NSP_GPIO_DRV_CTRL;
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dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
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strength);
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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strength = (strength / 2) - 1;
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for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
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val = readl(chip->io_ctrl + offset);
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@ -426,7 +426,7 @@ static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
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writel(val, chip->io_ctrl + offset);
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offset += 4;
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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@ -442,7 +442,7 @@ static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
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offset = NSP_GPIO_DRV_CTRL;
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shift = gpio;
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spin_lock_irqsave(&chip->lock, flags);
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raw_spin_lock_irqsave(&chip->lock, flags);
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*strength = 0;
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for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
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val = readl(chip->io_ctrl + offset) & BIT(shift);
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@ -453,7 +453,7 @@ static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
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/* convert to mA */
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*strength = (*strength + 1) * 2;
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spin_unlock_irqrestore(&chip->lock, flags);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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@ -660,7 +660,7 @@ static int nsp_gpio_probe(struct platform_device *pdev)
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return PTR_ERR(chip->io_ctrl);
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}
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spin_lock_init(&chip->lock);
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raw_spin_lock_init(&chip->lock);
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gc = &chip->gc;
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gc->base = -1;
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gc->can_sleep = false;
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