[ALSA] emu10k1: Update registers defines for the Audigy 2/emu10k2.5
Signed-off-by: James Courtier-Dutton <James@superbug.co.uk> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
James Courtier-Dutton
Jaroslav Kysela
Родитель
7c157069bc
Коммит
cbb7d8f9b7
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@ -460,6 +460,7 @@
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#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
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#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
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#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
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#define MAPA 0x0c /* Cache map A */
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#define MAPB 0x0d /* Cache map B */
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@ -467,6 +468,8 @@
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#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
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#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
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/* 0x0e, 0x0f: Not used */
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#define ENVVOL 0x10 /* Volume envelope register */
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#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
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/* 0x8000-n == 666*n usec delay */
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@ -555,7 +558,7 @@
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/* NOTE: All channels contain internal variables; do */
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/* not write to these locations. */
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/* 1f something */
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/* 0x1f: not used */
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#define CD0 0x20 /* Cache data 0 register */
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#define CD1 0x21 /* Cache data 1 register */
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@ -625,6 +628,8 @@
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#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
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#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
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#define A_TBLSZ ` 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
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#define TCBS 0x44 /* Tank cache buffer size register */
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#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
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#define TCBS_BUFFSIZE_16K 0x00000000
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@ -645,7 +650,7 @@
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#define FXBA 0x47 /* FX Buffer Address */
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#define FXBA_MASK 0xfffff000 /* 20 bit base address */
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/* 0x48 something - word access, defaults to 3f */
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#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
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#define MICBS 0x49 /* Microphone buffer size register */
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@ -689,6 +694,18 @@
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#define ADCBS_BUFSIZE_57344 0x0000001e
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#define ADCBS_BUFSIZE_65536 0x0000001f
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/* Current Send B, A Amounts */
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#define A_CSBA 0x4c
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/* Current Send D, C Amounts */
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#define A_CSDC 0x4d
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/* Current Send F, E Amounts */
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#define A_CSFE 0x4e
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/* Current Send H, G Amounts */
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#define A_CSHG 0x4f
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#define CDCS 0x50 /* CD-ROM digital channel status register */
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@ -696,6 +713,9 @@
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#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
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/* S/PDIF Input C Channel Status */
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#define A_SPSC 0x52
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#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
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#define A_DBG 0x53
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@ -736,6 +756,8 @@
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#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
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#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
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/* 0x57: Not used */
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/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
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#define CLIEL 0x58 /* Channel loop interrupt enable low register */
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@ -761,6 +783,9 @@
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#define AC97SLOT_CNTR 0x10 /* Center enable */
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#define AC97SLOT_LFE 0x20 /* LFE enable */
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/* PCB Revision */
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#define A_PCB 0x5f
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// NOTE: 0x60,61,62: 64-bit
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#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
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@ -808,9 +833,18 @@
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#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
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// 0x6a,6b,6c used for some recording
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// 0x6d unused
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// 0x6e,6f - tanktable base / offset
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/* S/PDIF Host Record Index (bypasses SRC) */
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#define A_SPRI 0x6a
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/* S/PDIF Host Record Address */
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#define A_SPRA 0x6b
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/* S/PDIF Host Record Control */
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#define A_SPRC 0x6c
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/* Delayed Interrupt Counter & Enable */
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#define A_DICE 0x6d
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/* Tank Table Base */
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#define A_TTB 0x6e
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/* Tank Delay Offset */
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#define A_TDOF 0x6f
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/* This is the MPU port on the card (via the game port) */
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#define A_MUDATA1 0x70
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@ -828,6 +862,7 @@
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#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
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#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
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/* Extended Hardware Control */
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#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
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#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
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#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
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@ -850,8 +885,20 @@
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#define A_PCM_96000 0x00004000
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#define A_PCM_44100 0x00008000
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/* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */
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/* 0x7a, 0x7b - lookup tables */
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/* I2S0 Sample Rate Tracker Status */
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#define A_SRT3 0x77
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/* I2S1 Sample Rate Tracker Status */
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#define A_SRT4 0x78
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/* I2S2 Sample Rate Tracker Status */
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#define A_SRT5 0x79
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/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
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/* Tank Table DMA Address */
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#define A_TTDA 0x7a
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/* Tank Table DMA Data */
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#define A_TTDD 0x7b
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#define A_FXRT2 0x7c
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#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
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@ -873,7 +920,7 @@
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#define A_FXRT_CHANNELC 0x003f0000
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#define A_FXRT_CHANNELD 0x3f000000
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/* 0x7f: Not used */
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/* Each FX general purpose register is 32 bits in length, all bits are used */
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#define FXGPREGBASE 0x100 /* FX general purpose registers base */
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#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
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