media: ti-vpe: cal: Stop write DMA without disabling PPI
When stopping the stream, the driver needs to ensure that ongoing DMA completes and that no new DMA is started. It does so using a feature of the PPI that can be stopped on a frame boundary. The downside of this mechanism is that the DMA can't be stopped independently of the source, which prevents usage of multiple contexts for the same source (to handle CSI-2 virtual channels or data types). Rework the stream stop mechanism to stop the write DMA without disabling the PPI first. The new mechanism relies on the combination of a state machine in the driver and shadowing of the CAL_WR_DMA_CTRL_j.MODE field in the hardware. When a stop is requested, the DMA start interrupt handler will request the hardware to stop at the end of the current frame by disabling the write DMA context in the shadowed register, and flag that a stop is in progress. The next DMA end interrupt will then report that the stop is complete. This makes it possible to stop the PPI after stopping the DMA, and fold the cal_camerarx_ppi_disable() call into cal_camerarx_stop(). Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
Родитель
172ba79daf
Коммит
cbb8cd7cc1
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@ -258,13 +258,11 @@ static void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
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static void cal_camerarx_ppi_enable(struct cal_camerarx *phy)
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{
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cal_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
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CAL_CSI2_PPI_CTRL_FRAME_MASK);
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cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
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1, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
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}
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void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
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static void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
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{
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cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
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0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
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@ -409,6 +407,8 @@ static void cal_camerarx_stop(struct cal_camerarx *phy)
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unsigned int i;
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int ret;
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cal_camerarx_ppi_disable(phy);
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cal_camerarx_disable_irqs(phy);
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cal_camerarx_power(phy, false);
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@ -9,7 +9,6 @@
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#include <linux/delay.h>
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#include <linux/ioctl.h>
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#include <linux/pm_runtime.h>
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#include <linux/videodev2.h>
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@ -511,6 +510,7 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count)
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addr = vb2_dma_contig_plane_dma_addr(&ctx->cur_frm->vb.vb2_buf, 0);
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ctx->sequence = 0;
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ctx->dma_state = CAL_DMA_RUNNING;
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pm_runtime_get_sync(ctx->cal->dev);
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@ -530,6 +530,10 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count)
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return 0;
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err:
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cal_ctx_wr_dma_disable(ctx);
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cal_ctx_disable_irqs(ctx);
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ctx->dma_state = CAL_DMA_STOPPED;
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spin_lock_irqsave(&ctx->slock, flags);
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vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
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ctx->cur_frm = NULL;
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@ -547,26 +551,9 @@ static void cal_stop_streaming(struct vb2_queue *vq)
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struct cal_ctx *ctx = vb2_get_drv_priv(vq);
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struct cal_dmaqueue *dma_q = &ctx->vidq;
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struct cal_buffer *buf, *tmp;
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unsigned long timeout;
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unsigned long flags;
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bool dma_act;
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cal_camerarx_ppi_disable(ctx->phy);
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/* wait for stream and dma to finish */
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dma_act = true;
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timeout = jiffies + msecs_to_jiffies(500);
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while (dma_act && time_before(jiffies, timeout)) {
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msleep(50);
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spin_lock_irqsave(&ctx->slock, flags);
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dma_act = ctx->dma_act;
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spin_unlock_irqrestore(&ctx->slock, flags);
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}
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if (dma_act)
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ctx_err(ctx, "failed to disable dma cleanly\n");
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cal_ctx_wr_dma_stop(ctx);
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cal_ctx_disable_irqs(ctx);
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v4l2_subdev_call(&ctx->phy->subdev, video, s_stream, 0);
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@ -745,6 +732,7 @@ int cal_ctx_v4l2_init(struct cal_ctx *ctx)
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INIT_LIST_HEAD(&ctx->vidq.active);
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spin_lock_init(&ctx->slock);
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mutex_init(&ctx->mutex);
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init_waitqueue_head(&ctx->dma_wait);
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/* Initialize the vb2 queue. */
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q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
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@ -411,6 +411,45 @@ void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
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cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->index), dmaaddr);
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}
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void cal_ctx_wr_dma_disable(struct cal_ctx *ctx)
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{
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u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index));
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cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_DIS,
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CAL_WR_DMA_CTRL_MODE_MASK);
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cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->index), val);
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}
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static bool cal_ctx_wr_dma_stopped(struct cal_ctx *ctx)
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{
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bool stopped;
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spin_lock_irq(&ctx->slock);
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stopped = ctx->dma_state == CAL_DMA_STOPPED;
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spin_unlock_irq(&ctx->slock);
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return stopped;
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}
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int cal_ctx_wr_dma_stop(struct cal_ctx *ctx)
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{
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long timeout;
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/* Request DMA stop and wait until it completes. */
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spin_lock_irq(&ctx->slock);
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ctx->dma_state = CAL_DMA_STOP_REQUESTED;
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spin_unlock_irq(&ctx->slock);
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timeout = wait_event_timeout(ctx->dma_wait, cal_ctx_wr_dma_stopped(ctx),
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msecs_to_jiffies(500));
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if (!timeout) {
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ctx_err(ctx, "failed to disable dma cleanly\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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void cal_ctx_enable_irqs(struct cal_ctx *ctx)
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{
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/* Enable IRQ_WDMA_END and IRQ_WDMA_START. */
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@ -434,35 +473,71 @@ void cal_ctx_disable_irqs(struct cal_ctx *ctx)
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* ------------------------------------------------------------------
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*/
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static inline void cal_schedule_next_buffer(struct cal_ctx *ctx)
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static inline void cal_irq_wdma_start(struct cal_ctx *ctx)
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{
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struct cal_dmaqueue *dma_q = &ctx->vidq;
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struct cal_buffer *buf;
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unsigned long addr;
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buf = list_entry(dma_q->active.next, struct cal_buffer, list);
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ctx->next_frm = buf;
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list_del(&buf->list);
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spin_lock(&ctx->slock);
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addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
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cal_ctx_wr_dma_addr(ctx, addr);
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if (ctx->dma_state == CAL_DMA_STOP_REQUESTED) {
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/*
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* If a stop is requested, disable the write DMA context
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* immediately. The CAL_WR_DMA_CTRL_j.MODE field is shadowed,
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* the current frame will complete and the DMA will then stop.
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*/
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cal_ctx_wr_dma_disable(ctx);
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ctx->dma_state = CAL_DMA_STOP_PENDING;
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} else if (!list_empty(&dma_q->active) &&
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ctx->cur_frm == ctx->next_frm) {
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/*
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* Otherwise, if a new buffer is available, queue it to the
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* hardware.
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*/
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struct cal_buffer *buf;
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unsigned long addr;
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buf = list_entry(dma_q->active.next, struct cal_buffer, list);
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addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
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cal_ctx_wr_dma_addr(ctx, addr);
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ctx->next_frm = buf;
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list_del(&buf->list);
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}
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spin_unlock(&ctx->slock);
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}
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static inline void cal_process_buffer_complete(struct cal_ctx *ctx)
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static inline void cal_irq_wdma_end(struct cal_ctx *ctx)
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{
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ctx->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
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ctx->cur_frm->vb.field = ctx->v_fmt.fmt.pix.field;
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ctx->cur_frm->vb.sequence = ctx->sequence++;
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struct cal_buffer *buf = NULL;
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vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
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ctx->cur_frm = ctx->next_frm;
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spin_lock(&ctx->slock);
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/* If the DMA context was stopping, it is now stopped. */
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if (ctx->dma_state == CAL_DMA_STOP_PENDING) {
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ctx->dma_state = CAL_DMA_STOPPED;
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wake_up(&ctx->dma_wait);
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}
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/* If a new buffer was queued, complete the current buffer. */
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if (ctx->cur_frm != ctx->next_frm) {
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buf = ctx->cur_frm;
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ctx->cur_frm = ctx->next_frm;
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}
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spin_unlock(&ctx->slock);
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if (buf) {
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buf->vb.vb2_buf.timestamp = ktime_get_ns();
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buf->vb.field = ctx->v_fmt.fmt.pix.field;
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buf->vb.sequence = ctx->sequence++;
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vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
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}
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}
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static irqreturn_t cal_irq(int irq_cal, void *data)
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{
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struct cal_dev *cal = data;
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struct cal_ctx *ctx;
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struct cal_dmaqueue *dma_q;
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u32 status;
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status = cal_read(cal, CAL_HL_IRQSTATUS(0));
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@ -497,17 +572,8 @@ static irqreturn_t cal_irq(int irq_cal, void *data)
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cal_write(cal, CAL_HL_IRQSTATUS(1), status);
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for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
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if (status & CAL_HL_IRQ_MASK(i)) {
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ctx = cal->ctx[i];
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spin_lock(&ctx->slock);
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ctx->dma_act = false;
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if (ctx->cur_frm != ctx->next_frm)
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cal_process_buffer_complete(ctx);
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spin_unlock(&ctx->slock);
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}
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if (status & CAL_HL_IRQ_MASK(i))
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cal_irq_wdma_end(cal->ctx[i]);
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}
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}
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@ -520,17 +586,8 @@ static irqreturn_t cal_irq(int irq_cal, void *data)
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cal_write(cal, CAL_HL_IRQSTATUS(2), status);
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for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
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if (status & CAL_HL_IRQ_MASK(i)) {
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ctx = cal->ctx[i];
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dma_q = &ctx->vidq;
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spin_lock(&ctx->slock);
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ctx->dma_act = true;
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if (!list_empty(&dma_q->active) &&
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ctx->cur_frm == ctx->next_frm)
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cal_schedule_next_buffer(ctx);
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spin_unlock(&ctx->slock);
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}
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if (status & CAL_HL_IRQ_MASK(i))
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cal_irq_wdma_start(cal->ctx[i]);
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}
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}
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@ -17,6 +17,7 @@
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <linux/wait.h>
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#include <media/media-device.h>
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#include <media/v4l2-async.h>
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@ -60,6 +61,13 @@ enum cal_camerarx_field {
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F_MAX_FIELDS,
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};
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enum cal_dma_state {
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CAL_DMA_RUNNING,
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CAL_DMA_STOP_REQUESTED,
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CAL_DMA_STOP_PENDING,
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CAL_DMA_STOPPED,
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};
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struct cal_format_info {
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u32 fourcc;
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u32 code;
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@ -190,7 +198,8 @@ struct cal_ctx {
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/* Pointer pointing to next v4l2_buffer */
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struct cal_buffer *next_frm;
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bool dma_act;
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enum cal_dma_state dma_state;
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struct wait_queue_head dma_wait;
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};
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extern unsigned int cal_debug;
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@ -262,7 +271,6 @@ const struct cal_format_info *cal_format_by_code(u32 code);
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void cal_quickdump_regs(struct cal_dev *cal);
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void cal_camerarx_disable(struct cal_camerarx *phy);
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void cal_camerarx_ppi_disable(struct cal_camerarx *phy);
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void cal_camerarx_i913_errata(struct cal_camerarx *phy);
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struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
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unsigned int instance);
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@ -272,6 +280,8 @@ void cal_ctx_csi2_config(struct cal_ctx *ctx);
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void cal_ctx_pix_proc_config(struct cal_ctx *ctx);
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void cal_ctx_wr_dma_config(struct cal_ctx *ctx);
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void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr);
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void cal_ctx_wr_dma_disable(struct cal_ctx *ctx);
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int cal_ctx_wr_dma_stop(struct cal_ctx *ctx);
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void cal_ctx_enable_irqs(struct cal_ctx *ctx);
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void cal_ctx_disable_irqs(struct cal_ctx *ctx);
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