spi: iproc-qspi: Add Broadcom iProc SoCs support
This spi driver uses the common spi-bcm-qspi driver and implements iProc SoCs specific interrupt controller. The common driver now calls the SoC handlers when present. Adding support for both muxed l1 and unmuxed interrupt sources. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kamal Dasu
Mark Brown
Родитель
71b8f350a4
Коммит
cc20a38612
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@ -21,7 +21,7 @@ obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm2835aux.o
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obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
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obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
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obj-$(CONFIG_SPI_BCM_QSPI) += spi-brcmstb-qspi.o spi-bcm-qspi.o
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obj-$(CONFIG_SPI_BCM_QSPI) += spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi.o
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obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
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obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
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obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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@ -175,9 +175,15 @@ enum base_type {
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BASEMAX,
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};
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enum irq_source {
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SINGLE_L2,
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MUXED_L1,
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};
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struct bcm_qspi_irq {
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const char *irq_name;
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const irq_handler_t irq_handler;
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int irq_source;
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u32 mask;
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};
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@ -198,6 +204,10 @@ struct bcm_qspi {
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u32 base_clk;
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u32 max_speed_hz;
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void __iomem *base[BASEMAX];
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/* Some SoCs provide custom interrupt status register(s) */
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struct bcm_qspi_soc_intc *soc_intc;
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struct bcm_qspi_parms last_parms;
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struct qspi_trans trans_pos;
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int curr_cs;
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@ -806,6 +816,7 @@ static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
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u32 addr = 0, len, len_words;
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int ret = 0;
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unsigned long timeo = msecs_to_jiffies(100);
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struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
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if (bcm_qspi_bspi_ver_three(qspi))
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if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
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@ -850,6 +861,15 @@ static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
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bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
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bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
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if (qspi->soc_intc) {
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/*
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* clear soc MSPI and BSPI interrupts and enable
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* BSPI interrupts.
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*/
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soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
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soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
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}
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/* Must flush previous writes before starting BSPI operation */
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mb();
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@ -952,9 +972,12 @@ static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
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u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
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if (status & MSPI_MSPI_STATUS_SPIF) {
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struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
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/* clear interrupt */
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status &= ~MSPI_MSPI_STATUS_SPIF;
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bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
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if (qspi->soc_intc)
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soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
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complete(&qspi->mspi_done);
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return IRQ_HANDLED;
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}
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@ -966,20 +989,33 @@ static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
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{
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struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
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struct bcm_qspi *qspi = qspi_dev_id->dev;
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u32 status;
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struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
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u32 status = qspi_dev_id->irqp->mask;
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if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
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bcm_qspi_bspi_lr_data_read(qspi);
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if (qspi->bspi_rf_msg_len == 0) {
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qspi->bspi_rf_msg = NULL;
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if (qspi->soc_intc) {
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/* disable soc BSPI interrupt */
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soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
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false);
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/* indicate done */
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status = INTR_BSPI_LR_SESSION_DONE_MASK;
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}
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if (qspi->bspi_rf_msg_status)
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bcm_qspi_bspi_lr_clear(qspi);
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else
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bcm_qspi_bspi_flush_prefetch_buffers(qspi);
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}
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if (qspi->soc_intc)
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/* clear soc BSPI interrupt */
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soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
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}
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status = (qspi_dev_id->irqp->mask & INTR_BSPI_LR_SESSION_DONE_MASK);
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status &= INTR_BSPI_LR_SESSION_DONE_MASK;
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if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
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complete(&qspi->bspi_done);
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@ -990,13 +1026,39 @@ static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
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{
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struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
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struct bcm_qspi *qspi = qspi_dev_id->dev;
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struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
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dev_err(&qspi->pdev->dev, "BSPI INT error\n");
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qspi->bspi_rf_msg_status = -EIO;
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if (qspi->soc_intc)
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/* clear soc interrupt */
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soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
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complete(&qspi->bspi_done);
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return IRQ_HANDLED;
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}
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static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
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{
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struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
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struct bcm_qspi *qspi = qspi_dev_id->dev;
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struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
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irqreturn_t ret = IRQ_NONE;
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if (soc_intc) {
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u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
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if (status & MSPI_DONE)
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ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
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else if (status & BSPI_DONE)
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ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
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else if (status & BSPI_ERR)
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ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
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}
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return ret;
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}
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static const struct bcm_qspi_irq qspi_irq_tab[] = {
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{
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.irq_name = "spi_lr_fullness_reached",
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@ -1036,6 +1098,13 @@ static const struct bcm_qspi_irq qspi_irq_tab[] = {
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.irq_handler = bcm_qspi_mspi_l2_isr,
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.mask = INTR_MSPI_HALTED_MASK,
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},
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{
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/* single muxed L1 interrupt source */
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.irq_name = "spi_l1_intr",
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.irq_handler = bcm_qspi_l1_isr,
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.irq_source = MUXED_L1,
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.mask = QSPI_INTERRUPTS_ALL,
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},
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};
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static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
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@ -1182,7 +1251,13 @@ int bcm_qspi_probe(struct platform_device *pdev,
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for (val = 0; val < num_irqs; val++) {
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irq = -1;
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name = qspi_irq_tab[val].irq_name;
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irq = platform_get_irq_byname(pdev, name);
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if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
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/* get the l2 interrupts */
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irq = platform_get_irq_byname(pdev, name);
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} else if (!num_ints && soc_intc) {
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/* all mspi, bspi intrs muxed to one L1 intr */
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irq = platform_get_irq(pdev, 0);
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}
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if (irq >= 0) {
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ret = devm_request_irq(&pdev->dev, irq,
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@ -1209,6 +1284,17 @@ int bcm_qspi_probe(struct platform_device *pdev,
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goto qspi_probe_err;
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}
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/*
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* Some SoCs integrate spi controller (e.g., its interrupt bits)
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* in specific ways
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*/
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if (soc_intc) {
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qspi->soc_intc = soc_intc;
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soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
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} else {
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qspi->soc_intc = NULL;
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}
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qspi->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(qspi->clk)) {
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dev_warn(dev, "unable to get clock\n");
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@ -1288,6 +1374,11 @@ static int __maybe_unused bcm_qspi_resume(struct device *dev)
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bcm_qspi_hw_init(qspi);
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bcm_qspi_chip_select(qspi, qspi->curr_cs);
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if (qspi->soc_intc)
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/* enable MSPI interrupt */
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qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
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true);
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ret = clk_enable(qspi->clk);
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if (!ret)
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spi_master_resume(qspi->master);
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@ -48,10 +48,26 @@
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(INTR_MSPI_DONE_MASK | \
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INTR_MSPI_HALTED_MASK)
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#define QSPI_INTERRUPTS_ALL \
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(MSPI_INTERRUPTS_ALL | \
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BSPI_LR_INTERRUPTS_ALL)
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struct platform_device;
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struct dev_pm_ops;
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struct bcm_qspi_soc_intc;
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enum {
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MSPI_DONE = 0x1,
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BSPI_DONE = 0x2,
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BSPI_ERR = 0x4,
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MSPI_BSPI_DONE = 0x7
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};
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struct bcm_qspi_soc_intc {
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void (*bcm_qspi_int_ack)(struct bcm_qspi_soc_intc *soc_intc, int type);
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void (*bcm_qspi_int_set)(struct bcm_qspi_soc_intc *soc_intc, int type,
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bool en);
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u32 (*bcm_qspi_get_int_status)(struct bcm_qspi_soc_intc *soc_intc);
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};
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/* Read controller register*/
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static inline u32 bcm_qspi_readl(bool be, void __iomem *addr)
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@ -72,6 +88,22 @@ static inline void bcm_qspi_writel(bool be,
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writel_relaxed(data, addr);
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}
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static inline u32 get_qspi_mask(int type)
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{
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switch (type) {
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case MSPI_DONE:
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return INTR_MSPI_DONE_MASK;
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case BSPI_DONE:
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return BSPI_LR_INTERRUPTS_ALL;
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case MSPI_BSPI_DONE:
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return QSPI_INTERRUPTS_ALL;
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case BSPI_ERR:
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return BSPI_LR_INTERRUPTS_ERROR;
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}
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return 0;
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}
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/* The common driver functions to be called by the SoC platform driver */
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int bcm_qspi_probe(struct platform_device *pdev,
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struct bcm_qspi_soc_intc *soc_intc);
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@ -0,0 +1,163 @@
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/*
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* Copyright 2016 Broadcom Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "spi-bcm-qspi.h"
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#define INTR_BASE_BIT_SHIFT 0x02
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#define INTR_COUNT 0x07
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struct bcm_iproc_intc {
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struct bcm_qspi_soc_intc soc_intc;
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struct platform_device *pdev;
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void __iomem *int_reg;
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void __iomem *int_status_reg;
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spinlock_t soclock;
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bool big_endian;
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};
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static u32 bcm_iproc_qspi_get_l2_int_status(struct bcm_qspi_soc_intc *soc_intc)
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{
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struct bcm_iproc_intc *priv =
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container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
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void __iomem *mmio = priv->int_status_reg;
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int i;
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u32 val = 0, sts = 0;
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for (i = 0; i < INTR_COUNT; i++) {
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if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4)))
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val |= 1UL << i;
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}
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if (val & INTR_MSPI_DONE_MASK)
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sts |= MSPI_DONE;
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if (val & BSPI_LR_INTERRUPTS_ALL)
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sts |= BSPI_DONE;
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if (val & BSPI_LR_INTERRUPTS_ERROR)
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sts |= BSPI_ERR;
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return sts;
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}
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static void bcm_iproc_qspi_int_ack(struct bcm_qspi_soc_intc *soc_intc, int type)
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{
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struct bcm_iproc_intc *priv =
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container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
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void __iomem *mmio = priv->int_status_reg;
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u32 mask = get_qspi_mask(type);
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int i;
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for (i = 0; i < INTR_COUNT; i++) {
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if (mask & (1UL << i))
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bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4));
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}
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}
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static void bcm_iproc_qspi_int_set(struct bcm_qspi_soc_intc *soc_intc, int type,
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bool en)
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{
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struct bcm_iproc_intc *priv =
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container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
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void __iomem *mmio = priv->int_reg;
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u32 mask = get_qspi_mask(type);
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&priv->soclock, flags);
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val = bcm_qspi_readl(priv->big_endian, mmio);
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if (en)
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val = val | (mask << INTR_BASE_BIT_SHIFT);
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else
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val = val & ~(mask << INTR_BASE_BIT_SHIFT);
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bcm_qspi_writel(priv->big_endian, val, mmio);
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spin_unlock_irqrestore(&priv->soclock, flags);
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}
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static int bcm_iproc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct bcm_iproc_intc *priv;
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struct bcm_qspi_soc_intc *soc_intc;
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struct resource *res;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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soc_intc = &priv->soc_intc;
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priv->pdev = pdev;
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spin_lock_init(&priv->soclock);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr_regs");
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priv->int_reg = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->int_reg))
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return PTR_ERR(priv->int_reg);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"intr_status_reg");
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priv->int_status_reg = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->int_status_reg))
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return PTR_ERR(priv->int_status_reg);
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priv->big_endian = of_device_is_big_endian(dev->of_node);
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bcm_iproc_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
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bcm_iproc_qspi_int_set(soc_intc, MSPI_BSPI_DONE, false);
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soc_intc->bcm_qspi_int_ack = bcm_iproc_qspi_int_ack;
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soc_intc->bcm_qspi_int_set = bcm_iproc_qspi_int_set;
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soc_intc->bcm_qspi_get_int_status = bcm_iproc_qspi_get_l2_int_status;
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return bcm_qspi_probe(pdev, soc_intc);
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}
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static int bcm_iproc_remove(struct platform_device *pdev)
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{
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return bcm_qspi_remove(pdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm_iproc_of_match[] = {
|
||||
{ .compatible = "brcm,spi-nsp-qspi" },
|
||||
{ .compatible = "brcm,spi-ns2-qspi" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bcm_iproc_of_match);
|
||||
|
||||
static struct platform_driver bcm_iproc_driver = {
|
||||
.probe = bcm_iproc_probe,
|
||||
.remove = bcm_iproc_remove,
|
||||
.driver = {
|
||||
.name = "bcm_iproc",
|
||||
.pm = &bcm_qspi_pm_ops,
|
||||
.of_match_table = bcm_iproc_of_match,
|
||||
}
|
||||
};
|
||||
module_platform_driver(bcm_iproc_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Kamal Dasu");
|
||||
MODULE_DESCRIPTION("SPI flash driver for Broadcom iProc SoCs");
|
||||
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