drm/msm: Generated register update
Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5 Small bit of .c churn in the phy code to adapt to split up of phy related registers. Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark
Родитель
b3fbfa2343
Коммит
cc4c26d4ae
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -1258,11 +1258,17 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
|
|||
|
||||
#define REG_A2XX_NQWAIT_UNTIL 0x00000394
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a
|
||||
|
||||
#define REG_A2XX_RBBM_DEBUG 0x0000039b
|
||||
|
||||
|
|
@ -2922,10 +2928,28 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
|
|||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f
|
||||
|
||||
#define REG_A2XX_SQ_TEX_0 0x00000000
|
||||
#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
|
||||
#define A2XX_SQ_TEX_0_TYPE__SHIFT 0
|
||||
|
|
|
|||
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -1215,7 +1215,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
|
|||
#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
|
||||
|
|
@ -1328,7 +1328,7 @@ static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
|
|||
#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_GREEN 0x000020e5
|
||||
|
|
@ -1342,7 +1342,7 @@ static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
|
|||
#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_BLUE 0x000020e6
|
||||
|
|
@ -1356,7 +1356,7 @@ static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
|
|||
#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
|
||||
|
|
@ -1370,7 +1370,7 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
|
|||
#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
|
||||
|
|
|
|||
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -1085,7 +1085,7 @@ static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
|
|||
#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
|
||||
|
|
@ -1113,7 +1113,7 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
|
|||
#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
|
||||
|
|
@ -1141,7 +1141,7 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
|
|||
#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
|
||||
|
|
@ -1169,7 +1169,7 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
|
|||
#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
|
||||
|
|
|
|||
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -2021,6 +2021,7 @@ static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
|
|||
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
|
||||
|
||||
#define REG_A5XX_RBBM_STATUS3 0x00000530
|
||||
#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
|
||||
|
||||
#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
|
||||
|
||||
|
|
@ -2351,6 +2352,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|||
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
|
||||
|
||||
#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
|
||||
#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
|
||||
|
||||
#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
|
||||
|
||||
|
|
@ -2808,7 +2810,19 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|||
#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
|
||||
#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E001 0x0000e001
|
||||
#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
|
||||
static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
|
||||
static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E004 0x0000e004
|
||||
|
||||
|
|
@ -3345,7 +3359,7 @@ static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
|
|||
#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
|
||||
|
|
@ -3373,7 +3387,7 @@ static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
|
|||
#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
|
||||
|
|
@ -3401,7 +3415,7 @@ static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
|
|||
#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
|
||||
|
|
@ -3429,7 +3443,7 @@ static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
|
|||
#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
|
||||
|
|
@ -3806,7 +3820,25 @@ static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294
|
|||
|
||||
#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
|
||||
#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
|
||||
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
|
||||
}
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
|
||||
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
|
||||
}
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
|
||||
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VPC_PACK 0x0000e29d
|
||||
#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
|
||||
|
|
@ -3910,7 +3942,13 @@ static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su
|
|||
}
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E389 0x0000e389
|
||||
#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
|
||||
#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
|
||||
#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
|
||||
|
||||
|
|
@ -4302,7 +4340,12 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|||
#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
|
||||
|
||||
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
|
||||
static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
|
||||
}
|
||||
#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
|
||||
#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
|
||||
|
||||
|
|
@ -5192,8 +5235,8 @@ static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
|
|||
}
|
||||
|
||||
#define REG_A5XX_TEX_SAMP_2 0x00000002
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
|
||||
static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
|
||||
|
|
@ -5273,6 +5316,7 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A5XX_TEX_CONST_2 0x00000002
|
||||
#define A5XX_TEX_CONST_2_UNK4 0x00000010
|
||||
#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
|
||||
#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
|
||||
static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
|
||||
|
|
@ -5291,6 +5335,7 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
|
|||
{
|
||||
return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
|
||||
}
|
||||
#define A5XX_TEX_CONST_2_UNK31 0x80000000
|
||||
|
||||
#define REG_A5XX_TEX_CONST_3 0x00000003
|
||||
#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -292,6 +292,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
|
|||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
|
||||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
|
||||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
|
||||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
|
||||
|
|
@ -439,6 +441,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
|
|||
|
||||
#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
|
||||
|
||||
#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
|
||||
|
||||
#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
|
||||
|
||||
#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
|
||||
a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
|
||||
|
||||
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
|
||||
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
|
||||
rbmemptr_stats(ring, index, cpcycles_start));
|
||||
|
||||
/*
|
||||
|
|
@ -185,7 +185,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
}
|
||||
}
|
||||
|
||||
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
|
||||
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
|
||||
rbmemptr_stats(ring, index, cpcycles_end));
|
||||
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
|
||||
rbmemptr_stats(ring, index, alwayson_end));
|
||||
|
|
@ -727,8 +727,8 @@ static int a6xx_ucode_init(struct msm_gpu *gpu)
|
|||
}
|
||||
}
|
||||
|
||||
gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
|
||||
REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
|
||||
gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
|
||||
REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -859,7 +859,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
|
|||
gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
|
||||
|
||||
/* Select CP0 to always count cycles */
|
||||
gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
|
||||
gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
|
||||
|
||||
a6xx_set_ubwc_config(gpu);
|
||||
|
||||
|
|
|
|||
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -247,9 +247,9 @@ enum adreno_pm4_type3_packets {
|
|||
CP_DRAW_INDX_INDIRECT = 41,
|
||||
CP_DRAW_INDIRECT_MULTI = 42,
|
||||
CP_DRAW_AUTO = 36,
|
||||
CP_UNKNOWN_19 = 25,
|
||||
CP_UNKNOWN_1A = 26,
|
||||
CP_UNKNOWN_4E = 78,
|
||||
CP_DRAW_PRED_ENABLE_GLOBAL = 25,
|
||||
CP_DRAW_PRED_ENABLE_LOCAL = 26,
|
||||
CP_DRAW_PRED_SET = 78,
|
||||
CP_WIDE_REG_WRITE = 116,
|
||||
CP_SCRATCH_TO_REG = 77,
|
||||
CP_REG_TO_SCRATCH = 74,
|
||||
|
|
@ -267,6 +267,7 @@ enum adreno_pm4_type3_packets {
|
|||
CP_SKIP_IB2_ENABLE_GLOBAL = 29,
|
||||
CP_SKIP_IB2_ENABLE_LOCAL = 35,
|
||||
CP_SET_SUBDRAW_SIZE = 53,
|
||||
CP_WHERE_AM_I = 98,
|
||||
CP_SET_VISIBILITY_OVERRIDE = 100,
|
||||
CP_PREEMPT_ENABLE_GLOBAL = 105,
|
||||
CP_PREEMPT_ENABLE_LOCAL = 106,
|
||||
|
|
@ -298,7 +299,6 @@ enum adreno_pm4_type3_packets {
|
|||
CP_SET_BIN_DATA5_OFFSET = 46,
|
||||
CP_SET_CTXSWITCH_IB = 85,
|
||||
CP_REG_WRITE = 109,
|
||||
CP_WHERE_AM_I = 98,
|
||||
};
|
||||
|
||||
enum adreno_state_block {
|
||||
|
|
@ -400,6 +400,17 @@ enum a6xx_patch_type {
|
|||
enum a6xx_draw_indirect_opcode {
|
||||
INDIRECT_OP_NORMAL = 2,
|
||||
INDIRECT_OP_INDEXED = 4,
|
||||
INDIRECT_OP_INDIRECT_COUNT = 6,
|
||||
INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
|
||||
};
|
||||
|
||||
enum cp_draw_pred_src {
|
||||
PRED_SRC_MEM = 5,
|
||||
};
|
||||
|
||||
enum cp_draw_pred_test {
|
||||
NE_0_PASS = 0,
|
||||
EQ_0_PASS = 1,
|
||||
};
|
||||
|
||||
enum cp_cond_function {
|
||||
|
|
@ -1040,33 +1051,61 @@ static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
|
|||
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
|
||||
}
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002
|
||||
#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff
|
||||
#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0
|
||||
static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
|
||||
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
|
||||
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
|
||||
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
|
||||
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
|
||||
|
||||
#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
|
||||
|
||||
#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
|
||||
#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
|
||||
|
||||
#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
|
||||
#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
|
||||
|
||||
#define REG_CP_DRAW_PRED_SET_0 0x00000000
|
||||
#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
|
||||
#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4
|
||||
static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
|
||||
{
|
||||
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
|
||||
return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
|
||||
}
|
||||
#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
|
||||
#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8
|
||||
static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
|
||||
{
|
||||
return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
|
||||
}
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005
|
||||
#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff
|
||||
#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0
|
||||
static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;
|
||||
}
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
|
||||
|
||||
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008
|
||||
#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff
|
||||
#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0
|
||||
static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;
|
||||
}
|
||||
#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
|
||||
|
||||
static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -80,6 +88,10 @@ enum mdp5_pipe {
|
|||
SSPP_CURSOR1 = 12,
|
||||
};
|
||||
|
||||
enum mdp5_format {
|
||||
DUMMY = 0,
|
||||
};
|
||||
|
||||
enum mdp5_ctl_mode {
|
||||
MODE_NONE = 0,
|
||||
MODE_WB_0_BLOCK = 1,
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,228 @@
|
|||
#ifndef DSI_PHY_10NM_XML
|
||||
#define DSI_PHY_10NM_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
|
||||
|
||||
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
|
||||
|
||||
#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
|
||||
|
||||
|
||||
#endif /* DSI_PHY_10NM_XML */
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
#ifndef DSI_PHY_14NM_XML
|
||||
#define DSI_PHY_14NM_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
|
||||
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
|
||||
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
|
||||
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
|
||||
}
|
||||
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
|
||||
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
|
||||
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
|
||||
#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
|
||||
#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
|
||||
#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
|
||||
|
||||
#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
|
||||
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
|
||||
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
|
||||
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
|
||||
static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
|
||||
}
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
|
||||
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
|
||||
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
|
||||
|
||||
#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
|
||||
|
||||
|
||||
#endif /* DSI_PHY_14NM_XML */
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
#ifndef DSI_PHY_20NM_XML
|
||||
#define DSI_PHY_20NM_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
|
||||
|
||||
#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
|
||||
}
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
|
||||
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
|
||||
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
|
||||
|
||||
#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
|
||||
|
||||
#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
|
||||
|
||||
#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
|
||||
|
||||
#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
|
||||
|
||||
#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
|
||||
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
|
||||
|
||||
#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
|
||||
|
||||
#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
|
||||
|
||||
|
||||
#endif /* DSI_PHY_20NM_XML */
|
||||
|
|
@ -0,0 +1,385 @@
|
|||
#ifndef DSI_PHY_28NM_XML
|
||||
#define DSI_PHY_28NM_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
|
||||
|
||||
#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
|
||||
}
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
|
||||
|
||||
#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
|
||||
|
||||
#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
|
||||
|
||||
#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
|
||||
|
||||
#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
|
||||
|
||||
#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
|
||||
|
||||
#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
|
||||
|
||||
#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
|
||||
|
||||
#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
|
||||
|
||||
#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
|
||||
|
||||
#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
|
||||
|
||||
#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
|
||||
|
||||
#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
|
||||
|
||||
#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
|
||||
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
|
||||
|
||||
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
|
||||
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
|
||||
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
|
||||
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
|
||||
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
|
||||
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
|
||||
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
|
||||
}
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
|
||||
}
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
|
||||
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
|
||||
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
|
||||
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
|
||||
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
|
||||
|
||||
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
|
||||
|
||||
|
||||
#endif /* DSI_PHY_28NM_XML */
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
#ifndef DSI_PHY_28NM_8960_XML
|
||||
#define DSI_PHY_28NM_8960_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
|
||||
}
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
|
||||
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
|
||||
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
|
||||
#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
|
||||
#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
|
||||
|
||||
#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
|
||||
#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
|
||||
|
||||
|
||||
#endif /* DSI_PHY_28NM_8960_XML */
|
||||
|
|
@ -0,0 +1,480 @@
|
|||
#ifndef DSI_PHY_5NM_XML
|
||||
#define DSI_PHY_5NM_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_REVISION_ID0 0x00000000
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_REVISION_ID1 0x00000004
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_REVISION_ID2 0x00000008
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_REVISION_ID3 0x0000000c
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CLK_CFG0 0x00000010
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CLK_CFG1 0x00000014
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL 0x00000018
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL 0x0000001c
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0 0x00000020
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CTRL_0 0x00000024
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CTRL_1 0x00000028
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CTRL_2 0x0000002c
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CTRL_3 0x00000030
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CFG0 0x00000034
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CFG1 0x00000038
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL 0x0000003c
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_DPHY_SOT 0x00000040
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0 0x000000a0
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1 0x000000a4
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2 0x000000a8
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3 0x000000ac
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4 0x000000b0
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1 0x00000110
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_CTRL_4 0x00000114
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_PHY_STATUS 0x00000140
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0 0x00000148
|
||||
|
||||
#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1 0x0000014c
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER 0x00000020
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES 0x00000028
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CMODE 0x00000030
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PSM_CTRL 0x00000034
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_RSM_CTRL 0x00000038
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL 0x00000040
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN 0x00000054
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX 0x00000058
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PFILT 0x00000090
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_IFILT 0x00000094
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_GAIN 0x00000098
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ICODE_LOW 0x0000009c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH 0x000000a0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_LOCKDET 0x000000a4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_OUTDIV 0x000000a8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE 0x000000c0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL 0x00000100
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL 0x00000150
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW 0x000001c4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG 0x000001d4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FLL_CODE0 0x000001dc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FLL_CODE1 0x000001e0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0 0x000001e4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1 0x000001e8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SW_RESET 0x000001ec
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP 0x000001f0
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_LOCKTIME0 0x000001f4
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_LOCKTIME1 0x000001f8
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0 0x00000200
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1 0x00000204
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2 0x00000208
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3 0x0000020c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG 0x00000214
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS 0x00000220
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET 0x00000224
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1 0x00000240
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2 0x00000244
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CMODE_1 0x00000250
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_CMODE_2 0x00000254
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
|
||||
|
||||
#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
|
||||
|
||||
|
||||
#endif /* DSI_PHY_5NM_XML */
|
||||
|
|
@ -0,0 +1,482 @@
|
|||
#ifndef DSI_PHY_7NM_XML
|
||||
#define DSI_PHY_7NM_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
|
||||
|
||||
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
|
||||
|
||||
static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
|
||||
|
||||
#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
|
||||
|
||||
|
||||
#endif /* DSI_PHY_7NM_XML */
|
||||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include "dsi_phy.h"
|
||||
#include "dsi.xml.h"
|
||||
#include "dsi_phy_10nm.xml.h"
|
||||
|
||||
/*
|
||||
* DSI PLL 10nm - clock diagram (eg: DSI0):
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include "dsi_phy.h"
|
||||
#include "dsi.xml.h"
|
||||
#include "dsi_phy_14nm.xml.h"
|
||||
|
||||
#define PHY_14NM_CKLN_IDX 4
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
|
||||
#include "dsi_phy.h"
|
||||
#include "dsi.xml.h"
|
||||
#include "dsi_phy_20nm.xml.h"
|
||||
|
||||
static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
|
||||
struct msm_dsi_dphy_timing *timing)
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include "dsi_phy.h"
|
||||
#include "dsi.xml.h"
|
||||
#include "dsi_phy_28nm.xml.h"
|
||||
|
||||
/*
|
||||
* DSI PLL 28nm - clock diagram (eg: DSI0):
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include "dsi_phy.h"
|
||||
#include "dsi.xml.h"
|
||||
#include "dsi_phy_28nm_8960.xml.h"
|
||||
|
||||
/*
|
||||
* DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include "dsi_phy.h"
|
||||
#include "dsi.xml.h"
|
||||
#include "dsi_phy_7nm.xml.h"
|
||||
|
||||
/*
|
||||
* DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -517,7 +517,7 @@ static inline int align_pitch(int width, int bpp)
|
|||
/* for the generated headers: */
|
||||
#define INVALID_IDX(idx) ({BUG(); 0;})
|
||||
#define fui(x) ({BUG(); 0;})
|
||||
#define util_float_to_half(x) ({BUG(); 0;})
|
||||
#define _mesa_float_to_half(x) ({BUG(); 0;})
|
||||
|
||||
|
||||
#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче