ARM: 7083/1: rewrite U300 GPIO to use gpiolib
This rewrites the U300 GPIO so as to use gpiolib and struct gpio_chip instead of just generic GPIO, hiding all the platform specifics and passing in GPIO chip variant as platform data at runtime instead of the compiletime kludges. As a result <mach/gpio.h> is now empty for U300 and using just defaults. Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Debian kernel maintainers <debian-kernel@lists.debian.org> Cc: Arnaud Patard <arnaud.patard@rtp-net.org> Reported-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Linus Walleij
Russell King
Родитель
526a0dc771
Коммит
cc890cd78a
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@ -836,6 +836,7 @@ config ARCH_U300
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select CLKDEV_LOOKUP
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select HAVE_MACH_CLKDEV
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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help
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Support for ST-Ericsson U300 series mobile platforms.
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@ -6,6 +6,7 @@ comment "ST-Ericsson Mobile Platform Products"
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config MACH_U300
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bool "U300"
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select GPIO_U300
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comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
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@ -37,6 +37,7 @@
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#include <mach/hardware.h>
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#include <mach/syscon.h>
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#include <mach/dma_channels.h>
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#include <mach/gpio-u300.h>
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#include "clock.h"
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#include "mmc.h"
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@ -239,7 +240,7 @@ static struct resource gpio_resources[] = {
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.end = IRQ_U300_GPIO_PORT2,
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.flags = IORESOURCE_IRQ,
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},
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#ifdef U300_COH901571_3
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#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
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{
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.name = "gpio3",
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.start = IRQ_U300_GPIO_PORT3,
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@ -252,6 +253,7 @@ static struct resource gpio_resources[] = {
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.end = IRQ_U300_GPIO_PORT4,
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.flags = IORESOURCE_IRQ,
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},
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#endif
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#ifdef CONFIG_MACH_U300_BS335
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{
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.name = "gpio5",
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@ -266,7 +268,6 @@ static struct resource gpio_resources[] = {
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.flags = IORESOURCE_IRQ,
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},
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#endif /* CONFIG_MACH_U300_BS335 */
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#endif /* U300_COH901571_3 */
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};
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static struct resource keypad_resources[] = {
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@ -1556,11 +1557,35 @@ static struct platform_device i2c1_device = {
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.resource = i2c1_resources,
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};
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/*
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* The different variants have a few different versions of the
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* GPIO block, with different number of ports.
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*/
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static struct u300_gpio_platform u300_gpio_plat = {
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#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
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.variant = U300_GPIO_COH901335,
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.ports = 3,
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#endif
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#ifdef CONFIG_MACH_U300_BS335
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.variant = U300_GPIO_COH901571_3_BS335,
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.ports = 7,
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#endif
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#ifdef CONFIG_MACH_U300_BS365
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.variant = U300_GPIO_COH901571_3_BS365,
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.ports = 5,
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#endif
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.gpio_base = 0,
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.gpio_irq_base = IRQ_U300_GPIO_BASE,
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};
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static struct platform_device gpio_device = {
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.name = "u300-gpio",
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.id = -1,
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resource = gpio_resources,
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.dev = {
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.platform_data = &u300_gpio_plat,
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},
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};
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static struct platform_device keypad_device = {
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@ -1666,7 +1691,7 @@ void __init u300_init_irq(void)
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BUG_ON(IS_ERR(clk));
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clk_enable(clk);
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for (i = 0; i < NR_IRQS; i++)
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for (i = 0; i < U300_VIC_IRQS_END; i++)
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set_bit(i, (unsigned long *) &mask[0]);
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vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
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vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
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@ -9,132 +9,6 @@
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#ifndef __MACH_U300_GPIO_U300_H
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#define __MACH_U300_GPIO_U300_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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/* Switch type depending on platform/chip variant */
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#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
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#define U300_COH901335
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#endif
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#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
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#define U300_COH901571_3
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#endif
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/* Get base address for regs here */
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#include "u300-regs.h"
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/* IRQ numbers */
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#include "irqs.h"
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/*
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* This is the GPIO block definitions. GPIO (General Purpose I/O) can be
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* used for anything, and often is. The event/enable etc figures are for
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* the lowermost pin (pin 0 on each port), shift this left to match your
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* pin if you're gonna use these values.
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*/
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#ifdef U300_COH901335
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#define U300_GPIO_PORTX_SPACING (0x1C)
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/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
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#define U300_GPIO_PXPDIR (0x00)
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#define U300_GPIO_PXPDOR (0x00)
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/* Port X Pin Config Register 32bit (R/W) */
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#define U300_GPIO_PXPCR (0x04)
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#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
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#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
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#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
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/* Port X Interrupt Event Register 32bit (R/W) */
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#define U300_GPIO_PXIEV (0x08)
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#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
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/* Port X Interrupt Enable Register 32bit (R/W) */
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#define U300_GPIO_PXIEN (0x0C)
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#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
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/* Port X Interrupt Force Register 32bit (R/W) */
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#define U300_GPIO_PXIFR (0x10)
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#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
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/* Port X Interrupt Config Register 32bit (R/W) */
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#define U300_GPIO_PXICR (0x14)
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#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
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/* Port X Pull-up Enable Register 32bit (R/W) */
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#define U300_GPIO_PXPER (0x18)
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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/* Control Register 32bit (R/W) */
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#define U300_GPIO_CR (0x54)
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#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
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/* three ports of 8 bits each = GPIO pins 0..23 */
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#define U300_GPIO_NUM_PORTS 3
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#define U300_GPIO_PINS_PER_PORT 8
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#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
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#endif
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#ifdef U300_COH901571_3
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/*
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* Control Register 32bit (R/W)
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* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
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* gives the number of GPIO pins.
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* bit 8-2 (mask 0x000001FC) contains the core version ID.
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*/
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#define U300_GPIO_CR (0x00)
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#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
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#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
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#define U300_GPIO_PORTX_SPACING (0x30)
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/* Port X Pin Data INPUT Register 32bit (R/W) */
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#define U300_GPIO_PXPDIR (0x04)
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/* Port X Pin Data OUTPUT Register 32bit (R/W) */
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#define U300_GPIO_PXPDOR (0x08)
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/* Port X Pin Config Register 32bit (R/W) */
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#define U300_GPIO_PXPCR (0x0C)
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#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
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#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
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#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
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/* Port X Pull-up Enable Register 32bit (R/W) */
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#define U300_GPIO_PXPER (0x10)
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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/* Port X Interrupt Event Register 32bit (R/W) */
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#define U300_GPIO_PXIEV (0x14)
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#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
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/* Port X Interrupt Enable Register 32bit (R/W) */
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#define U300_GPIO_PXIEN (0x18)
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#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
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/* Port X Interrupt Force Register 32bit (R/W) */
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#define U300_GPIO_PXIFR (0x1C)
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#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
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#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
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/* Port X Interrupt Config Register 32bit (R/W) */
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#define U300_GPIO_PXICR (0x20)
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#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
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#ifdef CONFIG_MACH_U300_BS335
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/* seven ports of 8 bits each = GPIO pins 0..55 */
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#define U300_GPIO_NUM_PORTS 7
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#else
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/* five ports of 8 bits each = GPIO pins 0..39 */
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#define U300_GPIO_NUM_PORTS 5
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#endif
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#define U300_GPIO_PINS_PER_PORT 8
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#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
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#endif
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/*
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* Individual pin assignments for the B26/S26. Notice that the
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* actual usage of these pins depends on the PAD MUX settings, that
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@ -250,4 +124,27 @@
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#endif
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/**
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* enum u300_gpio_variant - the type of U300 GPIO employed
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*/
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enum u300_gpio_variant {
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U300_GPIO_COH901335,
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U300_GPIO_COH901571_3_BS335,
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U300_GPIO_COH901571_3_BS365,
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};
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/**
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* struct u300_gpio_platform - U300 GPIO platform data
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* @variant: IP block variant
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* @ports: number of GPIO block ports
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* @gpio_base: first GPIO number for this block (use a free range)
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* @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
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*/
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struct u300_gpio_platform {
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enum u300_gpio_variant variant;
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u8 ports;
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int gpio_base;
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int gpio_irq_base;
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};
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#endif /* __MACH_U300_GPIO_U300_H */
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@ -1,47 +0,0 @@
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/*
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*
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* arch/arm/mach-u300/include/mach/gpio.h
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*
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*
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* Copyright (C) 2007-2009 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* GPIO block resgister definitions and inline macros for
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* U300 GPIO COH 901 335 or COH 901 571/3
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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*/
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#ifndef __MACH_U300_GPIO_H
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#define __MACH_U300_GPIO_H
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#define __ARM_GPIOLIB_COMPLEX
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/* These can be found in arch/arm/mach-u300/gpio.c */
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extern int gpio_is_valid(int number);
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extern int gpio_request(unsigned gpio, const char *label);
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extern void gpio_free(unsigned gpio);
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extern int gpio_direction_input(unsigned gpio);
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extern int gpio_direction_output(unsigned gpio, int value);
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extern int gpio_register_callback(unsigned gpio,
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int (*func)(void *arg),
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void *);
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extern int gpio_unregister_callback(unsigned gpio);
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extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
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extern void disable_irq_on_gpio_pin(unsigned gpio);
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extern void gpio_pullup(unsigned gpio, int value);
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extern int gpio_get_value(unsigned gpio);
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extern void gpio_set_value(unsigned gpio, int value);
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#define gpio_get_value_cansleep gpio_get_value
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#define gpio_set_value_cansleep gpio_set_value
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/* translates a pin number to a port number */
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#define PIN_TO_PORT(val) (val >> 3)
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/* wrappers to sleep-enable the previous two functions */
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static inline unsigned gpio_to_irq(unsigned gpio)
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{
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return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
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}
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#define gpio_to_irq gpio_to_irq
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#endif /* __MACH_U300_GPIO_H */
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@ -72,7 +72,7 @@
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/* DB3150 and DB3200 have only 45 IRQs */
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#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
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#define U300_NR_IRQS 45
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#define U300_VIC_IRQS_END 45
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#endif
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/* The DB3350-specific interrupt lines */
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@ -88,7 +88,7 @@
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#define IRQ_U300_GPIO_PORT4 53
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#define IRQ_U300_GPIO_PORT5 54
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#define IRQ_U300_GPIO_PORT6 55
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#define U300_NR_IRQS 56
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#define U300_VIC_IRQS_END 56
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#endif
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/* The DB3210-specific interrupt lines */
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@ -106,16 +106,25 @@
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#define IRQ_U300_NFIF 45
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#define IRQ_U300_NFIF2 46
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#define IRQ_U300_SYSCON_PLL_LOCK 47
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#define U300_NR_IRQS 48
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#define U300_VIC_IRQS_END 48
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#endif
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#ifdef CONFIG_AB3550_CORE
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#define IRQ_AB3550_BASE (U300_NR_IRQS)
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#define IRQ_AB3550_END (IRQ_AB3550_BASE + 37)
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#define NR_IRQS (IRQ_AB3550_END + 1)
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/* Maximum 8*7 GPIO lines */
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#ifdef CONFIG_GPIO_U300
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#define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END)
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#define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56)
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#else
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#define NR_IRQS U300_NR_IRQS
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#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
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#endif
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/* Optional AB3550 mixsig chip */
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#ifdef CONFIG_AB3550_CORE
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#define IRQ_AB3550_BASE (IRQ_U300_GPIO_END)
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#define IRQ_AB3550_END (IRQ_AB3550_BASE + 38)
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#else
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#define IRQ_AB3550_END (IRQ_U300_GPIO_END)
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#endif
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#define NR_IRQS (IRQ_AB3550_END)
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#endif
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@ -178,6 +178,15 @@ config GPIO_SCH
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The Intel Tunnel Creek processor has 5 GPIOs powered by the
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core power rail and 9 from suspend power supply.
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config GPIO_U300
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bool "ST-Ericsson U300 COH 901 335/571 GPIO"
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depends on GPIOLIB && ARCH_U300
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help
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Say yes here to support GPIO interface on ST-Ericsson U300.
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The names of the two IP block variants supported are
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COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
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ports of 8 GPIO pins each.
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config GPIO_VX855
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tristate "VIA VX855/VX875 GPIO"
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depends on MFD_SUPPORT && PCI
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