MIPS: Simplify FP context initialization
MIPS has up until now had 3 different ways for a task's floating point
context to be initialized:
- If the task's first use of FP involves it gaining ownership of an
FPU then _init_fpu() is used to initialize the FPU's registers such
that they all contain ~0, and the FPU registers will be stored to
struct thread_info later (eg. when context switching).
- If the task first uses FP on a CPU without an associated FPU then
fpu_emulator_init_fpu() initializes the task's floating point
register state in struct thread_info such that all floating point
register contain the bit pattern 0x7ff800007ff80000, different to
the _init_fpu() behaviour.
- If a task's floating point context is first accessed via ptrace then
init_fp_ctx() initializes the floating point register state in
struct thread_info to ~0, giving equivalent state to _init_fpu().
The _init_fpu() path has 2 separate implementations - one for r2k/r3k
style systems & one for r4k style systems. The _init_fpu() path also
requires that we be careful to clear & restore the value of the
Config5.FRE bit on modern systems in order to avoid inadvertently
triggering floating point exceptions.
None of this code is in a performance critical hot path - it runs only
the first time a task uses floating point. As such it doesn't seem to
warrant the complications of maintaining the _init_fpu() path.
Remove _init_fpu() & fpu_emulator_init_fpu(), instead using
init_fp_ctx() consistently to initialize floating point register state
in struct thread_info. Upon a task's first use of floating point this
will typically mean that we initialize state in memory & then load it
into FPU registers using _restore_fp() just as we would on a context
switch. For other paths such as __compute_return_epc_for_insn() or
mipsr2_decoder() this results in a significant simplification of the
work to be done.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21002/
Cc: linux-mips@linux-mips.org
This commit is contained in:
Paul Burton
Родитель
b1013f1e95
Коммит
cc97ab235f
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@ -33,7 +33,6 @@
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struct sigcontext;
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struct sigcontext32;
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extern void _init_fpu(unsigned int);
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extern void _save_fp(struct task_struct *);
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extern void _restore_fp(struct task_struct *);
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@ -198,42 +197,36 @@ static inline void lose_fpu(int save)
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preempt_enable();
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}
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static inline int init_fpu(void)
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/**
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* init_fp_ctx() - Initialize task FP context
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* @target: The task whose FP context should be initialized.
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*
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* Initializes the FP context of the target task to sane default values if that
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* target task does not already have valid FP context. Once the context has
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* been initialized, the task will be marked as having used FP & thus having
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* valid FP context.
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*
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* Returns: true if context is initialized, else false.
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*/
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static inline bool init_fp_ctx(struct task_struct *target)
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{
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unsigned int fcr31 = current->thread.fpu.fcr31;
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int ret = 0;
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/* If FP has been used then the target already has context */
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if (tsk_used_math(target))
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return false;
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if (cpu_has_fpu) {
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unsigned int config5;
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/* Begin with data registers set to all 1s... */
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memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
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ret = __own_fpu();
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if (ret)
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return ret;
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/* FCSR has been preset by `mips_set_personality_nan'. */
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if (!cpu_has_fre) {
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_init_fpu(fcr31);
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/*
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* Record that the target has "used" math, such that the context
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* just initialised, and any modifications made by the caller,
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* aren't discarded.
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*/
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set_stopped_child_used_math(target);
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return 0;
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}
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/*
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* Ensure FRE is clear whilst running _init_fpu, since
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* single precision FP instructions are used. If FRE
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* was set then we'll just end up initialising all 32
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* 64b registers.
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*/
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config5 = clear_c0_config5(MIPS_CONF5_FRE);
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enable_fpu_hazard();
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_init_fpu(fcr31);
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/* Restore FRE */
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write_c0_config5(config5);
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enable_fpu_hazard();
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} else
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fpu_emulator_init_fpu();
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return ret;
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return true;
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}
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static inline void save_fp(struct task_struct *tsk)
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@ -188,17 +188,6 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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unsigned long *contpc);
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#define SIGNALLING_NAN 0x7ff800007ff80000LL
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static inline void fpu_emulator_init_fpu(void)
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{
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struct task_struct *t = current;
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int i;
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for (i = 0; i < 32; i++)
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set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
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}
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/*
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* Mask the FCSR Cause bits according to the Enable bits, observing
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* that Unimplemented is always enabled.
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@ -674,16 +674,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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if (cpu_has_mips_r6 &&
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((insn.i_format.rs == bc1eqz_op) ||
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(insn.i_format.rs == bc1nez_op))) {
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if (!used_math()) { /* First time FPU user */
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ret = init_fpu();
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if (ret && NO_R6EMU) {
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ret = -ret;
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break;
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}
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ret = 0;
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set_used_math();
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}
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lose_fpu(1); /* Save FPU state for the emulator. */
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if (!init_fp_ctx(current))
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lose_fpu(1);
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reg = insn.i_format.rt;
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bit = get_fpr32(¤t->thread.fpu.fpr[reg], 0) & 0x1;
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if (insn.i_format.rs == bc1eqz_op)
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@ -1174,13 +1174,9 @@ repeat:
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fpu_emul:
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regs->regs[31] = r31;
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regs->cp0_epc = epc;
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if (!used_math()) { /* First time FPU user. */
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preempt_disable();
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err = init_fpu();
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preempt_enable();
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set_used_math();
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}
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lose_fpu(1); /* Save FPU state for the emulator. */
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if (!init_fp_ctx(current))
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lose_fpu(1);
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err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
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&fault_addr);
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@ -50,25 +50,6 @@
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#define CREATE_TRACE_POINTS
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#include <trace/events/syscalls.h>
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static void init_fp_ctx(struct task_struct *target)
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{
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/* If FP has been used then the target already has context */
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if (tsk_used_math(target))
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return;
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/* Begin with data registers set to all 1s... */
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memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
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/* FCSR has been preset by `mips_set_personality_nan'. */
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/*
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* Record that the target has "used" math, such that the context
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* just initialised, and any modifications made by the caller,
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* aren't discarded.
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*/
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set_stopped_child_used_math(target);
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}
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/*
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* Called by kernel/ptrace.c when detaching..
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*
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@ -52,64 +52,6 @@ LEAF(_restore_fp)
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jr ra
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END(_restore_fp)
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using has
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* the property that no matter whether considered as single or as double
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* precision represents signaling NANS.
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*
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* The value to initialize fcr31 to comes in $a0.
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*/
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.set push
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SET_HARDFLOAT
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LEAF(_init_fpu)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_STATUS
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ctc1 a0, fcr31
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li t0, -1
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mtc1 t0, $f0
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mtc1 t0, $f1
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mtc1 t0, $f2
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mtc1 t0, $f3
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mtc1 t0, $f4
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mtc1 t0, $f5
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mtc1 t0, $f6
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mtc1 t0, $f7
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mtc1 t0, $f8
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mtc1 t0, $f9
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mtc1 t0, $f10
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mtc1 t0, $f11
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mtc1 t0, $f12
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mtc1 t0, $f13
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mtc1 t0, $f14
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mtc1 t0, $f15
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mtc1 t0, $f16
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mtc1 t0, $f17
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mtc1 t0, $f18
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mtc1 t0, $f19
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mtc1 t0, $f20
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mtc1 t0, $f21
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mtc1 t0, $f22
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mtc1 t0, $f23
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mtc1 t0, $f24
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mtc1 t0, $f25
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mtc1 t0, $f26
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mtc1 t0, $f27
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mtc1 t0, $f28
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mtc1 t0, $f29
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mtc1 t0, $f30
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mtc1 t0, $f31
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jr ra
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END(_init_fpu)
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.set pop
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.set noreorder
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/**
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@ -86,150 +86,6 @@ LEAF(_init_msa_upper)
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#endif
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using has
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* the property that no matter whether considered as single or as double
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* precision represents signaling NANS.
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*
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* The value to initialize fcr31 to comes in $a0.
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*/
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.set push
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SET_HARDFLOAT
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LEAF(_init_fpu)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_STATUS
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enable_fpu_hazard
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ctc1 a0, fcr31
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li t1, -1 # SNaN
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#ifdef CONFIG_64BIT
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sll t0, t0, 5
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bgez t0, 1f # 16 / 32 register mode?
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dmtc1 t1, $f1
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dmtc1 t1, $f3
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dmtc1 t1, $f5
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dmtc1 t1, $f7
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dmtc1 t1, $f9
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dmtc1 t1, $f11
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dmtc1 t1, $f13
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dmtc1 t1, $f15
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dmtc1 t1, $f17
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dmtc1 t1, $f19
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dmtc1 t1, $f21
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dmtc1 t1, $f23
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dmtc1 t1, $f25
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dmtc1 t1, $f27
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dmtc1 t1, $f29
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dmtc1 t1, $f31
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1:
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#endif
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#ifdef CONFIG_CPU_MIPS32
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mtc1 t1, $f0
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mtc1 t1, $f1
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mtc1 t1, $f2
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mtc1 t1, $f3
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mtc1 t1, $f4
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mtc1 t1, $f5
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mtc1 t1, $f6
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mtc1 t1, $f7
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mtc1 t1, $f8
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mtc1 t1, $f9
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mtc1 t1, $f10
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mtc1 t1, $f11
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mtc1 t1, $f12
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mtc1 t1, $f13
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mtc1 t1, $f14
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mtc1 t1, $f15
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mtc1 t1, $f16
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mtc1 t1, $f17
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mtc1 t1, $f18
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mtc1 t1, $f19
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mtc1 t1, $f20
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mtc1 t1, $f21
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mtc1 t1, $f22
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mtc1 t1, $f23
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mtc1 t1, $f24
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mtc1 t1, $f25
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mtc1 t1, $f26
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mtc1 t1, $f27
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mtc1 t1, $f28
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mtc1 t1, $f29
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mtc1 t1, $f30
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mtc1 t1, $f31
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#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set fp=64
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sll t0, t0, 5 # is Status.FR set?
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bgez t0, 1f # no: skip setting upper 32b
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mthc1 t1, $f0
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mthc1 t1, $f1
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mthc1 t1, $f2
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mthc1 t1, $f3
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mthc1 t1, $f4
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mthc1 t1, $f5
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mthc1 t1, $f6
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mthc1 t1, $f7
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mthc1 t1, $f8
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mthc1 t1, $f9
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mthc1 t1, $f10
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mthc1 t1, $f11
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mthc1 t1, $f12
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mthc1 t1, $f13
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mthc1 t1, $f14
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mthc1 t1, $f15
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mthc1 t1, $f16
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mthc1 t1, $f17
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mthc1 t1, $f18
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mthc1 t1, $f19
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mthc1 t1, $f20
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mthc1 t1, $f21
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mthc1 t1, $f22
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mthc1 t1, $f23
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mthc1 t1, $f24
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mthc1 t1, $f25
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mthc1 t1, $f26
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mthc1 t1, $f27
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mthc1 t1, $f28
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mthc1 t1, $f29
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mthc1 t1, $f30
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mthc1 t1, $f31
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1: .set pop
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#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
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#else
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.set MIPS_ISA_ARCH_LEVEL_RAW
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dmtc1 t1, $f0
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dmtc1 t1, $f2
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dmtc1 t1, $f4
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dmtc1 t1, $f6
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dmtc1 t1, $f8
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dmtc1 t1, $f10
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dmtc1 t1, $f12
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dmtc1 t1, $f14
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dmtc1 t1, $f16
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dmtc1 t1, $f18
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dmtc1 t1, $f20
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dmtc1 t1, $f22
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dmtc1 t1, $f24
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dmtc1 t1, $f26
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dmtc1 t1, $f28
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dmtc1 t1, $f30
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#endif
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jr ra
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END(_init_fpu)
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.set pop /* SET_HARDFLOAT */
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.set noreorder
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/**
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@ -1218,20 +1218,20 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
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static int enable_restore_fp_context(int msa)
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{
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int err, was_fpu_owner, prior_msa;
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bool first_fp;
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if (!used_math()) {
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/* First time FP context user. */
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/* Initialize context if it hasn't been used already */
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first_fp = init_fp_ctx(current);
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if (first_fp) {
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preempt_disable();
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err = init_fpu();
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err = own_fpu_inatomic(1);
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if (msa && !err) {
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enable_msa();
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init_msa_upper();
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set_thread_flag(TIF_USEDMSA);
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set_thread_flag(TIF_MSA_CTX_LIVE);
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}
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preempt_enable();
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if (!err)
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set_used_math();
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return err;
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}
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@ -43,11 +43,8 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
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/* If FPU is owned, we needn't init or restore fp */
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if (!fpu_owned) {
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set_thread_flag(TIF_USEDFPU);
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if (!used_math()) {
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_init_fpu(current->thread.fpu.fcr31);
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set_used_math();
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} else
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_restore_fp(current);
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init_fp_ctx(current);
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_restore_fp(current);
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}
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preempt_enable();
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