dmaengine: rcar-dmac: Implement support for hardware descriptor lists
The DMAC supports hardware-based auto-configuration from descriptor lists. This reduces the number of interrupts required for processing a DMA transfer. Support that mode in the driver. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
This commit is contained in:
Laurent Pinchart
Родитель
87244fe5ab
Коммит
ccadee9b1e
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@ -10,6 +10,7 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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@ -40,6 +41,19 @@ struct rcar_dmac_xfer_chunk {
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u32 size;
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};
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/*
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* struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
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* @sar: value of the SAR register (source address)
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* @dar: value of the DAR register (destination address)
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* @tcr: value of the TCR register (transfer count)
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*/
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struct rcar_dmac_hw_desc {
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u32 sar;
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u32 dar;
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u32 tcr;
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u32 reserved;
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} __attribute__((__packed__));
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/*
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* struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
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* @async_tx: base DMA asynchronous transaction descriptor
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@ -49,6 +63,10 @@ struct rcar_dmac_xfer_chunk {
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* @node: entry in the channel's descriptors lists
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* @chunks: list of transfer chunks for this transfer
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* @running: the transfer chunk being currently processed
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* @nchunks: number of transfer chunks for this transfer
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* @hwdescs.mem: hardware descriptors memory for the transfer
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* @hwdescs.dma: device address of the hardware descriptors memory
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* @hwdescs.size: size of the hardware descriptors in bytes
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* @size: transfer size in bytes
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* @cyclic: when set indicates that the DMA transfer is cyclic
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*/
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@ -61,6 +79,13 @@ struct rcar_dmac_desc {
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struct list_head node;
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struct list_head chunks;
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struct rcar_dmac_xfer_chunk *running;
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unsigned int nchunks;
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struct {
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struct rcar_dmac_hw_desc *mem;
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dma_addr_t dma;
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size_t size;
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} hwdescs;
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unsigned int size;
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bool cyclic;
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@ -217,7 +242,8 @@ struct rcar_dmac {
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#define RCAR_DMATSRB 0x0038
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#define RCAR_DMACHCRB 0x001c
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#define RCAR_DMACHCRB_DCNT(n) ((n) << 24)
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#define RCAR_DMACHCRB_DPTR(n) ((n) << 16)
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#define RCAR_DMACHCRB_DPTR_MASK (0xff << 16)
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#define RCAR_DMACHCRB_DPTR_SHIFT 16
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#define RCAR_DMACHCRB_DRST (1 << 15)
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#define RCAR_DMACHCRB_DTS (1 << 8)
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#define RCAR_DMACHCRB_SLM_NORMAL (0 << 4)
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@ -289,30 +315,81 @@ static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan)
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static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
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{
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struct rcar_dmac_desc *desc = chan->desc.running;
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struct rcar_dmac_xfer_chunk *chunk = desc->running;
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dev_dbg(chan->chan.device->dev,
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"chan%u: queue chunk %p: %u@%pad -> %pad\n",
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chan->index, chunk, chunk->size, &chunk->src_addr,
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&chunk->dst_addr);
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u32 chcr = desc->chcr;
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WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR, chunk->src_addr >> 32);
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rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR, chunk->dst_addr >> 32);
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#endif
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rcar_dmac_chan_write(chan, RCAR_DMASAR, chunk->src_addr & 0xffffffff);
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rcar_dmac_chan_write(chan, RCAR_DMADAR, chunk->dst_addr & 0xffffffff);
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if (chan->mid_rid >= 0)
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rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
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rcar_dmac_chan_write(chan, RCAR_DMATCR,
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chunk->size >> desc->xfer_shift);
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if (desc->hwdescs.mem) {
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dev_dbg(chan->chan.device->dev,
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"chan%u: queue desc %p: %u@%pad\n",
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chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
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rcar_dmac_chan_write(chan, RCAR_DMACHCR, desc->chcr | RCAR_DMACHCR_DE |
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RCAR_DMACHCR_IE);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
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desc->hwdescs.dma >> 32);
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#endif
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rcar_dmac_chan_write(chan, RCAR_DMADPBASE,
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(desc->hwdescs.dma & 0xfffffff0) |
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RCAR_DMADPBASE_SEL);
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rcar_dmac_chan_write(chan, RCAR_DMACHCRB,
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RCAR_DMACHCRB_DCNT(desc->nchunks - 1) |
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RCAR_DMACHCRB_DRST);
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/*
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* Program the descriptor stage interrupt to occur after the end
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* of the first stage.
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*/
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rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1));
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chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
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| RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB;
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/*
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* If the descriptor isn't cyclic enable normal descriptor mode
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* and the transfer completion interrupt.
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*/
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if (!desc->cyclic)
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chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
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/*
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* If the descriptor is cyclic and has a callback enable the
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* descriptor stage interrupt in infinite repeat mode.
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*/
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else if (desc->async_tx.callback)
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chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
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/*
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* Otherwise just select infinite repeat mode without any
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* interrupt.
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*/
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else
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chcr |= RCAR_DMACHCR_DPM_INFINITE;
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} else {
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struct rcar_dmac_xfer_chunk *chunk = desc->running;
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dev_dbg(chan->chan.device->dev,
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"chan%u: queue chunk %p: %u@%pad -> %pad\n",
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chan->index, chunk, chunk->size, &chunk->src_addr,
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&chunk->dst_addr);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
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chunk->src_addr >> 32);
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rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
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chunk->dst_addr >> 32);
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#endif
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rcar_dmac_chan_write(chan, RCAR_DMASAR,
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chunk->src_addr & 0xffffffff);
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rcar_dmac_chan_write(chan, RCAR_DMADAR,
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chunk->dst_addr & 0xffffffff);
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rcar_dmac_chan_write(chan, RCAR_DMATCR,
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chunk->size >> desc->xfer_shift);
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chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
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}
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rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE);
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}
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static int rcar_dmac_init(struct rcar_dmac *dmac)
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@ -403,31 +480,58 @@ static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
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* @desc: the descriptor
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*
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* Put the descriptor and its transfer chunk descriptors back in the channel's
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* free descriptors lists. The descriptor's chunk will be reinitialized to an
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* empty list as a result.
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* free descriptors lists, and free the hardware descriptors list memory. The
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* descriptor's chunks list will be reinitialized to an empty list as a result.
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*
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* The descriptor must have been removed from the channel's done list before
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* calling this function.
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* The descriptor must have been removed from the channel's lists before calling
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* this function.
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*
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* Locking: Must be called with the channel lock held.
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* Locking: Must be called in non-atomic context.
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*/
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static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan,
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struct rcar_dmac_desc *desc)
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{
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if (desc->hwdescs.mem) {
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dma_free_coherent(NULL, desc->hwdescs.size, desc->hwdescs.mem,
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desc->hwdescs.dma);
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desc->hwdescs.mem = NULL;
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}
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spin_lock_irq(&chan->lock);
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list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free);
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list_add_tail(&desc->node, &chan->desc.free);
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spin_unlock_irq(&chan->lock);
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}
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static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan)
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{
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struct rcar_dmac_desc *desc, *_desc;
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LIST_HEAD(list);
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list_for_each_entry_safe(desc, _desc, &chan->desc.wait, node) {
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/*
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* We have to temporarily move all descriptors from the wait list to a
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* local list as iterating over the wait list, even with
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* list_for_each_entry_safe, isn't safe if we release the channel lock
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* around the rcar_dmac_desc_put() call.
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*/
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spin_lock_irq(&chan->lock);
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list_splice_init(&chan->desc.wait, &list);
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spin_unlock_irq(&chan->lock);
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list_for_each_entry_safe(desc, _desc, &list, node) {
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if (async_tx_test_ack(&desc->async_tx)) {
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list_del(&desc->node);
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rcar_dmac_desc_put(chan, desc);
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}
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}
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if (list_empty(&list))
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return;
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/* Put the remaining descriptors back in the wait list. */
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spin_lock_irq(&chan->lock);
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list_splice(&list, &chan->desc.wait);
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spin_unlock_irq(&chan->lock);
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}
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/*
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@ -444,11 +548,11 @@ static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan)
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struct rcar_dmac_desc *desc;
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int ret;
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spin_lock_irq(&chan->lock);
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/* Recycle acked descriptors before attempting allocation. */
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rcar_dmac_desc_recycle_acked(chan);
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spin_lock_irq(&chan->lock);
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do {
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if (list_empty(&chan->desc.free)) {
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/*
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@ -547,6 +651,28 @@ rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan)
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return chunk;
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}
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static void rcar_dmac_alloc_hwdesc(struct rcar_dmac_chan *chan,
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struct rcar_dmac_desc *desc)
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{
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struct rcar_dmac_xfer_chunk *chunk;
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struct rcar_dmac_hw_desc *hwdesc;
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size_t size = desc->nchunks * sizeof(*hwdesc);
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hwdesc = dma_alloc_coherent(NULL, size, &desc->hwdescs.dma, GFP_NOWAIT);
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if (!hwdesc)
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return;
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desc->hwdescs.mem = hwdesc;
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desc->hwdescs.size = size;
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list_for_each_entry(chunk, &desc->chunks, node) {
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hwdesc->sar = chunk->src_addr;
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hwdesc->dar = chunk->dst_addr;
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hwdesc->tcr = chunk->size >> desc->xfer_shift;
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hwdesc++;
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}
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}
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/* -----------------------------------------------------------------------------
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* Stop and reset
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*/
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@ -555,7 +681,8 @@ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
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{
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u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
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chcr &= ~(RCAR_DMACHCR_IE | RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
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chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
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RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
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rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
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}
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@ -666,8 +793,10 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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struct rcar_dmac_xfer_chunk *chunk;
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struct rcar_dmac_desc *desc;
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struct scatterlist *sg;
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unsigned int nchunks = 0;
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unsigned int max_chunk_size;
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unsigned int full_size = 0;
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bool highmem = false;
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unsigned int i;
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desc = rcar_dmac_desc_get(chan);
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@ -706,6 +835,14 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
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if (mem_addr >> 32 != (mem_addr + size - 1) >> 32)
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size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
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/*
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* Check if either of the source or destination address
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* can't be expressed in 32 bits. If so we can't use
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* hardware descriptor lists.
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*/
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if (dev_addr >> 32 || mem_addr >> 32)
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highmem = true;
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#endif
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chunk = rcar_dmac_xfer_chunk_get(chan);
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@ -736,11 +873,26 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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len -= size;
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list_add_tail(&chunk->node, &desc->chunks);
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nchunks++;
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}
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}
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desc->nchunks = nchunks;
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desc->size = full_size;
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/*
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* Use hardware descriptor lists if possible when more than one chunk
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* needs to be transferred (otherwise they don't make much sense).
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*
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* The highmem check currently covers the whole transfer. As an
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* optimization we could use descriptor lists for consecutive lowmem
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* chunks and direct manual mode for highmem chunks. Whether the
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* performance improvement would be significant enough compared to the
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* additional complexity remains to be investigated.
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*/
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if (!highmem && nchunks > 1)
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rcar_dmac_alloc_hwdesc(chan, desc);
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return &desc->async_tx;
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}
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@ -940,8 +1092,10 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
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dma_cookie_t cookie)
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{
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struct rcar_dmac_desc *desc = chan->desc.running;
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struct rcar_dmac_xfer_chunk *running = NULL;
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struct rcar_dmac_xfer_chunk *chunk;
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unsigned int residue = 0;
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unsigned int dptr = 0;
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if (!desc)
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return 0;
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@ -954,9 +1108,23 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
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if (cookie != desc->async_tx.cookie)
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return desc->size;
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/*
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* In descriptor mode the descriptor running pointer is not maintained
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* by the interrupt handler, find the running descriptor from the
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* descriptor pointer field in the CHCRB register. In non-descriptor
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* mode just use the running descriptor pointer.
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*/
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if (desc->hwdescs.mem) {
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dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
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RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
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WARN_ON(dptr >= desc->nchunks);
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} else {
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running = desc->running;
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}
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/* Compute the size of all chunks still to be transferred. */
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list_for_each_entry_reverse(chunk, &desc->chunks, node) {
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if (chunk == desc->running)
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if (chunk == running || ++dptr == desc->nchunks)
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break;
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residue += chunk->size;
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@ -1025,42 +1193,71 @@ done:
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* IRQ handling
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*/
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static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan)
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{
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struct rcar_dmac_desc *desc = chan->desc.running;
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unsigned int stage;
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if (WARN_ON(!desc || !desc->cyclic)) {
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/*
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* This should never happen, there should always be a running
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* cyclic descriptor when a descriptor stage end interrupt is
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* triggered. Warn and return.
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*/
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return IRQ_NONE;
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}
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/* Program the interrupt pointer to the next stage. */
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stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
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RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
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rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage));
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return IRQ_WAKE_THREAD;
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}
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static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan)
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{
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struct rcar_dmac_desc *desc = chan->desc.running;
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struct rcar_dmac_xfer_chunk *chunk;
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irqreturn_t ret = IRQ_WAKE_THREAD;
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if (WARN_ON_ONCE(!desc)) {
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/*
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* This should never happen, there should always be
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* a running descriptor when a transfer ends. Warn and
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* return.
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* This should never happen, there should always be a running
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* descriptor when a transfer end interrupt is triggered. Warn
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* and return.
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*/
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return IRQ_NONE;
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}
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/*
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* If we haven't completed the last transfer chunk simply move to the
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* next one. Only wake the IRQ thread if the transfer is cyclic.
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* The transfer end interrupt isn't generated for each chunk when using
|
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* descriptor mode. Only update the running chunk pointer in
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* non-descriptor mode.
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*/
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chunk = desc->running;
|
||||
if (!list_is_last(&chunk->node, &desc->chunks)) {
|
||||
desc->running = list_next_entry(chunk, node);
|
||||
if (!desc->cyclic)
|
||||
ret = IRQ_HANDLED;
|
||||
goto done;
|
||||
}
|
||||
if (!desc->hwdescs.mem) {
|
||||
/*
|
||||
* If we haven't completed the last transfer chunk simply move
|
||||
* to the next one. Only wake the IRQ thread if the transfer is
|
||||
* cyclic.
|
||||
*/
|
||||
if (!list_is_last(&desc->running->node, &desc->chunks)) {
|
||||
desc->running = list_next_entry(desc->running, node);
|
||||
if (!desc->cyclic)
|
||||
ret = IRQ_HANDLED;
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* We've completed the last transfer chunk. If the transfer is cyclic,
|
||||
* move back to the first one.
|
||||
*/
|
||||
if (desc->cyclic) {
|
||||
desc->running = list_first_entry(&desc->chunks,
|
||||
/*
|
||||
* We've completed the last transfer chunk. If the transfer is
|
||||
* cyclic, move back to the first one.
|
||||
*/
|
||||
if (desc->cyclic) {
|
||||
desc->running =
|
||||
list_first_entry(&desc->chunks,
|
||||
struct rcar_dmac_xfer_chunk,
|
||||
node);
|
||||
goto done;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
/* The descriptor is complete, move it to the done list. */
|
||||
|
|
@ -1083,6 +1280,7 @@ done:
|
|||
|
||||
static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
|
||||
{
|
||||
u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE;
|
||||
struct rcar_dmac_chan *chan = dev;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
u32 chcr;
|
||||
|
|
@ -1090,8 +1288,12 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
|
|||
spin_lock(&chan->lock);
|
||||
|
||||
chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
|
||||
rcar_dmac_chan_write(chan, RCAR_DMACHCR,
|
||||
chcr & ~(RCAR_DMACHCR_TE | RCAR_DMACHCR_DE));
|
||||
if (chcr & RCAR_DMACHCR_TE)
|
||||
mask |= RCAR_DMACHCR_DE;
|
||||
rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
|
||||
|
||||
if (chcr & RCAR_DMACHCR_DSE)
|
||||
ret |= rcar_dmac_isr_desc_stage_end(chan);
|
||||
|
||||
if (chcr & RCAR_DMACHCR_TE)
|
||||
ret |= rcar_dmac_isr_transfer_end(chan);
|
||||
|
|
@ -1148,11 +1350,11 @@ static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev)
|
|||
list_add_tail(&desc->node, &chan->desc.wait);
|
||||
}
|
||||
|
||||
spin_unlock_irq(&chan->lock);
|
||||
|
||||
/* Recycle all acked descriptors. */
|
||||
rcar_dmac_desc_recycle_acked(chan);
|
||||
|
||||
spin_unlock_irq(&chan->lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
|
|||
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