ALSA: hda - Migrate more hdac_stream codes
... including dsp loader helpers. Lots of codes removed. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai
Родитель
7833c3f85b
Коммит
ccc98865aa
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@ -36,58 +36,6 @@
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#define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
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#define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
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/*
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* AZX stream operations.
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*/
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/*
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* set up the SD for streaming
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*/
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static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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{
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unsigned int val;
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/* make sure the run bit is zero for SD */
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snd_hdac_stream_clear(azx_stream(azx_dev));
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/* program the stream_tag */
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val = azx_sd_readl(chip, azx_dev, SD_CTL);
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val = (val & ~SD_CTL_STREAM_TAG_MASK) |
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(azx_dev->core.stream_tag << SD_CTL_STREAM_TAG_SHIFT);
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if (!azx_snoop(chip))
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val |= SD_CTL_TRAFFIC_PRIO;
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azx_sd_writel(chip, azx_dev, SD_CTL, val);
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/* program the length of samples in cyclic buffer */
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azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->core.bufsize);
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/* program the stream format */
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/* this value needs to be the same as the one programmed */
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azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->core.format_val);
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/* program the stream LVI (last valid index) of the BDL */
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azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->core.frags - 1);
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/* program the BDL address */
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/* lower BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->core.bdl.addr);
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/* upper BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPU,
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upper_32_bits(azx_dev->core.bdl.addr));
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/* enable the position buffer */
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if (chip->get_position[0] != azx_get_pos_lpib ||
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chip->get_position[1] != azx_get_pos_lpib) {
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if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE))
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azx_writel(chip, DPLBASE,
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(u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE);
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}
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/* set the interrupt enable bits in the descriptor control register */
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azx_sd_writel(chip, azx_dev, SD_CTL,
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azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
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return 0;
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}
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/* assign a stream for the PCM */
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static inline struct azx_dev *
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azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
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@ -106,50 +54,6 @@ static inline void azx_release_device(struct azx_dev *azx_dev)
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snd_hdac_stream_release(azx_stream(azx_dev));
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}
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static cycle_t azx_cc_read(const struct cyclecounter *cc)
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{
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struct azx_dev *azx_dev = container_of(cc, struct azx_dev, core.cc);
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struct snd_pcm_substream *substream = azx_dev->core.substream;
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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struct azx *chip = apcm->chip;
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return azx_readl(chip, WALLCLK);
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}
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static void azx_timecounter_init(struct snd_pcm_substream *substream,
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bool force, cycle_t last)
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{
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struct azx_dev *azx_dev = get_azx_dev(substream);
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struct timecounter *tc = &azx_dev->core.tc;
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struct cyclecounter *cc = &azx_dev->core.cc;
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u64 nsec;
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cc->read = azx_cc_read;
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cc->mask = CLOCKSOURCE_MASK(32);
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/*
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* Converting from 24 MHz to ns means applying a 125/3 factor.
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* To avoid any saturation issues in intermediate operations,
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* the 125 factor is applied first. The division is applied
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* last after reading the timecounter value.
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* Applying the 1/3 factor as part of the multiplication
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* requires at least 20 bits for a decent precision, however
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* overflows occur after about 4 hours or less, not a option.
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*/
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cc->mult = 125; /* saturation after 195 years */
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cc->shift = 0;
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nsec = 0; /* audio time is elapsed time since trigger */
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timecounter_init(tc, cc, nsec);
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if (force)
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/*
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* force timecounter to use predefined value,
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* used for synchronized starts
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*/
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tc->cycle_last = last;
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}
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static inline struct hda_pcm_stream *
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to_hda_pcm_stream(struct snd_pcm_substream *substream)
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{
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@ -177,119 +81,6 @@ static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
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return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
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}
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/*
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* set up a BDL entry
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*/
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static int setup_bdle(struct azx *chip,
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struct snd_dma_buffer *dmab,
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struct azx_dev *azx_dev, u32 **bdlp,
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int ofs, int size, int with_ioc)
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{
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u32 *bdl = *bdlp;
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while (size > 0) {
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dma_addr_t addr;
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int chunk;
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if (azx_dev->core.frags >= AZX_MAX_BDL_ENTRIES)
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return -EINVAL;
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addr = snd_sgbuf_get_addr(dmab, ofs);
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/* program the address field of the BDL entry */
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bdl[0] = cpu_to_le32((u32)addr);
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bdl[1] = cpu_to_le32(upper_32_bits(addr));
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/* program the size field of the BDL entry */
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chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
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/* one BDLE cannot cross 4K boundary on CTHDA chips */
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if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
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u32 remain = 0x1000 - (ofs & 0xfff);
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if (chunk > remain)
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chunk = remain;
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}
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bdl[2] = cpu_to_le32(chunk);
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/* program the IOC to enable interrupt
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* only when the whole fragment is processed
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*/
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size -= chunk;
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bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
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bdl += 4;
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azx_dev->core.frags++;
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ofs += chunk;
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}
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*bdlp = bdl;
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return ofs;
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}
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/*
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* set up BDL entries
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*/
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static int azx_setup_periods(struct azx *chip,
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struct snd_pcm_substream *substream,
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struct azx_dev *azx_dev)
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{
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u32 *bdl;
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int i, ofs, periods, period_bytes;
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int pos_adj = 0;
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/* reset BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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period_bytes = azx_dev->core.period_bytes;
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periods = azx_dev->core.bufsize / period_bytes;
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/* program the initial BDL entries */
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bdl = (u32 *)azx_dev->core.bdl.area;
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ofs = 0;
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azx_dev->core.frags = 0;
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if (chip->bdl_pos_adj)
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pos_adj = chip->bdl_pos_adj[chip->dev_index];
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if (!azx_dev->core.no_period_wakeup && pos_adj > 0) {
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struct snd_pcm_runtime *runtime = substream->runtime;
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int pos_align = pos_adj;
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pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
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if (!pos_adj)
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pos_adj = pos_align;
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else
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pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
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pos_align;
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pos_adj = frames_to_bytes(runtime, pos_adj);
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if (pos_adj >= period_bytes) {
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dev_warn(chip->card->dev,"Too big adjustment %d\n",
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pos_adj);
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pos_adj = 0;
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} else {
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ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
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azx_dev,
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&bdl, ofs, pos_adj, true);
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if (ofs < 0)
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goto error;
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}
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} else
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pos_adj = 0;
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for (i = 0; i < periods; i++) {
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if (i == periods - 1 && pos_adj)
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ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
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azx_dev, &bdl, ofs,
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period_bytes - pos_adj, 0);
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else
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ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
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azx_dev, &bdl, ofs,
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period_bytes,
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!azx_dev->core.no_period_wakeup);
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if (ofs < 0)
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goto error;
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}
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return 0;
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error:
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dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
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azx_dev->core.bufsize, period_bytes);
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return -EINVAL;
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}
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/*
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* PCM ops
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*/
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@ -300,13 +91,8 @@ static int azx_pcm_close(struct snd_pcm_substream *substream)
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struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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struct azx *chip = apcm->chip;
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struct azx_dev *azx_dev = get_azx_dev(substream);
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unsigned long flags;
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mutex_lock(&chip->open_mutex);
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spin_lock_irqsave(&chip->reg_lock, flags);
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azx_dev->core.substream = NULL;
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azx_dev->core.running = 0;
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spin_unlock_irqrestore(&chip->reg_lock, flags);
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azx_release_device(azx_dev);
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if (hinfo->ops.close)
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hinfo->ops.close(hinfo, apcm->codec, substream);
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@ -346,14 +132,8 @@ static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
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/* reset BDL address */
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dsp_lock(azx_dev);
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if (!dsp_is_locked(azx_dev)) {
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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azx_sd_writel(chip, azx_dev, SD_CTL, 0);
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azx_dev->core.bufsize = 0;
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azx_dev->core.period_bytes = 0;
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azx_dev->core.format_val = 0;
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}
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if (!dsp_is_locked(azx_dev))
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snd_hdac_stream_cleanup(azx_stream(azx_dev));
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snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
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@ -411,29 +191,12 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
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azx_dev->core.period_bytes = period_bytes;
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azx_dev->core.format_val = format_val;
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azx_dev->core.no_period_wakeup = runtime->no_period_wakeup;
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err = azx_setup_periods(chip, substream, azx_dev);
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err = snd_hdac_stream_setup_periods(azx_stream(azx_dev));
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if (err < 0)
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goto unlock;
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}
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/* when LPIB delay correction gives a small negative value,
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* we ignore it; currently set the threshold statically to
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* 64 frames
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*/
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if (runtime->period_size > 64)
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azx_dev->core.delay_negative_threshold = -frames_to_bytes(runtime, 64);
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else
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azx_dev->core.delay_negative_threshold = 0;
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/* wallclk has 24Mhz clock source */
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azx_dev->core.period_wallclk = (((runtime->period_size * 24000) /
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runtime->rate) * 1000);
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azx_setup_controller(chip, azx_dev);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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azx_dev->core.fifo_size =
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azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
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else
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azx_dev->core.fifo_size = 0;
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snd_hdac_stream_setup(azx_stream(azx_dev));
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stream_tag = azx_dev->core.stream_tag;
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/* CA-IBG chips need the playback stream starting from 1 */
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@ -456,25 +219,31 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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struct azx *chip = apcm->chip;
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struct azx_dev *azx_dev;
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struct snd_pcm_substream *s;
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int rstart = 0, start, nsync = 0, sbits = 0;
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int nwait, timeout;
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struct hdac_stream *hstr;
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bool start;
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int sbits = 0;
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int sync_reg;
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azx_dev = get_azx_dev(substream);
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hstr = azx_stream(azx_dev);
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if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
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sync_reg = AZX_REG_OLD_SSYNC;
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else
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sync_reg = AZX_REG_SSYNC;
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if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
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return -EPIPE;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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rstart = 1;
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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start = 1;
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start = true;
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break;
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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start = 0;
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start = false;
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break;
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default:
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return -EINVAL;
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@ -485,18 +254,13 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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continue;
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azx_dev = get_azx_dev(s);
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sbits |= 1 << azx_dev->core.index;
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nsync++;
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snd_pcm_trigger_done(s, substream);
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}
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spin_lock(&chip->reg_lock);
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/* first, set SYNC bits of corresponding streams */
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if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
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azx_writel(chip, OLD_SSYNC,
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azx_readl(chip, OLD_SSYNC) | sbits);
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else
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azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
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snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
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snd_pcm_group_for_each_entry(s, substream) {
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if (s->pcm->card != substream->pcm->card)
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|
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@ -510,65 +274,14 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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}
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}
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spin_unlock(&chip->reg_lock);
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if (start) {
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/* wait until all FIFOs get ready */
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for (timeout = 5000; timeout; timeout--) {
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nwait = 0;
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snd_pcm_group_for_each_entry(s, substream) {
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if (s->pcm->card != substream->pcm->card)
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continue;
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azx_dev = get_azx_dev(s);
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if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
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SD_STS_FIFO_READY))
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nwait++;
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}
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if (!nwait)
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break;
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cpu_relax();
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}
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} else {
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/* wait until all RUN bits are cleared */
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for (timeout = 5000; timeout; timeout--) {
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nwait = 0;
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snd_pcm_group_for_each_entry(s, substream) {
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if (s->pcm->card != substream->pcm->card)
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continue;
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azx_dev = get_azx_dev(s);
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if (azx_sd_readb(chip, azx_dev, SD_CTL) &
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SD_CTL_DMA_START)
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nwait++;
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}
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if (!nwait)
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break;
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cpu_relax();
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}
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}
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snd_hdac_stream_sync(hstr, start, sbits);
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spin_lock(&chip->reg_lock);
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/* reset SYNC bits */
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if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
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azx_writel(chip, OLD_SSYNC,
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azx_readl(chip, OLD_SSYNC) & ~sbits);
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else
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azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
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if (start) {
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azx_timecounter_init(substream, 0, 0);
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snd_pcm_gettime(substream->runtime, &substream->runtime->trigger_tstamp);
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substream->runtime->trigger_tstamp_latched = true;
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if (nsync > 1) {
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cycle_t cycle_last;
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/* same start cycle for master and group */
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azx_dev = get_azx_dev(substream);
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cycle_last = azx_dev->core.tc.cycle_last;
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|
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snd_pcm_group_for_each_entry(s, substream) {
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if (s->pcm->card != substream->pcm->card)
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continue;
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azx_timecounter_init(s, 1, cycle_last);
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}
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}
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}
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snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
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if (start)
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snd_hdac_stream_timecounter_init(hstr, sbits);
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spin_unlock(&chip->reg_lock);
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return 0;
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}
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|
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@ -689,7 +402,6 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
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struct azx *chip = apcm->chip;
|
||||
struct azx_dev *azx_dev;
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
unsigned long flags;
|
||||
int err;
|
||||
int buff_step;
|
||||
|
||||
|
|
@ -700,6 +412,7 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
|
|||
err = -EBUSY;
|
||||
goto unlock;
|
||||
}
|
||||
runtime->private_data = azx_dev;
|
||||
runtime->hw = azx_pcm_hw;
|
||||
runtime->hw.channels_min = hinfo->channels_min;
|
||||
runtime->hw.channels_max = hinfo->channels_max;
|
||||
|
|
@ -761,12 +474,6 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
|
|||
runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&chip->reg_lock, flags);
|
||||
azx_dev->core.substream = substream;
|
||||
azx_dev->core.running = 0;
|
||||
spin_unlock_irqrestore(&chip->reg_lock, flags);
|
||||
|
||||
runtime->private_data = azx_dev;
|
||||
snd_pcm_set_sync(substream);
|
||||
mutex_unlock(&chip->open_mutex);
|
||||
return 0;
|
||||
|
|
@ -1271,60 +978,31 @@ static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|||
unsigned int byte_size,
|
||||
struct snd_dma_buffer *bufp)
|
||||
{
|
||||
u32 *bdl;
|
||||
struct azx *chip = bus->private_data;
|
||||
struct azx_dev *azx_dev;
|
||||
struct hdac_stream *hstr;
|
||||
bool saved = false;
|
||||
int err;
|
||||
|
||||
azx_dev = azx_get_dsp_loader_dev(chip);
|
||||
|
||||
dsp_lock(azx_dev);
|
||||
hstr = azx_stream(azx_dev);
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
if (azx_dev->core.running || azx_dev->core.locked) {
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
err = -EBUSY;
|
||||
goto unlock;
|
||||
if (hstr->opened) {
|
||||
chip->saved_azx_dev = *azx_dev;
|
||||
saved = true;
|
||||
}
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
|
||||
err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
|
||||
if (err < 0) {
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
if (saved)
|
||||
*azx_dev = chip->saved_azx_dev;
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
azx_dev->prepared = 0;
|
||||
chip->saved_azx_dev = *azx_dev;
|
||||
azx_dev->core.locked = 1;
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
|
||||
err = chip->io_ops->dma_alloc_pages(&bus->core, SNDRV_DMA_TYPE_DEV_SG,
|
||||
byte_size, bufp);
|
||||
if (err < 0)
|
||||
goto err_alloc;
|
||||
|
||||
azx_dev->core.bufsize = byte_size;
|
||||
azx_dev->core.period_bytes = byte_size;
|
||||
azx_dev->core.format_val = format;
|
||||
|
||||
snd_hdac_stream_reset(azx_stream(azx_dev));
|
||||
|
||||
/* reset BDL address */
|
||||
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
||||
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
||||
|
||||
azx_dev->core.frags = 0;
|
||||
bdl = (u32 *)azx_dev->core.bdl.area;
|
||||
err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
|
||||
if (err < 0)
|
||||
goto error;
|
||||
|
||||
azx_setup_controller(chip, azx_dev);
|
||||
dsp_unlock(azx_dev);
|
||||
return azx_dev->core.stream_tag;
|
||||
|
||||
error:
|
||||
chip->io_ops->dma_free_pages(&bus->core, bufp);
|
||||
err_alloc:
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
if (azx_dev->core.opened)
|
||||
*azx_dev = chip->saved_azx_dev;
|
||||
azx_dev->core.locked = 0;
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
unlock:
|
||||
dsp_unlock(azx_dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -1333,10 +1011,7 @@ static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
|
|||
struct azx *chip = bus->private_data;
|
||||
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
||||
|
||||
if (start)
|
||||
snd_hdac_stream_start(azx_stream(azx_dev), false);
|
||||
else
|
||||
snd_hdac_stream_stop(azx_stream(azx_dev));
|
||||
snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
|
||||
}
|
||||
|
||||
static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
||||
|
|
@ -1344,28 +1019,17 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
||||
struct hdac_stream *hstr = azx_stream(azx_dev);
|
||||
|
||||
if (!dmab->area || !azx_dev->core.locked)
|
||||
return;
|
||||
|
||||
dsp_lock(azx_dev);
|
||||
/* reset BDL address */
|
||||
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
||||
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
||||
azx_sd_writel(chip, azx_dev, SD_CTL, 0);
|
||||
azx_dev->core.bufsize = 0;
|
||||
azx_dev->core.period_bytes = 0;
|
||||
azx_dev->core.format_val = 0;
|
||||
|
||||
chip->io_ops->dma_free_pages(&bus->core, dmab);
|
||||
dmab->area = NULL;
|
||||
|
||||
snd_hdac_dsp_cleanup(hstr, dmab);
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
if (azx_dev->core.opened)
|
||||
if (hstr->opened)
|
||||
*azx_dev = chip->saved_azx_dev;
|
||||
azx_dev->core.locked = 0;
|
||||
hstr->locked = false;
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
dsp_unlock(azx_dev);
|
||||
}
|
||||
#endif /* CONFIG_SND_HDA_DSP_LOADER */
|
||||
|
||||
|
|
@ -1742,6 +1406,12 @@ int azx_bus_create(struct azx *chip, const char *model)
|
|||
bus->pci = chip->pci;
|
||||
bus->modelname = model;
|
||||
bus->ops = bus_ops;
|
||||
bus->core.snoop = azx_snoop(chip);
|
||||
if (chip->get_position[0] != azx_get_pos_lpib ||
|
||||
chip->get_position[1] != azx_get_pos_lpib)
|
||||
bus->core.use_posbuf = true;
|
||||
if (chip->bdl_pos_adj)
|
||||
bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index];
|
||||
|
||||
if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
|
||||
dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
|
||||
|
|
|
|||
|
|
@ -568,6 +568,9 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
|
|||
dev_info(chip->card->dev,
|
||||
"Invalid position buffer, using LPIB read method instead.\n");
|
||||
chip->get_position[stream] = azx_get_pos_lpib;
|
||||
if (chip->get_position[0] == azx_get_pos_lpib &&
|
||||
chip->get_position[1] == azx_get_pos_lpib)
|
||||
azx_bus(chip)->use_posbuf = false;
|
||||
pos = azx_get_pos_lpib(chip, azx_dev);
|
||||
chip->get_delay[stream] = NULL;
|
||||
} else {
|
||||
|
|
@ -1477,6 +1480,7 @@ static int azx_first_init(struct azx *chip)
|
|||
dev_err(card->dev, "ioremap error\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
azx_bus(chip)->remap_addr = chip->remap_addr; /* FIXME */
|
||||
|
||||
if (chip->msi) {
|
||||
if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
|
||||
|
|
|
|||
|
|
@ -325,6 +325,7 @@ static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
|
|||
return PTR_ERR(hda->regs);
|
||||
|
||||
chip->remap_addr = hda->regs + HDA_BAR0;
|
||||
azx_bus(chip)->remap_addr = chip->remap_addr; /* FIXME */
|
||||
chip->addr = res->start + HDA_BAR0;
|
||||
|
||||
err = hda_tegra_enable_clocks(hda);
|
||||
|
|
|
|||
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