ARM: OMAP2+: omap-pm-noop.c: Remove some unused functions
Removes some functions that are not used anywhere: omap_pm_set_max_dev_wakeup_lat() omap_pm_if_exit() omap_pm_cpu_get_freq() omap_pm_cpu_set_freq() omap_pm_cpu_get_freq_table() omap_pm_dsp_get_opp() omap_pm_dsp_set_min_opp() omap_pm_dsp_get_opp_table() omap_pm_set_min_clk_rate() omap_pm_set_max_sdma_lat() This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Rickard Strandqvist
Tony Lindgren
Родитель
b91dc63b2d
Коммит
cd0007e283
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@ -86,200 +86,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
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return 0;
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}
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int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
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long t)
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{
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if (!req_dev || !dev || t < -1) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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}
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if (t == -1)
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pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
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dev_name(dev));
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else
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pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
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dev_name(dev), t);
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/*
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* For current Linux, this needs to map the device to a
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* powerdomain, then go through the list of current max lat
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* constraints on that powerdomain and find the smallest. If
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* the latency constraint has changed, the code should
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* recompute the state to enter for the next powerdomain
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* state. Conceivably, this code should also determine
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* whether to actually disable the device clocks or not,
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* depending on how long it takes to re-enable the clocks.
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*
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* TI CDP code can call constraint_set here.
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*/
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return 0;
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}
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int omap_pm_set_max_sdma_lat(struct device *dev, long t)
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{
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if (!dev || t < -1) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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}
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if (t == -1)
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pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
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dev_name(dev));
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else
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pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
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dev_name(dev), t);
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/*
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* For current Linux PM QOS params, this code should scan the
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* list of maximum CPU and DMA latencies and select the
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* smallest, then set cpu_dma_latency pm_qos_param
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* accordingly.
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*
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* For future Linux PM QOS params, with separate CPU and DMA
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* latency params, this code should just set the dma_latency param.
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*
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* TI CDP code can call constraint_set here.
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*/
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return 0;
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}
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int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
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{
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if (!dev || !c || r < 0) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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}
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if (r == 0)
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pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
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dev_name(dev));
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else
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pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
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dev_name(dev), r);
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/*
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* Code in a real implementation should keep track of these
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* constraints on the clock, and determine the highest minimum
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* clock rate. It should iterate over each OPP and determine
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* whether the OPP will result in a clock rate that would
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* satisfy this constraint (and any other PM constraint in effect
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* at that time). Once it finds the lowest-voltage OPP that
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* meets those conditions, it should switch to it, or return
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* an error if the code is not capable of doing so.
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*/
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return 0;
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}
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/*
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* DSP Bridge-specific constraints
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*/
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const struct omap_opp *omap_pm_dsp_get_opp_table(void)
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{
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pr_debug("OMAP PM: DSP request for OPP table\n");
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/*
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* Return DSP frequency table here: The final item in the
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* array should have .rate = .opp_id = 0.
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*/
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return NULL;
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}
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void omap_pm_dsp_set_min_opp(u8 opp_id)
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{
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if (opp_id == 0) {
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WARN_ON(1);
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return;
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}
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pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
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/*
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*
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* For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
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* can just test to see which is higher, the CPU's desired OPP
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* ID or the DSP's desired OPP ID, and use whichever is
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* highest.
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*
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* In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
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* rate is keyed on MPU speed, not the OPP ID. So we need to
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* map the OPP ID to the MPU speed for use with clk_set_rate()
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* if it is higher than the current OPP clock rate.
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*
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*/
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}
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u8 omap_pm_dsp_get_opp(void)
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{
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pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
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/*
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* For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
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*
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* CDP12.14+:
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* Call clk_get_rate() on the OPP custom clock, map that to an
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* OPP ID using the tables defined in board-*.c/chip-*.c files.
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*/
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return 0;
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}
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/*
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* CPUFreq-originated constraint
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*
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* In the future, this should be handled by custom OPP clocktype
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* functions.
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*/
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struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
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{
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pr_debug("OMAP PM: CPUFreq request for frequency table\n");
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/*
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* Return CPUFreq frequency table here: loop over
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* all VDD1 clkrates, pull out the mpu_ck frequencies, build
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* table
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*/
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return NULL;
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}
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void omap_pm_cpu_set_freq(unsigned long f)
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{
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if (f == 0) {
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WARN_ON(1);
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return;
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}
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pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
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f);
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/*
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* For l-o dev tree, determine whether MPU freq or DSP OPP id
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* freq is higher. Find the OPP ID corresponding to the
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* higher frequency. Call clk_round_rate() and clk_set_rate()
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* on the OPP custom clock.
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*
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* CDP should just be able to set the VDD1 OPP clock rate here.
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*/
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}
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unsigned long omap_pm_cpu_get_freq(void)
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{
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pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
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/*
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* Call clk_get_rate() on the mpu_ck.
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*/
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return 0;
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}
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/**
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* omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
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@ -363,9 +173,3 @@ int __init omap_pm_if_init(void)
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{
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return 0;
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}
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void omap_pm_if_exit(void)
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{
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/* Deallocate CPUFreq frequency table here */
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}
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@ -50,14 +50,6 @@ int __init omap_pm_if_early_init(void);
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*/
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int __init omap_pm_if_init(void);
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/**
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* omap_pm_if_exit - OMAP PM exit code
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*
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* Exit code; currently unused. The "_if_" is to avoid name
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* collisions with the PM idle-loop code.
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*/
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void omap_pm_if_exit(void);
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/*
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* Device-driver-originated constraints (via board-*.c files, platform_data)
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*/
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@ -132,163 +124,6 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
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int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
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/**
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* omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
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* @req_dev: struct device * requesting the constraint, or NULL if none
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* @dev: struct device * to set the constraint one
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* @t: maximum device wakeup latency in microseconds
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*
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* Request that the maximum amount of time necessary for a device @dev
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* to become accessible after its clocks are enabled should be no
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* greater than @t microseconds. Specifically, this represents the
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* time from when a device driver enables device clocks with
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* clk_enable(), to when the register reads and writes on the device
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* will succeed. This function should be called before clk_disable()
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* is called, since the power state transition decision may be made
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* during clk_disable().
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*
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* It is intended that underlying PM code will use this information to
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* determine what power state to put the powerdomain enclosing this
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* device into.
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*
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* Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
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* previous wakeup latency values for this device. To remove the
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* wakeup latency restriction for this device, call with t = -1.
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*
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* Returns -EINVAL for an invalid argument, -ERANGE if the constraint
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* is not satisfiable, or 0 upon success.
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*/
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int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
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long t);
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/**
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* omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
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* @dev: struct device *
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* @t: maximum DMA transfer start latency in microseconds
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*
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* Request that the maximum system DMA transfer start latency for this
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* device 'dev' should be no greater than 't' microseconds. "DMA
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* transfer start latency" here is defined as the elapsed time from
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* when a device (e.g., McBSP) requests that a system DMA transfer
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* start or continue, to the time at which data starts to flow into
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* that device from the system DMA controller.
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*
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* It is intended that underlying PM code will use this information to
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* determine what power state to put the CORE powerdomain into.
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*
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* Since system DMA transfers may not involve the MPU, this function
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* will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
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* so. Similarly, this function will not affect device wakeup latency
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* -- use set_max_dev_wakeup_lat() to affect that.
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*
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* Multiple calls to set_max_sdma_lat() will replace the previous t
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* value for this device. To remove the maximum DMA latency for this
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* device, call with t = -1.
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*
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* Returns -EINVAL for an invalid argument, -ERANGE if the constraint
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* is not satisfiable, or 0 upon success.
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*/
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int omap_pm_set_max_sdma_lat(struct device *dev, long t);
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/**
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* omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
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* @dev: struct device * requesting the constraint
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* @clk: struct clk * to set the minimum rate constraint on
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* @r: minimum rate in Hz
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*
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* Request that the minimum clock rate on the device @dev's clk @clk
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* be no less than @r Hz.
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*
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* It is expected that the OMAP PM code will use this information to
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* find an OPP or clock setting that will satisfy this clock rate
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* constraint, along with any other applicable system constraints on
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* the clock rate or corresponding voltage, etc.
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*
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* omap_pm_set_min_clk_rate() differs from the clock code's
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* clk_set_rate() in that it considers other constraints before taking
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* any hardware action, and may change a system OPP rather than just a
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* clock rate. clk_set_rate() is intended to be a low-level
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* interface.
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*
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* omap_pm_set_min_clk_rate() is easily open to abuse. A better API
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* would be something like "omap_pm_set_min_dev_performance()";
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* however, there is no easily-generalizable concept of performance
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* that applies to all devices. Only a device (and possibly the
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* device subsystem) has both the subsystem-specific knowledge, and
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* the hardware IP block-specific knowledge, to translate a constraint
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* on "touchscreen sampling accuracy" or "number of pixels or polygons
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* rendered per second" to a clock rate. This translation can be
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* dependent on the hardware IP block's revision, or firmware version,
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* and the driver is the only code on the system that has this
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* information and can know how to translate that into a clock rate.
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*
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* The intended use-case for this function is for userspace or other
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* kernel code to communicate a particular performance requirement to
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* a subsystem; then for the subsystem to communicate that requirement
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* to something that is meaningful to the device driver; then for the
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* device driver to convert that requirement to a clock rate, and to
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* then call omap_pm_set_min_clk_rate().
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*
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* Users of this function (such as device drivers) should not simply
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* call this function with some high clock rate to ensure "high
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* performance." Rather, the device driver should take a performance
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* constraint from its subsystem, such as "render at least X polygons
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* per second," and use some formula or table to convert that into a
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* clock rate constraint given the hardware type and hardware
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* revision. Device drivers or subsystems should not assume that they
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* know how to make a power/performance tradeoff - some device use
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* cases may tolerate a lower-fidelity device function for lower power
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* consumption; others may demand a higher-fidelity device function,
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* no matter what the power consumption.
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*
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* Multiple calls to omap_pm_set_min_clk_rate() will replace the
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* previous rate value for the device @dev. To remove the minimum clock
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* rate constraint for the device, call with r = 0.
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*
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* Returns -EINVAL for an invalid argument, -ERANGE if the constraint
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* is not satisfiable, or 0 upon success.
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*/
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int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
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/*
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* DSP Bridge-specific constraints
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*/
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/**
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* omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
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*
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* Intended for use by DSPBridge. Returns an array of OPP->DSP clock
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* frequency entries. The final item in the array should have .rate =
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* .opp_id = 0.
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*/
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const struct omap_opp *omap_pm_dsp_get_opp_table(void);
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/**
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* omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
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* @opp_id: target DSP OPP ID
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*
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* Set a minimum OPP ID for the DSP. This is intended to be called
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* only from the DSP Bridge MPU-side driver. Unfortunately, the only
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* information that code receives from the DSP/BIOS load estimator is the
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* target OPP ID; hence, this interface. No return value.
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*/
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void omap_pm_dsp_set_min_opp(u8 opp_id);
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/**
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* omap_pm_dsp_get_opp - report the current DSP OPP ID
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*
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* Report the current OPP for the DSP. Since on OMAP3, the DSP and
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* MPU share a single voltage domain, the OPP ID returned back may
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* represent a higher DSP speed than the OPP requested via
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* omap_pm_dsp_set_min_opp().
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*
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* Returns the current VDD1 OPP ID, or 0 upon error.
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*/
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u8 omap_pm_dsp_get_opp(void);
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/*
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* CPUFreq-originated constraint
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*
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@ -296,33 +131,6 @@ u8 omap_pm_dsp_get_opp(void);
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* functions.
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*/
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/**
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* omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
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*
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* Provide a frequency table usable by CPUFreq for the current chip/board.
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* Returns a pointer to a struct cpufreq_frequency_table array or NULL
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* upon error.
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*/
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struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
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/**
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* omap_pm_cpu_set_freq - set the current minimum MPU frequency
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* @f: MPU frequency in Hz
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*
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* Set the current minimum CPU frequency. The actual CPU frequency
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* used could end up higher if the DSP requested a higher OPP.
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* Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
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* return value.
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*/
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void omap_pm_cpu_set_freq(unsigned long f);
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/**
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* omap_pm_cpu_get_freq - report the current CPU frequency
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*
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* Returns the current MPU frequency, or 0 upon error.
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*/
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unsigned long omap_pm_cpu_get_freq(void);
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/*
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* Device context loss tracking
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