dmaengine: remove iop-adma driver
The iop32x platform was removed, so this driver is no longer needed. Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/20221019150410.3851944-10-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Arnd Bergmann
Vinod Koul
Родитель
568aa6dd64
Коммит
cd0ab43ec9
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@ -357,14 +357,6 @@ config INTEL_IOATDMA
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If unsure, say N.
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config INTEL_IOP_ADMA
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tristate "Intel IOP32x ADMA support"
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depends on ARCH_IOP32X || COMPILE_TEST
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select DMA_ENGINE
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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help
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Enable support for the Intel(R) IOP Series RAID engines.
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config K3_DMA
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tristate "Hisilicon K3 DMA support"
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depends on ARCH_HI3xxx || ARCH_HISI || COMPILE_TEST
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@ -44,7 +44,6 @@ obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
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obj-$(CONFIG_INTEL_IDMA64) += idma64.o
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obj-$(CONFIG_INTEL_IOATDMA) += ioat/
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obj-y += idxd/
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obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
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obj-$(CONFIG_K3_DMA) += k3dma.o
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obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
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obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -1,914 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2006, Intel Corporation.
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*/
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#ifndef _ADMA_H
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#define _ADMA_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/platform_data/dma-iop32x.h>
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/* Memory copy units */
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#define DMA_CCR(chan) (chan->mmr_base + 0x0)
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#define DMA_CSR(chan) (chan->mmr_base + 0x4)
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#define DMA_DAR(chan) (chan->mmr_base + 0xc)
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#define DMA_NDAR(chan) (chan->mmr_base + 0x10)
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#define DMA_PADR(chan) (chan->mmr_base + 0x14)
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#define DMA_PUADR(chan) (chan->mmr_base + 0x18)
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#define DMA_LADR(chan) (chan->mmr_base + 0x1c)
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#define DMA_BCR(chan) (chan->mmr_base + 0x20)
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#define DMA_DCR(chan) (chan->mmr_base + 0x24)
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/* Application accelerator unit */
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#define AAU_ACR(chan) (chan->mmr_base + 0x0)
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#define AAU_ASR(chan) (chan->mmr_base + 0x4)
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#define AAU_ADAR(chan) (chan->mmr_base + 0x8)
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#define AAU_ANDAR(chan) (chan->mmr_base + 0xc)
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#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2)))
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#define AAU_DAR(chan) (chan->mmr_base + 0x20)
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#define AAU_ABCR(chan) (chan->mmr_base + 0x24)
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#define AAU_ADCR(chan) (chan->mmr_base + 0x28)
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#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
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#define AAU_EDCR0_IDX 8
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#define AAU_EDCR1_IDX 17
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#define AAU_EDCR2_IDX 26
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struct iop3xx_aau_desc_ctrl {
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unsigned int int_en:1;
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unsigned int blk1_cmd_ctrl:3;
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unsigned int blk2_cmd_ctrl:3;
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unsigned int blk3_cmd_ctrl:3;
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unsigned int blk4_cmd_ctrl:3;
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unsigned int blk5_cmd_ctrl:3;
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unsigned int blk6_cmd_ctrl:3;
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unsigned int blk7_cmd_ctrl:3;
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unsigned int blk8_cmd_ctrl:3;
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unsigned int blk_ctrl:2;
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unsigned int dual_xor_en:1;
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unsigned int tx_complete:1;
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unsigned int zero_result_err:1;
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unsigned int zero_result_en:1;
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unsigned int dest_write_en:1;
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};
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struct iop3xx_aau_e_desc_ctrl {
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unsigned int reserved:1;
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unsigned int blk1_cmd_ctrl:3;
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unsigned int blk2_cmd_ctrl:3;
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unsigned int blk3_cmd_ctrl:3;
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unsigned int blk4_cmd_ctrl:3;
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unsigned int blk5_cmd_ctrl:3;
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unsigned int blk6_cmd_ctrl:3;
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unsigned int blk7_cmd_ctrl:3;
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unsigned int blk8_cmd_ctrl:3;
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unsigned int reserved2:7;
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};
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struct iop3xx_dma_desc_ctrl {
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unsigned int pci_transaction:4;
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unsigned int int_en:1;
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unsigned int dac_cycle_en:1;
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unsigned int mem_to_mem_en:1;
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unsigned int crc_data_tx_en:1;
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unsigned int crc_gen_en:1;
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unsigned int crc_seed_dis:1;
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unsigned int reserved:21;
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unsigned int crc_tx_complete:1;
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};
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struct iop3xx_desc_dma {
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u32 next_desc;
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union {
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u32 pci_src_addr;
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u32 pci_dest_addr;
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u32 src_addr;
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};
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union {
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u32 upper_pci_src_addr;
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u32 upper_pci_dest_addr;
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};
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union {
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u32 local_pci_src_addr;
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u32 local_pci_dest_addr;
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u32 dest_addr;
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};
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u32 byte_count;
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union {
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u32 desc_ctrl;
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struct iop3xx_dma_desc_ctrl desc_ctrl_field;
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};
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u32 crc_addr;
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};
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struct iop3xx_desc_aau {
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u32 next_desc;
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u32 src[4];
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u32 dest_addr;
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u32 byte_count;
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union {
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u32 desc_ctrl;
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struct iop3xx_aau_desc_ctrl desc_ctrl_field;
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};
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union {
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u32 src_addr;
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u32 e_desc_ctrl;
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struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
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} src_edc[31];
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};
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struct iop3xx_aau_gfmr {
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unsigned int gfmr1:8;
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unsigned int gfmr2:8;
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unsigned int gfmr3:8;
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unsigned int gfmr4:8;
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};
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struct iop3xx_desc_pq_xor {
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u32 next_desc;
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u32 src[3];
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union {
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u32 data_mult1;
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struct iop3xx_aau_gfmr data_mult1_field;
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};
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u32 dest_addr;
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u32 byte_count;
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union {
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u32 desc_ctrl;
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struct iop3xx_aau_desc_ctrl desc_ctrl_field;
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};
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union {
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u32 src_addr;
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u32 e_desc_ctrl;
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struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
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u32 data_multiplier;
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struct iop3xx_aau_gfmr data_mult_field;
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u32 reserved;
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} src_edc_gfmr[19];
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};
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struct iop3xx_desc_dual_xor {
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u32 next_desc;
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u32 src0_addr;
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u32 src1_addr;
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u32 h_src_addr;
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u32 d_src_addr;
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u32 h_dest_addr;
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u32 byte_count;
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union {
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u32 desc_ctrl;
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struct iop3xx_aau_desc_ctrl desc_ctrl_field;
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};
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u32 d_dest_addr;
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};
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union iop3xx_desc {
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struct iop3xx_desc_aau *aau;
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struct iop3xx_desc_dma *dma;
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struct iop3xx_desc_pq_xor *pq_xor;
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struct iop3xx_desc_dual_xor *dual_xor;
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void *ptr;
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};
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/* No support for p+q operations */
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static inline int
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iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op)
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{
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BUG();
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return 0;
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}
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static inline void
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iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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BUG();
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}
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static inline void
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iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
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{
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BUG();
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}
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static inline void
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iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
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dma_addr_t addr, unsigned char coef)
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{
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BUG();
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}
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static inline int
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iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op)
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{
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BUG();
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return 0;
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}
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static inline void
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iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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BUG();
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}
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static inline void
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iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
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{
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BUG();
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}
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#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
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static inline void
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iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
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dma_addr_t *src)
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{
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BUG();
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}
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static inline int iop_adma_get_max_xor(void)
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{
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return 32;
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}
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static inline int iop_adma_get_max_pq(void)
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{
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BUG();
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return 0;
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}
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static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
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{
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int id = chan->device->id;
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switch (id) {
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case DMA0_ID:
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case DMA1_ID:
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return __raw_readl(DMA_DAR(chan));
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case AAU_ID:
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return __raw_readl(AAU_ADAR(chan));
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default:
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BUG();
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}
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return 0;
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}
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static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
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u32 next_desc_addr)
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{
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int id = chan->device->id;
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switch (id) {
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case DMA0_ID:
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case DMA1_ID:
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__raw_writel(next_desc_addr, DMA_NDAR(chan));
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break;
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case AAU_ID:
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__raw_writel(next_desc_addr, AAU_ANDAR(chan));
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break;
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}
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}
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#define IOP_ADMA_STATUS_BUSY (1 << 10)
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#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024)
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#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024)
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#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
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static inline int iop_chan_is_busy(struct iop_adma_chan *chan)
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{
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u32 status = __raw_readl(DMA_CSR(chan));
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return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0;
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}
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static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc,
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int num_slots)
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{
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/* num_slots will only ever be 1, 2, 4, or 8 */
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return (desc->idx & (num_slots - 1)) ? 0 : 1;
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}
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/* to do: support large (i.e. > hw max) buffer sizes */
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static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
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{
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*slots_per_op = 1;
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return 1;
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}
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/* to do: support large (i.e. > hw max) buffer sizes */
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static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
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{
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*slots_per_op = 1;
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return 1;
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}
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static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
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int *slots_per_op)
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{
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static const char slot_count_table[] = {
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1, 1, 1, 1, /* 01 - 04 */
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2, 2, 2, 2, /* 05 - 08 */
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4, 4, 4, 4, /* 09 - 12 */
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4, 4, 4, 4, /* 13 - 16 */
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8, 8, 8, 8, /* 17 - 20 */
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8, 8, 8, 8, /* 21 - 24 */
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8, 8, 8, 8, /* 25 - 28 */
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8, 8, 8, 8, /* 29 - 32 */
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};
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*slots_per_op = slot_count_table[src_cnt - 1];
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return *slots_per_op;
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}
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static inline int
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iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan)
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{
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switch (chan->device->id) {
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case DMA0_ID:
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case DMA1_ID:
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return iop_chan_memcpy_slot_count(0, slots_per_op);
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case AAU_ID:
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return iop3xx_aau_xor_slot_count(0, 2, slots_per_op);
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default:
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BUG();
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}
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return 0;
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}
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static inline int iop_chan_xor_slot_count(size_t len, int src_cnt,
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int *slots_per_op)
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{
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int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
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if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT)
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return slot_cnt;
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len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
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while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) {
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len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
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slot_cnt += *slots_per_op;
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}
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slot_cnt += *slots_per_op;
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return slot_cnt;
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}
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/* zero sum on iop3xx is limited to 1k at a time so it requires multiple
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* descriptors
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*/
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static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt,
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int *slots_per_op)
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{
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int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
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if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT)
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return slot_cnt;
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len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
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while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
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len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
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slot_cnt += *slots_per_op;
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}
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slot_cnt += *slots_per_op;
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return slot_cnt;
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}
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static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
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switch (chan->device->id) {
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case DMA0_ID:
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case DMA1_ID:
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return hw_desc.dma->byte_count;
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case AAU_ID:
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return hw_desc.aau->byte_count;
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default:
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BUG();
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}
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return 0;
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}
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/* translate the src_idx to a descriptor word index */
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static inline int __desc_idx(int src_idx)
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{
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static const int desc_idx_table[] = { 0, 0, 0, 0,
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0, 1, 2, 3,
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5, 6, 7, 8,
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9, 10, 11, 12,
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14, 15, 16, 17,
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18, 19, 20, 21,
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23, 24, 25, 26,
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27, 28, 29, 30,
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};
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return desc_idx_table[src_idx];
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}
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static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan,
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int src_idx)
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{
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union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
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switch (chan->device->id) {
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case DMA0_ID:
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case DMA1_ID:
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return hw_desc.dma->src_addr;
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case AAU_ID:
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break;
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default:
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BUG();
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}
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if (src_idx < 4)
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return hw_desc.aau->src[src_idx];
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else
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return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;
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}
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|
||||
static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc,
|
||||
int src_idx, dma_addr_t addr)
|
||||
{
|
||||
if (src_idx < 4)
|
||||
hw_desc->src[src_idx] = addr;
|
||||
else
|
||||
hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
|
||||
{
|
||||
struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
|
||||
union {
|
||||
u32 value;
|
||||
struct iop3xx_dma_desc_ctrl field;
|
||||
} u_desc_ctrl;
|
||||
|
||||
u_desc_ctrl.value = 0;
|
||||
u_desc_ctrl.field.mem_to_mem_en = 1;
|
||||
u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */
|
||||
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
|
||||
hw_desc->desc_ctrl = u_desc_ctrl.value;
|
||||
hw_desc->upper_pci_src_addr = 0;
|
||||
hw_desc->crc_addr = 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
|
||||
{
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
|
||||
union {
|
||||
u32 value;
|
||||
struct iop3xx_aau_desc_ctrl field;
|
||||
} u_desc_ctrl;
|
||||
|
||||
u_desc_ctrl.value = 0;
|
||||
u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */
|
||||
u_desc_ctrl.field.dest_write_en = 1;
|
||||
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
|
||||
hw_desc->desc_ctrl = u_desc_ctrl.value;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt,
|
||||
unsigned long flags)
|
||||
{
|
||||
int i, shift;
|
||||
u32 edcr;
|
||||
union {
|
||||
u32 value;
|
||||
struct iop3xx_aau_desc_ctrl field;
|
||||
} u_desc_ctrl;
|
||||
|
||||
u_desc_ctrl.value = 0;
|
||||
switch (src_cnt) {
|
||||
case 25 ... 32:
|
||||
u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
|
||||
edcr = 0;
|
||||
shift = 1;
|
||||
for (i = 24; i < src_cnt; i++) {
|
||||
edcr |= (1 << shift);
|
||||
shift += 3;
|
||||
}
|
||||
hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
|
||||
src_cnt = 24;
|
||||
fallthrough;
|
||||
case 17 ... 24:
|
||||
if (!u_desc_ctrl.field.blk_ctrl) {
|
||||
hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
|
||||
u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
|
||||
}
|
||||
edcr = 0;
|
||||
shift = 1;
|
||||
for (i = 16; i < src_cnt; i++) {
|
||||
edcr |= (1 << shift);
|
||||
shift += 3;
|
||||
}
|
||||
hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
|
||||
src_cnt = 16;
|
||||
fallthrough;
|
||||
case 9 ... 16:
|
||||
if (!u_desc_ctrl.field.blk_ctrl)
|
||||
u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
|
||||
edcr = 0;
|
||||
shift = 1;
|
||||
for (i = 8; i < src_cnt; i++) {
|
||||
edcr |= (1 << shift);
|
||||
shift += 3;
|
||||
}
|
||||
hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
|
||||
src_cnt = 8;
|
||||
fallthrough;
|
||||
case 2 ... 8:
|
||||
shift = 1;
|
||||
for (i = 0; i < src_cnt; i++) {
|
||||
u_desc_ctrl.value |= (1 << shift);
|
||||
shift += 3;
|
||||
}
|
||||
|
||||
if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
|
||||
u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
|
||||
}
|
||||
|
||||
u_desc_ctrl.field.dest_write_en = 1;
|
||||
u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */
|
||||
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
|
||||
hw_desc->desc_ctrl = u_desc_ctrl.value;
|
||||
|
||||
return u_desc_ctrl.value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
|
||||
unsigned long flags)
|
||||
{
|
||||
iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags);
|
||||
}
|
||||
|
||||
/* return the number of operations */
|
||||
static inline int
|
||||
iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
|
||||
unsigned long flags)
|
||||
{
|
||||
int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
|
||||
struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter;
|
||||
union {
|
||||
u32 value;
|
||||
struct iop3xx_aau_desc_ctrl field;
|
||||
} u_desc_ctrl;
|
||||
int i, j;
|
||||
|
||||
hw_desc = desc->hw_desc;
|
||||
|
||||
for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;
|
||||
i += slots_per_op, j++) {
|
||||
iter = iop_hw_desc_slot_idx(hw_desc, i);
|
||||
u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags);
|
||||
u_desc_ctrl.field.dest_write_en = 0;
|
||||
u_desc_ctrl.field.zero_result_en = 1;
|
||||
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
|
||||
iter->desc_ctrl = u_desc_ctrl.value;
|
||||
|
||||
/* for the subsequent descriptors preserve the store queue
|
||||
* and chain them together
|
||||
*/
|
||||
if (i) {
|
||||
prev_hw_desc =
|
||||
iop_hw_desc_slot_idx(hw_desc, i - slots_per_op);
|
||||
prev_hw_desc->next_desc =
|
||||
(u32) (desc->async_tx.phys + (i << 5));
|
||||
}
|
||||
}
|
||||
|
||||
return j;
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
|
||||
union {
|
||||
u32 value;
|
||||
struct iop3xx_aau_desc_ctrl field;
|
||||
} u_desc_ctrl;
|
||||
|
||||
u_desc_ctrl.value = 0;
|
||||
switch (src_cnt) {
|
||||
case 25 ... 32:
|
||||
u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
|
||||
hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
|
||||
fallthrough;
|
||||
case 17 ... 24:
|
||||
if (!u_desc_ctrl.field.blk_ctrl) {
|
||||
hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
|
||||
u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
|
||||
}
|
||||
hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
|
||||
fallthrough;
|
||||
case 9 ... 16:
|
||||
if (!u_desc_ctrl.field.blk_ctrl)
|
||||
u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
|
||||
hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;
|
||||
fallthrough;
|
||||
case 1 ... 8:
|
||||
if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
|
||||
u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
|
||||
}
|
||||
|
||||
u_desc_ctrl.field.dest_write_en = 0;
|
||||
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
|
||||
hw_desc->desc_ctrl = u_desc_ctrl.value;
|
||||
}
|
||||
|
||||
static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
|
||||
struct iop_adma_chan *chan,
|
||||
u32 byte_count)
|
||||
{
|
||||
union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
|
||||
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
hw_desc.dma->byte_count = byte_count;
|
||||
break;
|
||||
case AAU_ID:
|
||||
hw_desc.aau->byte_count = byte_count;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
|
||||
struct iop_adma_chan *chan)
|
||||
{
|
||||
union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
|
||||
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
iop_desc_init_memcpy(desc, 1);
|
||||
hw_desc.dma->byte_count = 0;
|
||||
hw_desc.dma->dest_addr = 0;
|
||||
hw_desc.dma->src_addr = 0;
|
||||
break;
|
||||
case AAU_ID:
|
||||
iop_desc_init_null_xor(desc, 2, 1);
|
||||
hw_desc.aau->byte_count = 0;
|
||||
hw_desc.aau->dest_addr = 0;
|
||||
hw_desc.aau->src[0] = 0;
|
||||
hw_desc.aau->src[1] = 0;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
|
||||
{
|
||||
int slots_per_op = desc->slots_per_op;
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
|
||||
int i = 0;
|
||||
|
||||
if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
|
||||
hw_desc->byte_count = len;
|
||||
} else {
|
||||
do {
|
||||
iter = iop_hw_desc_slot_idx(hw_desc, i);
|
||||
iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
|
||||
len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
|
||||
i += slots_per_op;
|
||||
} while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
|
||||
|
||||
iter = iop_hw_desc_slot_idx(hw_desc, i);
|
||||
iter->byte_count = len;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
|
||||
struct iop_adma_chan *chan,
|
||||
dma_addr_t addr)
|
||||
{
|
||||
union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
|
||||
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
hw_desc.dma->dest_addr = addr;
|
||||
break;
|
||||
case AAU_ID:
|
||||
hw_desc.aau->dest_addr = addr;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
|
||||
dma_addr_t addr)
|
||||
{
|
||||
struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
|
||||
hw_desc->src_addr = addr;
|
||||
}
|
||||
|
||||
static inline void
|
||||
iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
|
||||
dma_addr_t addr)
|
||||
{
|
||||
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
|
||||
int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
|
||||
int i;
|
||||
|
||||
for (i = 0; (slot_cnt -= slots_per_op) >= 0;
|
||||
i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
|
||||
iter = iop_hw_desc_slot_idx(hw_desc, i);
|
||||
iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
|
||||
int src_idx, dma_addr_t addr)
|
||||
{
|
||||
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
|
||||
int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
|
||||
int i;
|
||||
|
||||
for (i = 0; (slot_cnt -= slots_per_op) >= 0;
|
||||
i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) {
|
||||
iter = iop_hw_desc_slot_idx(hw_desc, i);
|
||||
iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
|
||||
u32 next_desc_addr)
|
||||
{
|
||||
/* hw_desc->next_desc is the same location for all channels */
|
||||
union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
|
||||
|
||||
iop_paranoia(hw_desc.dma->next_desc);
|
||||
hw_desc.dma->next_desc = next_desc_addr;
|
||||
}
|
||||
|
||||
static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
|
||||
{
|
||||
/* hw_desc->next_desc is the same location for all channels */
|
||||
union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
|
||||
return hw_desc.dma->next_desc;
|
||||
}
|
||||
|
||||
static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
|
||||
{
|
||||
/* hw_desc->next_desc is the same location for all channels */
|
||||
union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
|
||||
hw_desc.dma->next_desc = 0;
|
||||
}
|
||||
|
||||
static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
|
||||
u32 val)
|
||||
{
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
|
||||
hw_desc->src[0] = val;
|
||||
}
|
||||
|
||||
static inline enum sum_check_flags
|
||||
iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
|
||||
{
|
||||
struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
|
||||
struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
|
||||
|
||||
iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en));
|
||||
return desc_ctrl.zero_result_err << SUM_CHECK_P;
|
||||
}
|
||||
|
||||
static inline void iop_chan_append(struct iop_adma_chan *chan)
|
||||
{
|
||||
u32 dma_chan_ctrl;
|
||||
|
||||
dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
|
||||
dma_chan_ctrl |= 0x2;
|
||||
__raw_writel(dma_chan_ctrl, DMA_CCR(chan));
|
||||
}
|
||||
|
||||
static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
|
||||
{
|
||||
return __raw_readl(DMA_CSR(chan));
|
||||
}
|
||||
|
||||
static inline void iop_chan_disable(struct iop_adma_chan *chan)
|
||||
{
|
||||
u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
|
||||
dma_chan_ctrl &= ~1;
|
||||
__raw_writel(dma_chan_ctrl, DMA_CCR(chan));
|
||||
}
|
||||
|
||||
static inline void iop_chan_enable(struct iop_adma_chan *chan)
|
||||
{
|
||||
u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
|
||||
|
||||
dma_chan_ctrl |= 1;
|
||||
__raw_writel(dma_chan_ctrl, DMA_CCR(chan));
|
||||
}
|
||||
|
||||
static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
|
||||
{
|
||||
u32 status = __raw_readl(DMA_CSR(chan));
|
||||
status &= (1 << 9);
|
||||
__raw_writel(status, DMA_CSR(chan));
|
||||
}
|
||||
|
||||
static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
|
||||
{
|
||||
u32 status = __raw_readl(DMA_CSR(chan));
|
||||
status &= (1 << 8);
|
||||
__raw_writel(status, DMA_CSR(chan));
|
||||
}
|
||||
|
||||
static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
|
||||
{
|
||||
u32 status = __raw_readl(DMA_CSR(chan));
|
||||
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1);
|
||||
break;
|
||||
case AAU_ID:
|
||||
status &= (1 << 5);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
__raw_writel(status, DMA_CSR(chan));
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
return test_bit(5, &status);
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
return test_bit(2, &status);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
return test_bit(3, &status);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
|
||||
{
|
||||
switch (chan->device->id) {
|
||||
case DMA0_ID:
|
||||
case DMA1_ID:
|
||||
return test_bit(1, &status);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
#endif /* _ADMA_H */
|
||||
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