sunbmac: use standard #defines from mii.h.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
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@ -17,6 +17,7 @@
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#include <linux/crc32.h>
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#include <linux/errno.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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@ -500,13 +501,13 @@ static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
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/* Reset the PHY. */
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bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
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bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
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bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
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bp->sw_bmcr = (BMCR_RESET);
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bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
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bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
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timeout = 64;
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while (--timeout) {
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
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if ((bp->sw_bmcr & BMCR_RESET) == 0)
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break;
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udelay(20);
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@ -514,11 +515,11 @@ static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
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if (timeout == 0)
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printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
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/* Now we try 10baseT. */
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bp->sw_bmcr &= ~(BMCR_SPEED100);
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bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
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bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
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return 0;
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}
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@ -534,8 +535,8 @@ static void bigmac_timer(unsigned long data)
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bp->timer_ticks++;
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if (bp->timer_state == ltrywait) {
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bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
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bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
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if (bp->sw_bmsr & BMSR_LSTATUS) {
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printk(KERN_INFO "%s: Link is now up at %s.\n",
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bp->dev->name,
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@ -588,18 +589,18 @@ static void bigmac_begin_auto_negotiation(struct bigmac *bp)
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int timeout;
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/* Grab new software copies of PHY registers. */
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bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
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bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
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/* Reset the PHY. */
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bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
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bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
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bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
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bp->sw_bmcr = (BMCR_RESET);
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bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
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bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
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timeout = 64;
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while (--timeout) {
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
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if ((bp->sw_bmcr & BMCR_RESET) == 0)
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break;
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udelay(20);
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@ -607,11 +608,11 @@ static void bigmac_begin_auto_negotiation(struct bigmac *bp)
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if (timeout == 0)
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printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
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bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
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/* First we try 100baseT. */
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bp->sw_bmcr |= BMCR_SPEED100;
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bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
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bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
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bp->timer_state = ltrywait;
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bp->timer_ticks = 0;
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@ -1054,7 +1055,7 @@ static u32 bigmac_get_link(struct net_device *dev)
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struct bigmac *bp = netdev_priv(dev);
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spin_lock_irq(&bp->lock);
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bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
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bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, MII_BMSR);
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spin_unlock_irq(&bp->lock);
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return (bp->sw_bmsr & BMSR_LSTATUS);
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@ -223,23 +223,6 @@
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#define BIGMAC_PHY_EXTERNAL 0 /* External transceiver */
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#define BIGMAC_PHY_INTERNAL 1 /* Internal transceiver */
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/* PHY registers */
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#define BIGMAC_BMCR 0x00 /* Basic mode control register */
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#define BIGMAC_BMSR 0x01 /* Basic mode status register */
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/* BMCR bits */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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/* BMSR bits */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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#define BMSR_JCD 0x0002 /* Jabber detected */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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/* Ring descriptors and such, same as Quad Ethernet. */
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struct be_rxd {
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u32 rx_flags;
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