drm/i915: Clean up cursor junk from intel_crtc
Move cursor_base, cursor_cntl, and cursor_size from intel_crtc into intel_plane so that we don't need the crtc for cursor stuff so much. Also entirely nuke cursor_addr which IMO doesn't provide any benefit since it's not actually used by the cursor code itself. I'm not 100% sure what the SKL+ DDB is code is after by looking at cursor_addr so I just make it do its checks unconditionally. If that's not correct then we should likely replace it with somehting like plane_state->visible. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170327185546.2977-5-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
Ville Syrjälä
Родитель
1cecc830e6
Коммит
cd5dcbf1b2
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@ -3042,36 +3042,6 @@ static void intel_connector_info(struct seq_file *m,
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intel_seq_print_mode(m, 2, mode);
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}
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static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
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{
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u32 state;
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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else
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state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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return state;
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}
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static bool cursor_position(struct drm_i915_private *dev_priv,
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int pipe, int *x, int *y)
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{
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u32 pos;
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pos = I915_READ(CURPOS(pipe));
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*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
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if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
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*x = -*x;
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*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
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if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
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*y = -*y;
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return cursor_active(dev_priv, pipe);
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}
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static const char *plane_type(enum drm_plane_type type)
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{
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switch (type) {
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@ -3193,9 +3163,7 @@ static int i915_display_info(struct seq_file *m, void *unused)
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seq_printf(m, "CRTC info\n");
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seq_printf(m, "---------\n");
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for_each_intel_crtc(dev, crtc) {
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bool active;
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struct intel_crtc_state *pipe_config;
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int x, y;
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drm_modeset_lock(&crtc->base.mutex, NULL);
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pipe_config = to_intel_crtc_state(crtc->base.state);
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@ -3207,14 +3175,18 @@ static int i915_display_info(struct seq_file *m, void *unused)
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yesno(pipe_config->dither), pipe_config->pipe_bpp);
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if (pipe_config->base.active) {
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struct intel_plane *cursor =
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to_intel_plane(crtc->base.cursor);
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intel_crtc_info(m, crtc);
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active = cursor_position(dev_priv, crtc->pipe, &x, &y);
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seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
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yesno(crtc->cursor_base),
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x, y, crtc->base.cursor->state->crtc_w,
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crtc->base.cursor->state->crtc_h,
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crtc->cursor_addr, yesno(active));
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seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
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yesno(cursor->base.state->visible),
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cursor->base.state->crtc_x,
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cursor->base.state->crtc_y,
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cursor->base.state->crtc_w,
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cursor->base.state->crtc_h,
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cursor->cursor.base);
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intel_scaler_info(m, crtc);
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intel_plane_info(m, crtc);
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}
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@ -9135,8 +9135,7 @@ out:
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return active;
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}
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static u32 intel_cursor_base(struct intel_crtc *crtc,
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const struct intel_plane_state *plane_state)
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static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv =
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to_i915(plane_state->base.plane->dev);
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@ -9149,8 +9148,6 @@ static u32 intel_cursor_base(struct intel_crtc *crtc,
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else
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base = intel_plane_ggtt_offset(plane_state);
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crtc->cursor_addr = base;
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/* ILK+ do this automagically */
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if (HAS_GMCH_DISPLAY(dev_priv) &&
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plane_state->base.rotation & DRM_ROTATE_180)
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@ -9185,12 +9182,10 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
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CURSOR_STRIDE(stride);
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}
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static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
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static void i845_update_cursor(struct intel_plane *plane, u32 base,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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uint32_t cntl = 0, size = 0;
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if (plane_state && plane_state->base.visible) {
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@ -9201,32 +9196,32 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
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size = (height << 12) | width;
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}
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if (intel_crtc->cursor_cntl != 0 &&
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(intel_crtc->cursor_base != base ||
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intel_crtc->cursor_size != size ||
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intel_crtc->cursor_cntl != cntl)) {
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if (plane->cursor.cntl != 0 &&
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(plane->cursor.base != base ||
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plane->cursor.size != size ||
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plane->cursor.cntl != cntl)) {
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/* On these chipsets we can only modify the base/size/stride
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* whilst the cursor is disabled.
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*/
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I915_WRITE_FW(CURCNTR(PIPE_A), 0);
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POSTING_READ_FW(CURCNTR(PIPE_A));
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intel_crtc->cursor_cntl = 0;
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plane->cursor.cntl = 0;
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}
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if (intel_crtc->cursor_base != base) {
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if (plane->cursor.base != base) {
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I915_WRITE_FW(CURBASE(PIPE_A), base);
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intel_crtc->cursor_base = base;
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plane->cursor.base = base;
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}
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if (intel_crtc->cursor_size != size) {
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if (plane->cursor.size != size) {
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I915_WRITE_FW(CURSIZE, size);
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intel_crtc->cursor_size = size;
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plane->cursor.size = size;
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}
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if (intel_crtc->cursor_cntl != cntl) {
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if (plane->cursor.cntl != cntl) {
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I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
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POSTING_READ_FW(CURCNTR(PIPE_A));
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intel_crtc->cursor_cntl = cntl;
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plane->cursor.cntl = cntl;
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}
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}
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@ -9266,39 +9261,35 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
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return cntl;
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}
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static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
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static void i9xx_update_cursor(struct intel_plane *plane, u32 base,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum pipe pipe = plane->pipe;
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uint32_t cntl = 0;
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if (plane_state && plane_state->base.visible)
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cntl = plane_state->ctl;
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if (intel_crtc->cursor_cntl != cntl) {
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if (plane->cursor.cntl != cntl) {
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I915_WRITE_FW(CURCNTR(pipe), cntl);
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POSTING_READ_FW(CURCNTR(pipe));
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intel_crtc->cursor_cntl = cntl;
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plane->cursor.cntl = cntl;
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}
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/* and commit changes on next vblank */
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I915_WRITE_FW(CURBASE(pipe), base);
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POSTING_READ_FW(CURBASE(pipe));
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intel_crtc->cursor_base = base;
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plane->cursor.base = base;
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}
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/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
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static void intel_crtc_update_cursor(struct drm_crtc *crtc,
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static void intel_crtc_update_cursor(struct intel_plane *plane,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum pipe pipe = plane->pipe;
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u32 pos = 0, base = 0;
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unsigned long irqflags;
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@ -9318,9 +9309,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
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}
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pos |= y << CURSOR_Y_SHIFT;
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base = intel_cursor_base(intel_crtc, plane_state);
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} else {
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intel_crtc->cursor_addr = 0;
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base = intel_cursor_base(plane_state);
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}
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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@ -9328,9 +9317,9 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
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I915_WRITE_FW(CURPOS(pipe), pos);
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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i845_update_cursor(crtc, base, plane_state);
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i845_update_cursor(plane, base, plane_state);
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else
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i9xx_update_cursor(crtc, base, plane_state);
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i9xx_update_cursor(plane, base, plane_state);
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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@ -11892,7 +11881,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
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* allocation. In that case since the ddb allocation will be updated
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* once the plane becomes visible, we can skip this check
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*/
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if (intel_crtc->cursor_addr) {
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if (1) {
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hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
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sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
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@ -13734,7 +13723,7 @@ static void
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intel_disable_cursor_plane(struct intel_plane *plane,
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struct intel_crtc *crtc)
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{
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intel_crtc_update_cursor(&crtc->base, NULL);
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intel_crtc_update_cursor(plane, NULL);
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}
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static void
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@ -13742,9 +13731,7 @@ intel_update_cursor_plane(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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intel_crtc_update_cursor(&crtc->base, state);
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intel_crtc_update_cursor(plane, state);
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}
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static struct intel_plane *
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@ -13778,6 +13765,10 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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cursor->update_plane = intel_update_cursor_plane;
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cursor->disable_plane = intel_disable_cursor_plane;
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cursor->cursor.base = ~0;
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cursor->cursor.cntl = ~0;
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cursor->cursor.size = ~0;
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ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
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0, &intel_cursor_plane_funcs,
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intel_cursor_formats,
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@ -13885,10 +13876,6 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
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intel_crtc->pipe = pipe;
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intel_crtc->plane = primary->plane;
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intel_crtc->cursor_base = ~0;
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intel_crtc->cursor_cntl = ~0;
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intel_crtc->cursor_size = ~0;
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/* initialize shared scalers */
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intel_crtc_init_scalers(intel_crtc, crtc_state);
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@ -799,11 +799,6 @@ struct intel_crtc {
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int adjusted_x;
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int adjusted_y;
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uint32_t cursor_addr;
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uint32_t cursor_cntl;
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uint32_t cursor_size;
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uint32_t cursor_base;
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struct intel_crtc_state *config;
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/* global reset count when the last flip was submitted */
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@ -845,6 +840,10 @@ struct intel_plane {
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int max_downscale;
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uint32_t frontbuffer_bit;
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struct {
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u32 base, cntl, size;
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} cursor;
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/*
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* NOTE: Do not place new plane state fields here (e.g., when adding
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* new plane properties). New runtime state should now be placed in
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