[media] drxk_hard: Don't use CamelCase
X-Patchwork-Delegate: mchehab@redhat.com Thare are lots of CamelCase warnings produced by checkpatch.pl. This weren't fixed at the time the driver got submitted due to the lack of manpower do to such cleanup. Now that I have one script that automates this task, cleans it. That makes the driver almost checkpatch-compliant, except for 80 column warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
Родитель
b5e9eb6f52
Коммит
cd7a67a4f1
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@ -8,7 +8,7 @@
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/**
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* struct drxk_config - Configure the initial parameters for DRX-K
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*
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* @adr: I2C Address of the DRX-K
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* @adr: I2C address of the DRX-K
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* @parallel_ts: True means that the device uses parallel TS,
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* Serial otherwise.
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* @dynamic_clk: True means that the clock will be dynamically
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -46,7 +46,7 @@
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#define IQM_RC_ADJ_SEL_B_QAM 0x1
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#define IQM_RC_ADJ_SEL_B_VSB 0x2
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enum OperationMode {
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enum operation_mode {
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OM_NONE,
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OM_QAM_ITU_A,
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OM_QAM_ITU_B,
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@ -54,7 +54,7 @@ enum OperationMode {
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OM_DVBT
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};
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enum DRXPowerMode {
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enum drx_power_mode {
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DRX_POWER_UP = 0,
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DRX_POWER_MODE_1,
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DRX_POWER_MODE_2,
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@ -93,8 +93,8 @@ enum DRXPowerMode {
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#endif
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enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
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enum EDrxkState {
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enum agc_ctrl_mode { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
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enum e_drxk_state {
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DRXK_UNINITIALIZED = 0,
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DRXK_STOPPED,
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DRXK_DTV_STARTED,
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@ -103,7 +103,7 @@ enum EDrxkState {
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DRXK_NO_DEV /* If drxk init failed */
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};
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enum EDrxkCoefArrayIndex {
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enum e_drxk_coef_array_index {
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DRXK_COEF_IDX_MN = 0,
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DRXK_COEF_IDX_FM ,
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DRXK_COEF_IDX_L ,
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@ -113,13 +113,13 @@ enum EDrxkCoefArrayIndex {
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DRXK_COEF_IDX_I ,
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DRXK_COEF_IDX_MAX
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};
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enum EDrxkSifAttenuation {
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enum e_drxk_sif_attenuation {
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DRXK_SIF_ATTENUATION_0DB,
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DRXK_SIF_ATTENUATION_3DB,
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DRXK_SIF_ATTENUATION_6DB,
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DRXK_SIF_ATTENUATION_9DB
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};
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enum EDrxkConstellation {
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enum e_drxk_constellation {
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DRX_CONSTELLATION_BPSK = 0,
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DRX_CONSTELLATION_QPSK,
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DRX_CONSTELLATION_PSK8,
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@ -133,7 +133,7 @@ enum EDrxkConstellation {
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DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
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DRX_CONSTELLATION_AUTO = DRX_AUTO
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};
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enum EDrxkInterleaveMode {
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enum e_drxk_interleave_mode {
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DRXK_QAM_I12_J17 = 16,
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DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
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};
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@ -144,14 +144,14 @@ enum {
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DRXK_SPIN_UNKNOWN
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};
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enum DRXKCfgDvbtSqiSpeed {
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enum drxk_cfg_dvbt_sqi_speed {
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DRXK_DVBT_SQI_SPEED_FAST = 0,
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DRXK_DVBT_SQI_SPEED_MEDIUM,
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DRXK_DVBT_SQI_SPEED_SLOW,
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DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
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} ;
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enum DRXFftmode_t {
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enum drx_fftmode_t {
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DRX_FFTMODE_2K = 0,
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DRX_FFTMODE_4K,
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DRX_FFTMODE_8K,
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@ -159,40 +159,40 @@ enum DRXFftmode_t {
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DRX_FFTMODE_AUTO = DRX_AUTO
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};
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enum DRXMPEGStrWidth_t {
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enum drxmpeg_str_width_t {
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DRX_MPEG_STR_WIDTH_1,
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DRX_MPEG_STR_WIDTH_8
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};
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enum DRXQamLockRange_t {
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enum drx_qam_lock_range_t {
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DRX_QAM_LOCKRANGE_NORMAL,
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DRX_QAM_LOCKRANGE_EXTENDED
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};
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struct DRXKCfgDvbtEchoThres_t {
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struct drxk_cfg_dvbt_echo_thres_t {
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u16 threshold;
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enum DRXFftmode_t fftMode;
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enum drx_fftmode_t fft_mode;
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} ;
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struct SCfgAgc {
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enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
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u16 outputLevel; /* range dependent on AGC */
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u16 minOutputLevel; /* range dependent on AGC */
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u16 maxOutputLevel; /* range dependent on AGC */
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struct s_cfg_agc {
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enum agc_ctrl_mode ctrl_mode; /* off, user, auto */
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u16 output_level; /* range dependent on AGC */
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u16 min_output_level; /* range dependent on AGC */
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u16 max_output_level; /* range dependent on AGC */
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u16 speed; /* range dependent on AGC */
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u16 top; /* rf-agc take over point */
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u16 cutOffCurrent; /* rf-agc is accelerated if output current
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u16 cut_off_current; /* rf-agc is accelerated if output current
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is below cut-off current */
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u16 IngainTgtMax;
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u16 FastClipCtrlDelay;
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u16 ingain_tgt_max;
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u16 fast_clip_ctrl_delay;
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};
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struct SCfgPreSaw {
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struct s_cfg_pre_saw {
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u16 reference; /* pre SAW reference value, range 0 .. 31 */
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bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
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bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */
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};
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struct DRXKOfdmScCmd_t {
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struct drxk_ofdm_sc_cmd_t {
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u16 cmd; /**< Command number */
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u16 subcmd; /**< Sub-command parameter*/
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u16 param0; /**< General purpous param */
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@ -213,121 +213,121 @@ struct drxk_state {
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struct mutex mutex;
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u32 m_Instance; /**< Channel 1,2,3 or 4 */
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u32 m_instance; /**< Channel 1,2,3 or 4 */
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int m_ChunkSize;
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u8 Chunk[256];
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int m_chunk_size;
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u8 chunk[256];
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bool m_hasLNA;
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bool m_hasDVBT;
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bool m_hasDVBC;
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bool m_hasAudio;
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bool m_hasATV;
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bool m_hasOOB;
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bool m_hasSAWSW; /**< TRUE if mat_tx is available */
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bool m_hasGPIO1; /**< TRUE if mat_rx is available */
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bool m_hasGPIO2; /**< TRUE if GPIO is available */
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bool m_hasIRQN; /**< TRUE if IRQN is available */
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u16 m_oscClockFreq;
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u16 m_HICfgTimingDiv;
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u16 m_HICfgBridgeDelay;
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u16 m_HICfgWakeUpKey;
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u16 m_HICfgTimeout;
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u16 m_HICfgCtrl;
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s32 m_sysClockFreq; /**< system clock frequency in kHz */
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bool m_has_lna;
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bool m_has_dvbt;
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bool m_has_dvbc;
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bool m_has_audio;
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bool m_has_atv;
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bool m_has_oob;
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bool m_has_sawsw; /* TRUE if mat_tx is available */
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bool m_has_gpio1; /* TRUE if mat_rx is available */
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bool m_has_gpio2; /* TRUE if GPIO is available */
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bool m_has_irqn; /* TRUE if IRQN is available */
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u16 m_osc_clock_freq;
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u16 m_hi_cfg_timing_div;
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u16 m_hi_cfg_bridge_delay;
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u16 m_hi_cfg_wake_up_key;
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u16 m_hi_cfg_timeout;
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u16 m_hi_cfg_ctrl;
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s32 m_sys_clock_freq; /**< system clock frequency in kHz */
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enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
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enum OperationMode m_OperationMode; /**< digital standards */
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struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
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struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
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u16 m_vsbPgaCfg; /**< settings for VSB PGA */
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struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
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enum e_drxk_state m_drxk_state; /**< State of Drxk (init,stopped,started) */
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enum operation_mode m_operation_mode; /**< digital standards */
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struct s_cfg_agc m_vsb_rf_agc_cfg; /**< settings for VSB RF-AGC */
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struct s_cfg_agc m_vsb_if_agc_cfg; /**< settings for VSB IF-AGC */
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u16 m_vsb_pga_cfg; /**< settings for VSB PGA */
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struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /**< settings for pre SAW sense */
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s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
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s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
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bool m_smartAntInverted;
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bool m_bDebugEnableBridge;
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bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
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bool m_bPowerDown; /**< Power down when not used */
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bool m_smart_ant_inverted;
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bool m_b_debug_enable_bridge;
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bool m_b_p_down_open_bridge; /**< only open DRXK bridge before power-down once it has been accessed */
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bool m_b_power_down; /**< Power down when not used */
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u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
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u32 m_iqm_fs_rate_ofs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
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bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
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bool m_insertRSByte; /**< If TRUE, insert RS byte */
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bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
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bool m_invertDATA; /**< If TRUE, invert DATA signals */
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bool m_invertERR; /**< If TRUE, invert ERR signal */
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bool m_invertSTR; /**< If TRUE, invert STR signals */
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bool m_invertVAL; /**< If TRUE, invert VAL signals */
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bool m_invertCLK; /**< If TRUE, invert CLK signals */
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bool m_DVBCStaticCLK;
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bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
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bool m_enable_mpeg_output; /**< If TRUE, enable MPEG output */
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bool m_insert_rs_byte; /**< If TRUE, insert RS byte */
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bool m_enable_parallel; /**< If TRUE, parallel out otherwise serial */
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bool m_invert_data; /**< If TRUE, invert DATA signals */
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bool m_invert_err; /**< If TRUE, invert ERR signal */
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bool m_invert_str; /**< If TRUE, invert STR signals */
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bool m_invert_val; /**< If TRUE, invert VAL signals */
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bool m_invert_clk; /**< If TRUE, invert CLK signals */
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bool m_dvbc_static_clk;
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bool m_dvbt_static_clk; /**< If TRUE, static MPEG clockrate will
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be used, otherwise clockrate will
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adapt to the bitrate of the TS */
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u32 m_DVBTBitrate;
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u32 m_DVBCBitrate;
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u32 m_dvbt_bitrate;
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u32 m_dvbc_bitrate;
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u8 m_TSDataStrength;
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u8 m_TSClockkStrength;
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u8 m_ts_data_strength;
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u8 m_ts_clockk_strength;
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bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
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enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
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u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
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enum drxmpeg_str_width_t m_width_str; /**< MPEG start width */
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u32 m_mpeg_ts_static_bitrate; /**< Maximum bitrate in b/s in case
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static clockrate is selected */
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/* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */
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s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
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s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
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/* LARGE_INTEGER m_startTime; */ /**< Contains the time of the last demod start */
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s32 m_mpeg_lock_time_out; /**< WaitForLockStatus Timeout (counts from start time) */
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s32 m_demod_lock_time_out; /**< WaitForLockStatus Timeout (counts from start time) */
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bool m_disableTEIhandling;
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bool m_disable_te_ihandling;
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bool m_RfAgcPol;
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bool m_IfAgcPol;
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bool m_rf_agc_pol;
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bool m_if_agc_pol;
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struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
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struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
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struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
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bool m_phaseCorrectionBypass;
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s16 m_atvTopVidPeak;
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u16 m_atvTopNoiseTh;
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enum EDrxkSifAttenuation m_sifAttenuation;
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bool m_enableCVBSOutput;
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bool m_enableSIFOutput;
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bool m_bMirrorFreqSpect;
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enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
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u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
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struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
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struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
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u16 m_qamPgaCfg; /**< settings for QAM PGA */
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struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
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enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
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u16 m_fecRsPlen;
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u16 m_fecRsPrescale;
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struct s_cfg_agc m_atv_rf_agc_cfg; /**< settings for ATV RF-AGC */
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struct s_cfg_agc m_atv_if_agc_cfg; /**< settings for ATV IF-AGC */
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struct s_cfg_pre_saw m_atv_pre_saw_cfg; /**< settings for ATV pre SAW sense */
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bool m_phase_correction_bypass;
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s16 m_atv_top_vid_peak;
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u16 m_atv_top_noise_th;
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enum e_drxk_sif_attenuation m_sif_attenuation;
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bool m_enable_cvbs_output;
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bool m_enable_sif_output;
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bool m_b_mirror_freq_spect;
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enum e_drxk_constellation m_constellation; /**< constellation type of the channel */
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u32 m_curr_symbol_rate; /**< Current QAM symbol rate */
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struct s_cfg_agc m_qam_rf_agc_cfg; /**< settings for QAM RF-AGC */
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struct s_cfg_agc m_qam_if_agc_cfg; /**< settings for QAM IF-AGC */
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u16 m_qam_pga_cfg; /**< settings for QAM PGA */
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struct s_cfg_pre_saw m_qam_pre_saw_cfg; /**< settings for QAM pre SAW sense */
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enum e_drxk_interleave_mode m_qam_interleave_mode; /**< QAM Interleave mode */
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u16 m_fec_rs_plen;
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u16 m_fec_rs_prescale;
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enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
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enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
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u16 m_GPIO;
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u16 m_GPIOCfg;
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u16 m_gpio;
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u16 m_gpio_cfg;
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struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
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struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
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struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
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struct s_cfg_agc m_dvbt_rf_agc_cfg; /**< settings for QAM RF-AGC */
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struct s_cfg_agc m_dvbt_if_agc_cfg; /**< settings for QAM IF-AGC */
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struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /**< settings for QAM pre SAW sense */
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u16 m_agcFastClipCtrlDelay;
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bool m_adcCompPassed;
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u16 m_agcfast_clip_ctrl_delay;
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bool m_adc_comp_passed;
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u16 m_adcCompCoef[64];
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u16 m_adcState;
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u16 m_adc_state;
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u8 *m_microcode;
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int m_microcode_length;
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bool m_DRXK_A3_ROM_CODE;
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bool m_DRXK_A3_PATCH_CODE;
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bool m_drxk_a3_rom_code;
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bool m_drxk_a3_patch_code;
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bool m_rfmirror;
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u8 m_deviceSpin;
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u32 m_iqmRcRate;
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u8 m_device_spin;
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u32 m_iqm_rc_rate;
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enum DRXPowerMode m_currentPowerMode;
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enum drx_power_mode m_current_power_mode;
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/* when true, avoids other devices to use the I2C bus */
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bool drxk_i2c_exclusive_lock;
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@ -337,7 +337,7 @@ struct drxk_state {
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* at struct drxk_config.
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*/
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u16 UIO_mask; /* Bits used by UIO */
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u16 uio_mask; /* Bits used by UIO */
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|
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bool enable_merr_cfg;
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bool single_master;
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