drm/i915/icl: Add 10-bit support for hdmi
Starting Icelake silicon supports 10-bpc hdmi to support certain media workloads. Currently hdmi supports 8 and 12 bpc. Plumbed in support for 10 bit hdmi. Cc: James Ausmus <james.ausmus@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-18-paulo.r.zanoni@intel.com
This commit is contained in:
Radhakrishna Sripada
Paulo Zanoni
Родитель
c238ad6258
Коммит
cd9e11a8bf
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@ -1566,14 +1566,23 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
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/* check if we can do 8bpc */
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status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
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/* if we can't do 8bpc we may still be able to do 12bpc */
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if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
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status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
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if (hdmi->has_hdmi_sink && !force_dvi) {
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/* if we can't do 8bpc we may still be able to do 12bpc */
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if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
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status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
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true, force_dvi);
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/* if we can't do 8,12bpc we may still be able to do 10bpc */
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if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
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status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
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true, force_dvi);
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}
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return status;
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}
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static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
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static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
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int bpc)
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{
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struct drm_i915_private *dev_priv =
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to_i915(crtc_state->base.crtc->dev);
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@ -1585,6 +1594,9 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
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if (HAS_GMCH_DISPLAY(dev_priv))
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return false;
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if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
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return false;
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if (crtc_state->pipe_bpp <= 8*3)
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return false;
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@ -1592,7 +1604,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
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return false;
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/*
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* HDMI 12bpc affects the clocks, so it's only possible
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* HDMI deep color affects the clocks, so it's only possible
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* when not cloning with other encoder types.
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*/
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if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
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@ -1607,16 +1619,24 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
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if (crtc_state->ycbcr420) {
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const struct drm_hdmi_info *hdmi = &info->hdmi;
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if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
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if (bpc == 12 && !(hdmi->y420_dc_modes &
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DRM_EDID_YCBCR420_DC_36))
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return false;
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else if (bpc == 10 && !(hdmi->y420_dc_modes &
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DRM_EDID_YCBCR420_DC_30))
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return false;
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} else {
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if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
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if (bpc == 12 && !(info->edid_hdmi_dc_modes &
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DRM_EDID_HDMI_DC_36))
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return false;
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else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
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DRM_EDID_HDMI_DC_30))
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return false;
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}
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}
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/* Display WA #1139: glk */
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if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
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if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
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crtc_state->base.adjusted_mode.htotal > 5460)
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return false;
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@ -1626,7 +1646,8 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
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static bool
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intel_hdmi_ycbcr420_config(struct drm_connector *connector,
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struct intel_crtc_state *config,
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int *clock_12bpc, int *clock_8bpc)
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int *clock_12bpc, int *clock_10bpc,
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int *clock_8bpc)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
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@ -1638,6 +1659,7 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
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/* YCBCR420 TMDS rate requirement is half the pixel clock */
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config->port_clock /= 2;
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*clock_12bpc /= 2;
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*clock_10bpc /= 2;
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*clock_8bpc /= 2;
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config->ycbcr420 = true;
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@ -1665,6 +1687,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
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struct intel_digital_connector_state *intel_conn_state =
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to_intel_digital_connector_state(conn_state);
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int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
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int clock_10bpc = clock_8bpc * 5 / 4;
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int clock_12bpc = clock_8bpc * 3 / 2;
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int desired_bpp;
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bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
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@ -1691,12 +1714,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
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pipe_config->pixel_multiplier = 2;
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clock_8bpc *= 2;
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clock_10bpc *= 2;
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clock_12bpc *= 2;
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}
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if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
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if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
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&clock_12bpc, &clock_8bpc)) {
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&clock_12bpc, &clock_10bpc,
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&clock_8bpc)) {
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DRM_ERROR("Can't support YCBCR420 output\n");
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return false;
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}
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@ -1714,18 +1739,25 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
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}
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/*
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* HDMI is either 12 or 8, so if the display lets 10bpc sneak
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* through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
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* outputs. We also need to check that the higher clock still fits
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* within limits.
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* Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
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* to check that the higher clock still fits within limits.
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*/
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if (hdmi_12bpc_possible(pipe_config) &&
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hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) {
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if (hdmi_deep_color_possible(pipe_config, 12) &&
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hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
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true, force_dvi) == MODE_OK) {
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DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
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desired_bpp = 12*3;
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/* Need to adjust the port link by 1.5x for 12bpc. */
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pipe_config->port_clock = clock_12bpc;
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} else if (hdmi_deep_color_possible(pipe_config, 10) &&
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hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
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true, force_dvi) == MODE_OK) {
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DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
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desired_bpp = 10 * 3;
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/* Need to adjust the port link by 1.25x for 10bpc. */
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pipe_config->port_clock = clock_10bpc;
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} else {
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DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
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desired_bpp = 8*3;
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