ath9k_hw: Add initvals and register definitions for AR946/8x chipsets.
Add initvals and register modifications required to support AR946/8x chipsets. Signed-off-by: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Senthil Balasubramanian
John W. Linville
Родитель
910868db3f
Коммит
ce407afc10
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@ -581,6 +581,9 @@
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#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
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(AR_SREV_9485(ah) ? \
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0x3d0 : 0x450) + ((_i) << 2))
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#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
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#define AR_PHY_RTT_TABLE_SW_INTF_B (AR_SM_BASE + 0x384)
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#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 (AR_SM_BASE + 0x388)
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#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
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#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
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@ -600,6 +603,17 @@
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#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
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#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8
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/* AIC Registers */
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#define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
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#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
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#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
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#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
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#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \
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0x4c0 : 0x4c4))
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#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \
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0x4c4 : 0x4c8))
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#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
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#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
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#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
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#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
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@ -609,7 +623,10 @@
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#define AR_PHY_65NM_CH0_BIAS2 0x160c4
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#define AR_PHY_65NM_CH0_BIAS4 0x160cc
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#define AR_PHY_65NM_CH0_RXTX4 0x1610c
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#define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : 0x1628c)
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#define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\
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(AR_SREV_9485(ah) ? 0x1628c : 0x16294))
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#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
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#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
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@ -625,21 +642,23 @@
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#define AR_PHY_65NM_CH2_RXTX1 0x16900
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#define AR_PHY_65NM_CH2_RXTX2 0x16904
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#define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : 0x16284)
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#define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \
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(AR_SREV_9485(ah) ? 0x16284 : 0x16290))
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#define AR_CH0_TOP2_XPABIASLVL 0xf000
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#define AR_CH0_TOP2_XPABIASLVL_S 12
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#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : 0x16290)
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#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \
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(AR_SREV_9485(ah) ? 0x16290 : 0x16298))
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#define AR_CH0_XTAL_CAPINDAC 0x7f000000
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#define AR_CH0_XTAL_CAPINDAC_S 24
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#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
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#define AR_CH0_XTAL_CAPOUTDAC_S 17
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#define AR_PHY_PMU1 0x16c40
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#define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40)
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#define AR_PHY_PMU1_PWD 0x1
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#define AR_PHY_PMU1_PWD_S 0
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#define AR_PHY_PMU2 0x16c44
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#define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44)
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#define AR_PHY_PMU2_PGM 0x00200000
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#define AR_PHY_PMU2_PGM_S 21
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@ -839,19 +858,38 @@
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*/
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#define AR_SM1_BASE 0xb200
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#define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
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#define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
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#define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
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#define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
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#define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
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#define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
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#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
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#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
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#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
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#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
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#define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
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#define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
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#define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
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#define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
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#define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
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#define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
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#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
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#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
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#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
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#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_AR9300(ah) ? \
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0x240 : 0x280))
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#define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240)
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#define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff
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#define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0
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#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
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#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM_BASE + 0x450 + ((_i) << 2))
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/* SM 1 AIC Registers */
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#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
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#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
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#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
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#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \
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0x4c0 : 0x4c4))
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#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \
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0x4c4 : 0x4c8))
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#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
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#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
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#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
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#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
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/*
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* Channel 2 Register Map
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*/
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@ -914,6 +952,13 @@
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#define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180)
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/* GLB Registers */
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#define AR_GLB_BASE 0x20000
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#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
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#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
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(AR_SREV_9480_20(_ah) ? 0x4c : 0x50))
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#define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
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/*
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* Misc helper defines
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*/
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@ -46,6 +46,7 @@
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#define AR9300_DEVID_AR9340 0x0031
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#define AR9300_DEVID_AR9485_PCIE 0x0032
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#define AR9300_DEVID_AR9580 0x0033
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#define AR9300_DEVID_AR9480 0x0034
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#define AR9300_DEVID_AR9330 0x0035
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#define AR5416_AR9100_DEVID 0x000b
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@ -827,11 +828,14 @@ struct ath_hw {
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struct ar5416IniArray iniModes_9271_1_0_only;
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struct ar5416IniArray iniCckfirNormal;
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struct ar5416IniArray iniCckfirJapan2484;
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struct ar5416IniArray ini_japan2484;
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struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
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struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
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struct ar5416IniArray iniModes_9271_ANI_reg;
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struct ar5416IniArray iniModes_high_power_tx_gain_9271;
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struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
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struct ar5416IniArray ini_radio_post_sys2ant;
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struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
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struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
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struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
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@ -644,6 +644,7 @@ enum ath9k_rx_filter {
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ATH9K_RX_FILTER_PSPOLL = 0x00004000,
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ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
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ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
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ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,
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};
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#define ATH9K_RATESERIES_RTS_CTS 0x0001
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@ -796,6 +796,9 @@
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#define AR_SREV_VERSION_9340 0x300
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#define AR_SREV_VERSION_9580 0x1C0
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#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
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#define AR_SREV_VERSION_9480 0x280
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#define AR_SREV_REVISION_9480_10 0
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#define AR_SREV_REVISION_9480_20 2
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#define AR_SREV_5416(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
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@ -896,6 +899,21 @@
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(AR_SREV_9285_12_OR_LATER(_ah) && \
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((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
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#define AR_SREV_9480(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480))
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#define AR_SREV_9480_10(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \
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((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_10))
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#define AR_SREV_9480_20(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \
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((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_20))
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#define AR_SREV_9480_20_OR_LATER(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \
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((_ah)->hw_version.macRev >= AR_SREV_REVISION_9480_20))
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#define AR_SREV_9580(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
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((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))
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@ -1779,6 +1797,7 @@ enum {
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#define AR_TXOP_12_15 0x81fc
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#define AR_NEXT_NDP2_TIMER 0x8180
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#define AR_GEN_TIMER_BANK_1_LEN 8
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#define AR_FIRST_NDP_TIMER 7
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#define AR_NDP2_PERIOD 0x81a0
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#define AR_NDP2_TIMER_MODE 0x81c0
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#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000
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#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000
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#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358
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#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400
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#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000
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#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358
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#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400
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#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000
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#define AR_MAC_PCU_GEN_TIMER_TSF_SEL 0x83d8
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#define AR_AES_MUTE_MASK0 0x805c
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@ -1920,4 +1940,38 @@ enum {
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#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
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#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
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/* MCI Registers */
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#define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c
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#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
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#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0
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#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
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#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4
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#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
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#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5
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#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
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#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6
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#define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
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#define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8
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#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
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#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9
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#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
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#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10
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#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
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#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11
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#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
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#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12
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#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \
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AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \
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AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
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AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
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AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
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AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
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#endif
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