net: aquantia: fixups on 64bit dma counters
DMA counters are 64 bit and we can fetch that to reduce counter overflow, espesially on byte counters. Tested-by: Nikita Danilov <ndanilov@aquantia.com> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: Dmitry Bogdanov <dmitry.bogdanov@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Коммит
ce4cdbe44c
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@ -53,6 +53,18 @@ void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)
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writel(value, hw->mmio + reg);
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}
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/* Most of 64-bit registers are in LSW, MSW form.
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Counters are normally implemented by HW as latched pairs:
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reading LSW first locks MSW, to overcome LSW overflow
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*/
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u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg)
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{
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u64 value = aq_hw_read_reg(hw, reg);
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value |= (u64)aq_hw_read_reg(hw, reg + 4) << 32;
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return value;
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}
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int aq_hw_err_from_flags(struct aq_hw_s *hw)
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{
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int err = 0;
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@ -35,6 +35,7 @@ void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
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u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift);
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u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);
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void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);
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u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg);
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int aq_hw_err_from_flags(struct aq_hw_s *hw);
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#endif /* AQ_HW_UTILS_H */
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@ -49,11 +49,6 @@ u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
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HW_ATL_GLB_SOFT_RES_SHIFT);
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}
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u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR);
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}
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u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
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@ -65,44 +60,24 @@ u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
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return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
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}
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u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
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u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
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return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
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}
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u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
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u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
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return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
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}
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u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
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u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
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return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
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}
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u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
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u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
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}
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u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
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}
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u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
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}
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u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
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}
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u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
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return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
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}
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/* interrupt */
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@ -40,29 +40,17 @@ u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw);
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u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
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/* get rx dma good octet counter lsw */
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u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
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/* get rx dma good octet counter */
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u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw);
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/* get rx dma good packet counter lsw */
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u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
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/* get rx dma good packet counter */
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u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw);
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/* get tx dma good octet counter lsw */
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u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
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/* get tx dma good octet counter */
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u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw);
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/* get tx dma good packet counter lsw */
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u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
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/* get rx dma good octet counter msw */
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u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
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/* get rx dma good packet counter msw */
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u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
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/* get tx dma good octet counter msw */
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u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
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/* get tx dma good packet counter msw */
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u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
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/* get tx dma good packet counter */
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u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw);
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/* get msm rx errors counter register */
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u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
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@ -82,9 +70,6 @@ u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
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/* get msm rx unicast octets counter register 0 */
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u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
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/* get rx dma statistics counter 7 */
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u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
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/* get msm tx errors counter register */
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u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
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@ -58,9 +58,6 @@
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/* preprocessor definitions for msm rx unicast octets counter register 0 */
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#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u
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/* preprocessor definitions for rx dma statistics counter 7 */
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#define HW_ATL_RX_DMA_STAT_COUNTER7_ADR 0x00006818u
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/* preprocessor definitions for msm tx unicast frames counter register */
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#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u
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@ -545,7 +545,7 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
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pmbox->stats.ubtc = pmbox->stats.uptc * mtu;
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pmbox->stats.dpc = atomic_read(&self->dpc);
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} else {
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pmbox->stats.dpc = hw_atl_reg_rx_dma_stat_counter7get(self);
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pmbox->stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self);
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}
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err_exit:;
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@ -763,6 +763,7 @@ static int hw_atl_fw1x_deinit(struct aq_hw_s *self)
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int hw_atl_utils_update_stats(struct aq_hw_s *self)
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{
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struct hw_atl_utils_mbox mbox;
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struct aq_stats_s *cs = &self->curr_stats;
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hw_atl_utils_mpi_read_stats(self, &mbox);
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@ -789,10 +790,11 @@ int hw_atl_utils_update_stats(struct aq_hw_s *self)
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AQ_SDELTA(dpc);
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}
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#undef AQ_SDELTA
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self->curr_stats.dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self);
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self->curr_stats.dma_pkt_tc = hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self);
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self->curr_stats.dma_oct_rc = hw_atl_stats_rx_dma_good_octet_counterlsw_get(self);
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self->curr_stats.dma_oct_tc = hw_atl_stats_tx_dma_good_octet_counterlsw_get(self);
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cs->dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counter_get(self);
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cs->dma_pkt_tc = hw_atl_stats_tx_dma_good_pkt_counter_get(self);
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cs->dma_oct_rc = hw_atl_stats_rx_dma_good_octet_counter_get(self);
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cs->dma_oct_tc = hw_atl_stats_tx_dma_good_octet_counter_get(self);
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memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats));
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