dt-bindings: timer: Tegra: Convert text bindings to yaml
Convert Tegra timer binding into yaml format. This commit also merge 3 text bindings with almost identical content (differens in number of registers). Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20220303233307.61753-1-david@ixit.cz Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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David Heidelberg
Daniel Lezcano
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Коммит
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra timer
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maintainers:
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- Stephen Warren <swarren@nvidia.com>
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra210-timer
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then:
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properties:
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interrupts:
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# Either a single combined interrupt or up to 14 individual interrupts
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minItems: 1
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maxItems: 14
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description: >
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A list of 14 interrupts; one per each timer channels 0 through 13
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- if:
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- nvidia,tegra114-timer
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- nvidia,tegra124-timer
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- nvidia,tegra132-timer
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- const: nvidia,tegra30-timer
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- items:
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- const: nvidia,tegra30-timer
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- const: nvidia,tegra20-timer
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then:
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properties:
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interrupts:
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# Either a single combined interrupt or up to 6 individual interrupts
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minItems: 1
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maxItems: 6
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description: >
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A list of 6 interrupts; one per each of timer channels 1 through 5,
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and one for the shared interrupt for the remaining channels.
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- if:
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properties:
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compatible:
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const: nvidia,tegra20-timer
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then:
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properties:
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interrupts:
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# Either a single combined interrupt or up to 4 individual interrupts
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minItems: 1
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maxItems: 4
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description: |
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A list of 4 interrupts; one per timer channel.
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properties:
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compatible:
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oneOf:
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- const: nvidia,tegra210-timer
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description: >
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The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
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timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
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from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
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(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
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or watchdog interrupts.
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- items:
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- enum:
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- nvidia,tegra114-timer
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- nvidia,tegra124-timer
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- nvidia,tegra132-timer
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- const: nvidia,tegra30-timer
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- items:
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- const: nvidia,tegra30-timer
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- const: nvidia,tegra20-timer
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description: >
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The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
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running counter, and 5 watchdog modules. The first two channels may also
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trigger a legacy watchdog reset.
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- const: nvidia,tegra20-timer
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description: >
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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reg:
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maxItems: 1
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interrupts: true
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: timer
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@60005000 {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 42 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car 214>;
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};
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@60005000 {
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compatible = "nvidia,tegra210-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_TIMER>;
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clock-names = "timer";
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};
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@ -1,24 +0,0 @@
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NVIDIA Tegra20 timer
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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Example:
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timer {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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clocks = <&tegra_car 132>;
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};
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@ -1,36 +0,0 @@
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NVIDIA Tegra210 timer
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The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
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timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
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from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
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(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
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or watchdog interrupts.
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Required properties:
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- compatible : "nvidia,tegra210-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 14 interrupts; one per each timer channels 0 through
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13.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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timer@60005000 {
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compatible = "nvidia,tegra210-timer";
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reg = <0x0 0x60005000 0x0 0x400>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_TIMER>;
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clock-names = "timer";
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};
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@ -1,28 +0,0 @@
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NVIDIA Tegra30 timer
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The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
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running counter, and 5 watchdog modules. The first two channels may also
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trigger a legacy watchdog reset.
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Required properties:
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- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
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must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
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<chip> is tegra124 or tegra132.
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
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through 5, and one for the shared interrupt for the remaining channels.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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timer {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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clocks = <&tegra_car 214>;
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};
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