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Merge branch 'omap_chip_remove_cleanup_3.2' of git://git.pwsan.com/linux-2.6 into cleanup

This commit is contained in:
Tony Lindgren 2011-09-15 16:06:11 -07:00
Родитель 8f5b5a41eb 00c46b3069
Коммит ceb1c532ba
373 изменённых файлов: 4331 добавлений и 3607 удалений
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116
Documentation/networking/00-INDEX
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@ -1,13 +1,21 @@
00-INDEX
- this file
3c359.txt
- information on the 3Com TokenLink Velocity XL (3c5359) driver.
3c505.txt
- information on the 3Com EtherLink Plus (3c505) driver.
3c509.txt
- information on the 3Com Etherlink III Series Ethernet cards.
6pack.txt
- info on the 6pack protocol, an alternative to KISS for AX.25
DLINK.txt
- info on the D-Link DE-600/DE-620 parallel port pocket adapters
PLIP.txt
- PLIP: The Parallel Line Internet Protocol device driver
README.ipw2100
- README for the Intel PRO/Wireless 2100 driver.
README.ipw2200
- README for the Intel PRO/Wireless 2915ABG and 2200BG driver.
README.sb1000
- info on General Instrument/NextLevel SURFboard1000 cable modem.
alias.txt
@ -20,8 +28,12 @@ atm.txt
- info on where to get ATM programs and support for Linux.
ax25.txt
- info on using AX.25 and NET/ROM code for Linux
batman-adv.txt
- B.A.T.M.A.N routing protocol on top of layer 2 Ethernet Frames.
baycom.txt
- info on the driver for Baycom style amateur radio modems
bonding.txt
- Linux Ethernet Bonding Driver HOWTO: link aggregation in Linux.
bridge.txt
- where to get user space programs for ethernet bridging with Linux.
can.txt
@ -34,32 +46,60 @@ cxacru.txt
- Conexant AccessRunner USB ADSL Modem
cxacru-cf.py
- Conexant AccessRunner USB ADSL Modem configuration file parser
cxgb.txt
- Release Notes for the Chelsio N210 Linux device driver.
dccp.txt
- the Datagram Congestion Control Protocol (DCCP) (RFC 4340..42).
de4x5.txt
- the Digital EtherWORKS DE4?? and DE5?? PCI Ethernet driver
decnet.txt
- info on using the DECnet networking layer in Linux.
depca.txt
- the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
dl2k.txt
- README for D-Link DL2000-based Gigabit Ethernet Adapters (dl2k.ko).
dm9000.txt
- README for the Simtec DM9000 Network driver.
dmfe.txt
- info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
dns_resolver.txt
- The DNS resolver module allows kernel servies to make DNS queries.
driver.txt
- Softnet driver issues.
e100.txt
- info on Intel's EtherExpress PRO/100 line of 10/100 boards
e1000.txt
- info on Intel's E1000 line of gigabit ethernet boards
e1000e.txt
- README for the Intel Gigabit Ethernet Driver (e1000e).
eql.txt
- serial IP load balancing
ewrk3.txt
- the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
fib_trie.txt
- Level Compressed Trie (LC-trie) notes: a structure for routing.
filter.txt
- Linux Socket Filtering
fore200e.txt
- FORE Systems PCA-200E/SBA-200E ATM NIC driver info.
framerelay.txt
- info on using Frame Relay/Data Link Connection Identifier (DLCI).
gen_stats.txt
- Generic networking statistics for netlink users.
generic_hdlc.txt
- The generic High Level Data Link Control (HDLC) layer.
generic_netlink.txt
- info on Generic Netlink
gianfar.txt
- Gianfar Ethernet Driver.
ieee802154.txt
- Linux IEEE 802.15.4 implementation, API and drivers
ifenslave.c
- Configure network interfaces for parallel routing (bonding).
igb.txt
- README for the Intel Gigabit Ethernet Driver (igb).
igbvf.txt
- README for the Intel Gigabit Ethernet Driver (igbvf).
ip-sysctl.txt
- /proc/sys/net/ipv4/* variables
ip_dynaddr.txt
@ -68,41 +108,117 @@ ipddp.txt
- AppleTalk-IP Decapsulation and AppleTalk-IP Encapsulation
iphase.txt
- Interphase PCI ATM (i)Chip IA Linux driver info.
ipv6.txt
- Options to the ipv6 kernel module.
ipvs-sysctl.txt
- Per-inode explanation of the /proc/sys/net/ipv4/vs interface.
irda.txt
- where to get IrDA (infrared) utilities and info for Linux.
ixgb.txt
- README for the Intel 10 Gigabit Ethernet Driver (ixgb).
ixgbe.txt
- README for the Intel 10 Gigabit Ethernet Driver (ixgbe).
ixgbevf.txt
- README for the Intel Virtual Function (VF) Driver (ixgbevf).
l2tp.txt
- User guide to the L2TP tunnel protocol.
lapb-module.txt
- programming information of the LAPB module.
ltpc.txt
- the Apple or Farallon LocalTalk PC card driver
mac80211-injection.txt
- HOWTO use packet injection with mac80211
multicast.txt
- Behaviour of cards under Multicast
multiqueue.txt
- HOWTO for multiqueue network device support.
netconsole.txt
- The network console module netconsole.ko: configuration and notes.
netdev-features.txt
- Network interface features API description.
netdevices.txt
- info on network device driver functions exported to the kernel.
netif-msg.txt
- Design of the network interface message level setting (NETIF_MSG_*).
nfc.txt
- The Linux Near Field Communication (NFS) subsystem.
olympic.txt
- IBM PCI Pit/Pit-Phy/Olympic Token Ring driver info.
operstates.txt
- Overview of network interface operational states.
packet_mmap.txt
- User guide to memory mapped packet socket rings (PACKET_[RT]X_RING).
phonet.txt
- The Phonet packet protocol used in Nokia cellular modems.
phy.txt
- The PHY abstraction layer.
pktgen.txt
- User guide to the kernel packet generator (pktgen.ko).
policy-routing.txt
- IP policy-based routing
ppp_generic.txt
- Information about the generic PPP driver.
proc_net_tcp.txt
- Per inode overview of the /proc/net/tcp and /proc/net/tcp6 interfaces.
radiotap-headers.txt
- Background on radiotap headers.
ray_cs.txt
- Raylink Wireless LAN card driver info.
rds.txt
- Background on the reliable, ordered datagram delivery method RDS.
regulatory.txt
- Overview of the Linux wireless regulatory infrastructure.
rxrpc.txt
- Guide to the RxRPC protocol.
s2io.txt
- Release notes for Neterion Xframe I/II 10GbE driver.
scaling.txt
- Explanation of network scaling techniques: RSS, RPS, RFS, aRFS, XPS.
sctp.txt
- Notes on the Linux kernel implementation of the SCTP protocol.
secid.txt
- Explanation of the secid member in flow structures.
skfp.txt
- SysKonnect FDDI (SK-5xxx, Compaq Netelligent) driver info.
smc9.txt
- the driver for SMC's 9000 series of Ethernet cards
smctr.txt
- SMC TokenCard TokenRing Linux driver info.
spider-net.txt
- README for the Spidernet Driver (as found in PS3 / Cell BE).
stmmac.txt
- README for the STMicro Synopsys Ethernet driver.
tc-actions-env-rules.txt
- rules for traffic control (tc) actions.
timestamping.txt
- overview of network packet timestamping variants.
tcp.txt
- short blurb on how TCP output takes place.
tcp-thin.txt
- kernel tuning options for low rate 'thin' TCP streams.
tlan.txt
- ThunderLAN (Compaq Netelligent 10/100, Olicom OC-2xxx) driver info.
tms380tr.txt
- SysKonnect Token Ring ISA/PCI adapter driver info.
tproxy.txt
- Transparent proxy support user guide.
tuntap.txt
- TUN/TAP device driver, allowing user space Rx/Tx of packets.
udplite.txt
- UDP-Lite protocol (RFC 3828) introduction.
vortex.txt
- info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
vxge.txt
- README for the Neterion X3100 PCIe Server Adapter.
x25.txt
- general info on X.25 development.
x25-iface.txt
- description of the X.25 Packet Layer to LAPB device interface.
xfrm_proc.txt
- description of the statistics package for XFRM.
xfrm_sync.txt
- sync patches for XFRM enable migration of an SA between hosts.
xfrm_sysctl.txt
- description of the XFRM configuration options.
z8530drv.txt
- info about Linux driver for Z8530 based HDLC cards for AX.25

2
Documentation/networking/ip-sysctl.txt
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@ -992,7 +992,7 @@ bindv6only - BOOLEAN
TRUE: disable IPv4-mapped address feature
FALSE: enable IPv4-mapped address feature
Default: FALSE (as specified in RFC2553bis)
Default: FALSE (as specified in RFC3493)
IPv6 Fragmentation:

23
Documentation/networking/scaling.txt
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@ -52,7 +52,8 @@ module parameter for specifying the number of hardware queues to
configure. In the bnx2x driver, for instance, this parameter is called
num_queues. A typical RSS configuration would be to have one receive queue
for each CPU if the device supports enough queues, or otherwise at least
one for each cache domain at a particular cache level (L1, L2, etc.).
one for each memory domain, where a memory domain is a set of CPUs that
share a particular memory level (L1, L2, NUMA node, etc.).
The indirection table of an RSS device, which resolves a queue by masked
hash, is usually programmed by the driver at initialization. The
@ -82,11 +83,17 @@ RSS should be enabled when latency is a concern or whenever receive
interrupt processing forms a bottleneck. Spreading load between CPUs
decreases queue length. For low latency networking, the optimal setting
is to allocate as many queues as there are CPUs in the system (or the
NIC maximum, if lower). Because the aggregate number of interrupts grows
with each additional queue, the most efficient high-rate configuration
NIC maximum, if lower). The most efficient high-rate configuration
is likely the one with the smallest number of receive queues where no
CPU that processes receive interrupts reaches 100% utilization. Per-cpu
load can be observed using the mpstat utility.
receive queue overflows due to a saturated CPU, because in default
mode with interrupt coalescing enabled, the aggregate number of
interrupts (and thus work) grows with each additional queue.
Per-cpu load can be observed using the mpstat utility, but note that on
processors with hyperthreading (HT), each hyperthread is represented as
a separate CPU. For interrupt handling, HT has shown no benefit in
initial tests, so limit the number of queues to the number of CPU cores
in the system.
RPS: Receive Packet Steering
@ -145,7 +152,7 @@ the bitmap.
== Suggested Configuration
For a single queue device, a typical RPS configuration would be to set
the rps_cpus to the CPUs in the same cache domain of the interrupting
the rps_cpus to the CPUs in the same memory domain of the interrupting
CPU. If NUMA locality is not an issue, this could also be all CPUs in
the system. At high interrupt rate, it might be wise to exclude the
interrupting CPU from the map since that already performs much work.
@ -154,7 +161,7 @@ For a multi-queue system, if RSS is configured so that a hardware
receive queue is mapped to each CPU, then RPS is probably redundant
and unnecessary. If there are fewer hardware queues than CPUs, then
RPS might be beneficial if the rps_cpus for each queue are the ones that
share the same cache domain as the interrupting CPU for that queue.
share the same memory domain as the interrupting CPU for that queue.
RFS: Receive Flow Steering
@ -326,7 +333,7 @@ The queue chosen for transmitting a particular flow is saved in the
corresponding socket structure for the flow (e.g. a TCP connection).
This transmit queue is used for subsequent packets sent on the flow to
prevent out of order (ooo) packets. The choice also amortizes the cost
of calling get_xps_queues() over all packets in the connection. To avoid
of calling get_xps_queues() over all packets in the flow. To avoid
ooo packets, the queue for a flow can subsequently only be changed if
skb->ooo_okay is set for a packet in the flow. This flag indicates that
there are no outstanding packets in the flow, so the transmit queue can

3
Documentation/power/runtime_pm.txt
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@ -431,8 +431,7 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
void pm_runtime_irq_safe(struct device *dev);
- set the power.irq_safe flag for the device, causing the runtime-PM
suspend and resume callbacks (but not the idle callback) to be invoked
with interrupts disabled
callbacks to be invoked with interrupts off
void pm_runtime_mark_last_busy(struct device *dev);
- set the power.last_busy field to the current time

7
MAINTAINERS
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@ -1883,7 +1883,7 @@ S: Maintained
F: drivers/connector/
CONTROL GROUPS (CGROUPS)
M: Paul Menage <menage@google.com>
M: Paul Menage <paul@paulmenage.org>
M: Li Zefan <lizf@cn.fujitsu.com>
L: containers@lists.linux-foundation.org
S: Maintained
@ -1932,7 +1932,7 @@ S: Maintained
F: tools/power/cpupower
CPUSETS
M: Paul Menage <menage@google.com>
M: Paul Menage <paul@paulmenage.org>
W: http://www.bullopensource.org/cpuset/
W: http://oss.sgi.com/projects/cpusets/
S: Supported
@ -5532,6 +5532,7 @@ F: include/media/*7146*
SAMSUNG AUDIO (ASoC) DRIVERS
M: Jassi Brar <jassisinghbrar@gmail.com>
M: Sangbeom Kim <sbkim73@samsung.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Supported
F: sound/soc/samsung
@ -7087,7 +7088,7 @@ S: Supported
F: drivers/mmc/host/vub300.c
W1 DALLAS'S 1-WIRE BUS
M: Evgeniy Polyakov <johnpol@2ka.mipt.ru>
M: Evgeniy Polyakov <zbr@ioremap.net>
S: Maintained
F: Documentation/w1/
F: drivers/w1/

2
Makefile
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@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 1
SUBLEVEL = 0
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME = "Divemaster Edition"
# *DOCUMENTATION*

9
arch/alpha/include/asm/sysinfo.h
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@ -27,13 +27,4 @@
#define UAC_NOFIX 2
#define UAC_SIGBUS 4
#ifdef __KERNEL__
/* This is the shift that is applied to the UAC bits as stored in the
per-thread flags. See thread_info.h. */
#define UAC_SHIFT 6
#endif
#endif /* __ASM_ALPHA_SYSINFO_H */

8
arch/alpha/include/asm/thread_info.h
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@ -74,9 +74,9 @@ register struct thread_info *__current_thread_info __asm__("$8");
#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
#define TIF_POLLING_NRFLAG 8 /* poll_idle is polling NEED_RESCHED */
#define TIF_DIE_IF_KERNEL 9 /* dik recursion lock */
#define TIF_UAC_NOPRINT 10 /* see sysinfo.h */
#define TIF_UAC_NOFIX 11
#define TIF_UAC_SIGBUS 12
#define TIF_UAC_NOPRINT 10 /* ! Preserve sequence of following */
#define TIF_UAC_NOFIX 11 /* ! flags as they match */
#define TIF_UAC_SIGBUS 12 /* ! userspace part of 'osf_sysinfo' */
#define TIF_MEMDIE 13 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 14 /* restore signal mask in do_signal */
#define TIF_FREEZE 16 /* is freezing for suspend */
@ -97,7 +97,7 @@ register struct thread_info *__current_thread_info __asm__("$8");
#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK \
| _TIF_SYSCALL_TRACE)
#define ALPHA_UAC_SHIFT 10
#define ALPHA_UAC_SHIFT TIF_UAC_NOPRINT
#define ALPHA_UAC_MASK (1 << TIF_UAC_NOPRINT | 1 << TIF_UAC_NOFIX | \
1 << TIF_UAC_SIGBUS)

12
arch/alpha/kernel/osf_sys.c
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@ -42,6 +42,7 @@
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/sysinfo.h>
#include <asm/thread_info.h>
#include <asm/hwrpb.h>
#include <asm/processor.h>
@ -633,9 +634,10 @@ SYSCALL_DEFINE5(osf_getsysinfo, unsigned long, op, void __user *, buffer,
case GSI_UACPROC:
if (nbytes < sizeof(unsigned int))
return -EINVAL;
w = (current_thread_info()->flags >> UAC_SHIFT) & UAC_BITMASK;
if (put_user(w, (unsigned int __user *)buffer))
return -EFAULT;
w = (current_thread_info()->flags >> ALPHA_UAC_SHIFT) &
UAC_BITMASK;
if (put_user(w, (unsigned int __user *)buffer))
return -EFAULT;
return 1;
case GSI_PROC_TYPE:
@ -756,8 +758,8 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer,
case SSIN_UACPROC:
again:
old = current_thread_info()->flags;
new = old & ~(UAC_BITMASK << UAC_SHIFT);
new = new | (w & UAC_BITMASK) << UAC_SHIFT;
new = old & ~(UAC_BITMASK << ALPHA_UAC_SHIFT);
new = new | (w & UAC_BITMASK) << ALPHA_UAC_SHIFT;
if (cmpxchg(&current_thread_info()->flags,
old, new) != old)
goto again;

2
arch/alpha/kernel/systbls.S
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@ -360,7 +360,7 @@ sys_call_table:
.quad sys_newuname
.quad sys_nanosleep /* 340 */
.quad sys_mremap
.quad sys_nfsservctl
.quad sys_ni_syscall /* old nfsservctl */
.quad sys_setresuid
.quad sys_getresuid
.quad sys_pciconfig_read /* 345 */

2
arch/arm/kernel/calls.S
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@ -178,7 +178,7 @@
CALL(sys_ni_syscall) /* vm86 */
CALL(sys_ni_syscall) /* was sys_query_module */
CALL(sys_poll)
CALL(sys_nfsservctl)
CALL(sys_ni_syscall) /* was nfsservctl */
/* 170 */ CALL(sys_setresgid16)
CALL(sys_getresgid16)
CALL(sys_prctl)

5
arch/arm/mach-omap2/Makefile
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@ -116,9 +116,12 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
clockdomains2xxx_3xxx_data.o \
clockdomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o

13
arch/arm/mach-omap2/clock3xxx_data.c
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@ -3078,6 +3078,7 @@ static struct clk gpt12_fck = {
.name = "gpt12_fck",
.ops = &clkops_null,
.parent = &secure_32k_fck,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
@ -3085,6 +3086,7 @@ static struct clk wdt1_fck = {
.name = "wdt1_fck",
.ops = &clkops_null,
.parent = &secure_32k_fck,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
@ -3470,7 +3472,16 @@ int __init omap3xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg = 0;
if (cpu_is_omap3517()) {
/*
* 3505 must be tested before 3517, since 3517 returns true
* for both AM3517 chips and AM3517 family chips, which
* includes 3505. Unfortunately there's no obvious family
* test for 3517/3505 :-(
*/
if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_3505;
} else if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_3517;
} else if (cpu_is_omap3505()) {

10
arch/arm/mach-omap2/clock44xx_data.c
Просмотреть файл

@ -3376,10 +3376,18 @@ int __init omap4xxx_clk_init(void)
} else if (cpu_is_omap446x()) {
cpu_mask = RATE_IN_4460;
cpu_clkflg = CK_446X;
} else {
return 0;
}
clk_init(&omap2_clk_functions);
omap2_clk_disable_clkdm_control();
/*
* Must stay commented until all OMAP SoC drivers are
* converted to runtime PM, or drivers may start crashing
*
* omap2_clk_disable_clkdm_control();
*/
for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
c++)

149
arch/arm/mach-omap2/clockdomain.c
Просмотреть файл

@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
if (!clkdm || !clkdm->name)
return -EINVAL;
if (!omap_chip_is(clkdm->omap_chip))
return -EINVAL;
pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
if (!pwrdm) {
pr_err("clockdomain: %s: powerdomain %s does not exist\n",
@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
{
struct clkdm_dep *cd;
if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
if (!clkdm || !deps)
return ERR_PTR(-EINVAL);
for (cd = deps; cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm && cd->clkdm_name)
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
if (!autodep)
return;
if (!omap_chip_is(autodep->omap_chip))
return;
clkdm = clkdm_lookup(autodep->clkdm.name);
if (!clkdm) {
pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
if (IS_ERR(autodep->clkdm.ptr))
continue;
if (!omap_chip_is(autodep->omap_chip))
continue;
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
"clkdm %s\n", autodep->clkdm.ptr->name,
clkdm->name);
@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
if (IS_ERR(autodep->clkdm.ptr))
continue;
if (!omap_chip_is(autodep->omap_chip))
continue;
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
"clkdm %s\n", autodep->clkdm.ptr->name,
clkdm->name);
@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
struct clkdm_dep *cd;
for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (cd->clkdm)
continue;
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
@ -257,43 +240,113 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
/* Public functions */
/**
* clkdm_init - set up the clockdomain layer
* @clkdms: optional pointer to an array of clockdomains to register
* @init_autodeps: optional pointer to an array of autodeps to register
* @custom_funcs: func pointers for arch specific implementations
* clkdm_register_platform_funcs - register clockdomain implementation fns
* @co: func pointers for arch specific implementations
*
* Set up internal state. If a pointer to an array of clockdomains
* @clkdms was supplied, loop through the list of clockdomains,
* register all that are available on the current platform. Similarly,
* if a pointer to an array of clockdomain autodependencies
* @init_autodeps was provided, register those. No return value.
* Register the list of function pointers used to implement the
* clockdomain functions on different OMAP SoCs. Should be called
* before any other clkdm_register*() function. Returns -EINVAL if
* @co is null, -EEXIST if platform functions have already been
* registered, or 0 upon success.
*/
void clkdm_init(struct clockdomain **clkdms,
struct clkdm_autodep *init_autodeps,
struct clkdm_ops *custom_funcs)
int clkdm_register_platform_funcs(struct clkdm_ops *co)
{
if (!co)
return -EINVAL;
if (arch_clkdm)
return -EEXIST;
arch_clkdm = co;
return 0;
};
/**
* clkdm_register_clkdms - register SoC clockdomains
* @cs: pointer to an array of struct clockdomain to register
*
* Register the clockdomains available on a particular OMAP SoC. Must
* be called after clkdm_register_platform_funcs(). May be called
* multiple times. Returns -EACCES if called before
* clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
* null; or 0 upon success.
*/
int clkdm_register_clkdms(struct clockdomain **cs)
{
struct clockdomain **c = NULL;
struct clockdomain *clkdm;
struct clkdm_autodep *autodep = NULL;
if (!custom_funcs)
WARN(1, "No custom clkdm functions registered\n");
else
arch_clkdm = custom_funcs;
if (!arch_clkdm)
return -EACCES;
if (clkdms)
for (c = clkdms; *c; c++)
_clkdm_register(*c);
if (!cs)
return -EINVAL;
for (c = cs; *c; c++)
_clkdm_register(*c);
return 0;
}
/**
* clkdm_register_autodeps - register autodeps (if required)
* @ia: pointer to a static array of struct clkdm_autodep to register
*
* Register clockdomain "automatic dependencies." These are
* clockdomain wakeup and sleep dependencies that are automatically
* added whenever the first clock inside a clockdomain is enabled, and
* removed whenever the last clock inside a clockdomain is disabled.
* These are currently only used on OMAP3 devices, and are deprecated,
* since they waste energy. However, until the OMAP2/3 IP block
* enable/disable sequence can be converted to match the OMAP4
* sequence, they are needed.
*
* Must be called only after all of the SoC clockdomains are
* registered, since the function will resolve autodep clockdomain
* names into clockdomain pointers.
*
* The struct clkdm_autodep @ia array must be static, as this function
* does not copy the array elements.
*
* Returns -EACCES if called before any clockdomains have been
* registered, -EINVAL if called with a null @ia argument, -EEXIST if
* autodeps have already been registered, or 0 upon success.
*/
int clkdm_register_autodeps(struct clkdm_autodep *ia)
{
struct clkdm_autodep *a = NULL;
if (list_empty(&clkdm_list))
return -EACCES;
if (!ia)
return -EINVAL;
autodeps = init_autodeps;
if (autodeps)
for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
_autodep_lookup(autodep);
return -EEXIST;
autodeps = ia;
for (a = autodeps; a->clkdm.ptr; a++)
_autodep_lookup(a);
return 0;
}
/**
* clkdm_complete_init - set up the clockdomain layer
*
* Put all clockdomains into software-supervised mode; PM code should
* later enable hardware-supervised mode as appropriate. Must be
* called after clkdm_register_clkdms(). Returns -EACCES if called
* before clkdm_register_clkdms(), or 0 upon success.
*/
int clkdm_complete_init(void)
{
struct clockdomain *clkdm;
if (list_empty(&clkdm_list))
return -EACCES;
/*
* Put all clockdomains into software-supervised mode; PM code
* should later enable hardware-supervised mode as appropriate
*/
list_for_each_entry(clkdm, &clkdm_list, node) {
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
clkdm_wakeup(clkdm);
@ -306,6 +359,8 @@ void clkdm_init(struct clockdomain **clkdms,
_resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
clkdm_clear_all_sleepdeps(clkdm);
}
return 0;
}
/**
@ -747,6 +802,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
ret = arch_clkdm->clkdm_wakeup(clkdm);
ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
return ret;
}
@ -818,6 +874,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_deny_idle(clkdm);
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
}

22
arch/arm/mach-omap2/clockdomain.h
Просмотреть файл

@ -45,7 +45,6 @@
/**
* struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
* @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
* @omap_chip: OMAP chip types that this autodep is valid on
*
* A clockdomain that should have wkdeps and sleepdeps added when a
* clockdomain should stay active in hwsup mode; and conversely,
@ -60,14 +59,12 @@ struct clkdm_autodep {
const char *name;
struct clockdomain *ptr;
} clkdm;
const struct omap_chip_id omap_chip;
};
/**
* struct clkdm_dep - encode dependencies between clockdomains
* @clkdm_name: clockdomain name
* @clkdm: pointer to the struct clockdomain of @clkdm_name
* @omap_chip: OMAP chip types that this dependency is valid on
* @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
* @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
*
@ -81,7 +78,6 @@ struct clkdm_dep {
struct clockdomain *clkdm;
atomic_t wkdep_usecount;
atomic_t sleepdep_usecount;
const struct omap_chip_id omap_chip;
};
/* Possible flags for struct clockdomain._flags */
@ -101,7 +97,6 @@ struct clkdm_dep {
* @clkdm_offs: (OMAP4 only) CM clockdomain register offset
* @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
* @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
* @omap_chip: OMAP chip types that this clockdomain is valid on
* @usecount: Usecount tracking
* @node: list_head to link all clockdomains together
*
@ -126,7 +121,6 @@ struct clockdomain {
const u16 clkdm_offs;
struct clkdm_dep *wkdep_srcs;
struct clkdm_dep *sleepdep_srcs;
const struct omap_chip_id omap_chip;
atomic_t usecount;
struct list_head node;
spinlock_t lock;
@ -166,8 +160,11 @@ struct clkdm_ops {
int (*clkdm_clk_disable)(struct clockdomain *clkdm);
};
void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
struct clkdm_ops *custom_funcs);
int clkdm_register_platform_funcs(struct clkdm_ops *co);
int clkdm_register_autodeps(struct clkdm_autodep *ia);
int clkdm_register_clkdms(struct clockdomain **c);
int clkdm_complete_init(void);
struct clockdomain *clkdm_lookup(const char *name);
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
@ -195,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
extern void __init omap2xxx_clockdomains_init(void);
extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
@ -205,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
extern struct clockdomain prm_common_clkdm;
extern struct clockdomain cm_common_clkdm;
#endif

4
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
Просмотреть файл

@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
u32 mask = 0;
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
u32 mask = 0;
for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */

2
arch/arm/mach-omap2/clockdomain44xx.c
Просмотреть файл

@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
u32 mask = 0;
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */

154
arch/arm/mach-omap2/clockdomains2420_data.c Normal file
Просмотреть файл

@ -0,0 +1,154 @@
/*
* OMAP2420 clockdomains
*
* Copyright (C) 2008-2011 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
*
* This file contains clockdomains and clockdomain wakeup dependencies
* for OMAP2420 chips. Some notes:
*
* A useful validation rule for struct clockdomain: Any clockdomain
* referenced by a wkdep_srcs must have a dep_bit assigned. So
* wkdep_srcs are really just software-controllable dependencies.
* Non-software-controllable dependencies do exist, but they are not
* encoded below (yet).
*
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
*
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
*
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
* sanity check?
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
*/
/*
* To-Do List
* -> Port the Sleep/Wakeup dependencies for the domains
* from the Power domain framework
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
/*
* Clockdomain dependencies for wkdeps
*
* XXX Hardware dependencies (e.g., dependencies that cannot be
* changed in software) are not included here yet, but should be.
*/
/* Wakeup dependency source arrays */
/* 2420-specific possible wakeup dependencies */
/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
static struct clkdm_dep mpu_2420_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
static struct clkdm_dep core_2420_wkdeps[] = {
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "gfx_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/*
* 2420-only clockdomains
*/
static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.wkdep_srcs = mpu_2420_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
};
static struct clockdomain iva1_2420_clkdm = {
.name = "iva1_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
.wkdep_srcs = dsp_24xx_wkdeps,
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
};
static struct clockdomain dsp_2420_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
};
static struct clockdomain gfx_2420_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
};
static struct clockdomain core_l3_2420_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.wkdep_srcs = core_2420_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
};
static struct clockdomain core_l4_2420_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.wkdep_srcs = core_2420_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
};
static struct clockdomain dss_2420_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
};
static struct clockdomain *clockdomains_omap242x[] __initdata = {
&wkup_common_clkdm,
&cm_common_clkdm,
&prm_common_clkdm,
&mpu_2420_clkdm,
&iva1_2420_clkdm,
&dsp_2420_clkdm,
&gfx_2420_clkdm,
&core_l3_2420_clkdm,
&core_l4_2420_clkdm,
&dss_2420_clkdm,
NULL,
};
void __init omap242x_clockdomains_init(void)
{
if (!cpu_is_omap242x())
return;
clkdm_register_platform_funcs(&omap2_clkdm_operations);
clkdm_register_clkdms(clockdomains_omap242x);
clkdm_complete_init();
}

181
arch/arm/mach-omap2/clockdomains2430_data.c Normal file
Просмотреть файл

@ -0,0 +1,181 @@
/*
* OMAP2xxx clockdomains
*
* Copyright (C) 2008-2009 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
*
* This file contains clockdomains and clockdomain wakeup dependencies
* for OMAP2xxx chips. Some notes:
*
* A useful validation rule for struct clockdomain: Any clockdomain
* referenced by a wkdep_srcs must have a dep_bit assigned. So
* wkdep_srcs are really just software-controllable dependencies.
* Non-software-controllable dependencies do exist, but they are not
* encoded below (yet).
*
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
*
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
*
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
* sanity check?
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
*/
/*
* To-Do List
* -> Port the Sleep/Wakeup dependencies for the domains
* from the Power domain framework
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
/*
* Clockdomain dependencies for wkdeps
*
* XXX Hardware dependencies (e.g., dependencies that cannot be
* changed in software) are not included here yet, but should be.
*/
/* Wakeup dependency source arrays */
/* 2430-specific possible wakeup dependencies */
/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
static struct clkdm_dep core_2430_wkdeps[] = {
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "gfx_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ .clkdm_name = "mdm_clkdm" },
{ NULL },
};
/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
static struct clkdm_dep mpu_2430_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ .clkdm_name = "mdm_clkdm" },
{ NULL },
};
/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
static struct clkdm_dep mdm_2430_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/*
* 2430-only clockdomains
*/
static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = mpu_2430_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
};
/* Another case of bit name collisions between several registers: EN_MDM */
static struct clockdomain mdm_clkdm = {
.name = "mdm_clkdm",
.pwrdm = { .name = "mdm_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
.wkdep_srcs = mdm_2430_wkdeps,
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
};
static struct clockdomain dsp_2430_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
.wkdep_srcs = dsp_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
};
static struct clockdomain gfx_2430_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
* could cause trouble
*/
static struct clockdomain core_l3_2430_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
.wkdep_srcs = core_2430_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
* could cause trouble
*/
static struct clockdomain core_l4_2430_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
.wkdep_srcs = core_2430_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
};
static struct clockdomain dss_2430_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
};
static struct clockdomain *clockdomains_omap243x[] __initdata = {
&wkup_common_clkdm,
&cm_common_clkdm,
&prm_common_clkdm,
&mpu_2430_clkdm,
&mdm_clkdm,
&dsp_2430_clkdm,
&gfx_2430_clkdm,
&core_l3_2430_clkdm,
&core_l4_2430_clkdm,
&dss_2430_clkdm,
NULL,
};
void __init omap243x_clockdomains_init(void)
{
if (!cpu_is_omap243x())
return;
clkdm_register_platform_funcs(&omap2_clkdm_operations);
clkdm_register_clkdms(clockdomains_omap243x);
clkdm_complete_init();
}

805
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
Просмотреть файл

@ -1,7 +1,7 @@
/*
* OMAP2/3 clockdomains
* OMAP2/3 clockdomain common data
*
* Copyright (C) 2008-2009 Texas Instruments, Inc.
* Copyright (C) 2008-2011 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
@ -51,374 +51,28 @@
* changed in software) are not included here yet, but should be.
*/
/* OMAP2/3-common wakeup dependencies */
/*
* 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
* These can share data since they will never be present simultaneously
* on the same device.
*/
static struct clkdm_dep gfx_sgx_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 24XX-specific possible dependencies */
#ifdef CONFIG_ARCH_OMAP2
/* Wakeup dependency source arrays */
/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
static struct clkdm_dep dsp_24xx_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
/* 2xxx-specific possible dependencies */
/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
struct clkdm_dep gfx_24xx_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/*
* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
* 2430 adds MDM
*/
static struct clkdm_dep mpu_24xx_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "dsp_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "mdm_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
},
/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
struct clkdm_dep dsp_24xx_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/*
* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
* 2430 adds MDM
*/
static struct clkdm_dep core_24xx_wkdeps[] = {
{
.clkdm_name = "dsp_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "mdm_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
},
{ NULL },
};
#endif /* CONFIG_ARCH_OMAP2 */
/* 2430-specific possible wakeup dependencies */
#ifdef CONFIG_SOC_OMAP2430
/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
static struct clkdm_dep mdm_2430_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{ NULL },
};
#endif /* CONFIG_SOC_OMAP2430 */
/* OMAP3-specific possible dependencies */
#ifdef CONFIG_ARCH_OMAP3
/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep per_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep usbhost_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
static struct clkdm_dep mpu_3xxx_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
static struct clkdm_dep iva2_wkdeps[] = {
{
.clkdm_name = "core_l3_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "core_l4_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
static struct clkdm_dep cam_wkdeps[] = {
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
static struct clkdm_dep dss_wkdeps[] = {
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430: PM_WKDEP_NEON: MPU */
static struct clkdm_dep neon_wkdeps[] = {
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* Sleep dependency source arrays for OMAP3-specific clkdms */
/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
static struct clkdm_dep dss_sleepdeps[] = {
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
static struct clkdm_dep per_sleepdeps[] = {
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
static struct clkdm_dep usbhost_sleepdeps[] = {
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm_name = "iva2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430: CM_SLEEPDEP_CAM: MPU */
static struct clkdm_dep cam_sleepdeps[] = {
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/*
* 3430ES1: CM_SLEEPDEP_GFX: MPU
* 3430ES2: CM_SLEEPDEP_SGX: MPU
* These can share data since they will never be present simultaneously
* on the same device.
*/
static struct clkdm_dep gfx_sgx_sleepdeps[] = {
{
.clkdm_name = "mpu_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
#endif /* CONFIG_ARCH_OMAP3 */
/*
* OMAP2/3-common clockdomains
@ -430,439 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
*/
/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
struct clockdomain wkup_common_clkdm = {
.name = "wkup_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
.dep_bit = OMAP_EN_WKUP_SHIFT,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
static struct clockdomain prm_clkdm = {
struct clockdomain prm_common_clkdm = {
.name = "prm_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
static struct clockdomain cm_clkdm = {
struct clockdomain cm_common_clkdm = {
.name = "cm_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
/*
* 2420-only clockdomains
*/
#if defined(CONFIG_SOC_OMAP2420)
static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.wkdep_srcs = mpu_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain iva1_2420_clkdm = {
.name = "iva1_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
.wkdep_srcs = dsp_24xx_wkdeps,
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain dsp_2420_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain gfx_2420_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_sgx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain core_l3_2420_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.wkdep_srcs = core_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain core_l4_2420_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.wkdep_srcs = core_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain dss_2420_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
#endif /* CONFIG_SOC_OMAP2420 */
/*
* 2430-only clockdomains
*/
#if defined(CONFIG_SOC_OMAP2430)
static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = mpu_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* Another case of bit name collisions between several registers: EN_MDM */
static struct clockdomain mdm_clkdm = {
.name = "mdm_clkdm",
.pwrdm = { .name = "mdm_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
.wkdep_srcs = mdm_2430_wkdeps,
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static struct clockdomain dsp_2430_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
.wkdep_srcs = dsp_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static struct clockdomain gfx_2430_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_sgx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
* could cause trouble
*/
static struct clockdomain core_l3_2430_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
.wkdep_srcs = core_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
* could cause trouble
*/
static struct clockdomain core_l4_2430_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
.wkdep_srcs = core_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static struct clockdomain dss_2430_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
#endif /* CONFIG_SOC_OMAP2430 */
/*
* OMAP3 clockdomains
*/
#if defined(CONFIG_ARCH_OMAP3)
static struct clockdomain mpu_3xxx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
.dep_bit = OMAP3430_EN_MPU_SHIFT,
.wkdep_srcs = mpu_3xxx_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain neon_clkdm = {
.name = "neon_clkdm",
.pwrdm = { .name = "neon_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = neon_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
.pwrdm = { .name = "iva2_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
.wkdep_srcs = iva2_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain gfx_3430es1_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs = gfx_sgx_sleepdeps,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
};
static struct clockdomain sgx_clkdm = {
.name = "sgx_clkdm",
.pwrdm = { .name = "sgx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs = gfx_sgx_sleepdeps,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
/*
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
* then that information was removed from the 34xx ES2+ TRM. It is
* unclear whether the core is still there, but the clockdomain logic
* is there, and must be programmed to an appropriate state if the
* CORE clockdomain is to become inactive.
*/
static struct clockdomain d2d_clkdm = {
.name = "d2d_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
* could cause trouble
*/
static struct clockdomain core_l3_3xxx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
* could cause trouble
*/
static struct clockdomain core_l4_3xxx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* Another case of bit name collisions between several registers: EN_DSS */
static struct clockdomain dss_3xxx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "dss_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
.wkdep_srcs = dss_wkdeps,
.sleepdep_srcs = dss_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain cam_clkdm = {
.name = "cam_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = cam_wkdeps,
.sleepdep_srcs = cam_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain usbhost_clkdm = {
.name = "usbhost_clkdm",
.pwrdm = { .name = "usbhost_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = usbhost_wkdeps,
.sleepdep_srcs = usbhost_sleepdeps,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
static struct clockdomain per_clkdm = {
.name = "per_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP3430_EN_PER_SHIFT,
.wkdep_srcs = per_wkdeps,
.sleepdep_srcs = per_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/*
* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
* switched of even if sdti is in use
*/
static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dpll1_clkdm = {
.name = "dpll1_clkdm",
.pwrdm = { .name = "dpll1_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dpll2_clkdm = {
.name = "dpll2_clkdm",
.pwrdm = { .name = "dpll2_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dpll3_clkdm = {
.name = "dpll3_clkdm",
.pwrdm = { .name = "dpll3_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dpll4_clkdm = {
.name = "dpll4_clkdm",
.pwrdm = { .name = "dpll4_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dpll5_clkdm = {
.name = "dpll5_clkdm",
.pwrdm = { .name = "dpll5_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
#endif /* CONFIG_ARCH_OMAP3 */
/*
* Clockdomain hwsup dependencies (OMAP3 only)
*/
static struct clkdm_autodep clkdm_autodeps[] = {
{
.clkdm = { .name = "mpu_clkdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm = { .name = "iva2_clkdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.clkdm = { .name = NULL },
}
};
static struct clockdomain *clockdomains_omap2[] __initdata = {
&wkup_clkdm,
&cm_clkdm,
&prm_clkdm,
#ifdef CONFIG_SOC_OMAP2420
&mpu_2420_clkdm,
&iva1_2420_clkdm,
&dsp_2420_clkdm,
&gfx_2420_clkdm,
&core_l3_2420_clkdm,
&core_l4_2420_clkdm,
&dss_2420_clkdm,
#endif
#ifdef CONFIG_SOC_OMAP2430
&mpu_2430_clkdm,
&mdm_clkdm,
&dsp_2430_clkdm,
&gfx_2430_clkdm,
&core_l3_2430_clkdm,
&core_l4_2430_clkdm,
&dss_2430_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP3
&mpu_3xxx_clkdm,
&neon_clkdm,
&iva2_clkdm,
&gfx_3430es1_clkdm,
&sgx_clkdm,
&d2d_clkdm,
&core_l3_3xxx_clkdm,
&core_l4_3xxx_clkdm,
&dss_3xxx_clkdm,
&cam_clkdm,
&usbhost_clkdm,
&per_clkdm,
&emu_clkdm,
&dpll1_clkdm,
&dpll2_clkdm,
&dpll3_clkdm,
&dpll4_clkdm,
&dpll5_clkdm,
#endif
NULL,
};
void __init omap2xxx_clockdomains_init(void)
{
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
}
void __init omap3xxx_clockdomains_init(void)
{
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
}

398
arch/arm/mach-omap2/clockdomains3xxx_data.c Normal file
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@ -0,0 +1,398 @@
/*
* OMAP3xxx clockdomains
*
* Copyright (C) 2008-2011 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
*
* This file contains clockdomains and clockdomain wakeup/sleep
* dependencies for the OMAP3xxx chips. Some notes:
*
* A useful validation rule for struct clockdomain: Any clockdomain
* referenced by a wkdep_srcs or sleepdep_srcs array must have a
* dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
* software-controllable dependencies. Non-software-controllable
* dependencies do exist, but they are not encoded below (yet).
*
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
*
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
* sanity check?
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
*/
/*
* To-Do List
* -> Port the Sleep/Wakeup dependencies for the domains
* from the Power domain framework
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
/*
* Clockdomain dependencies for wkdeps/sleepdeps
*
* XXX Hardware dependencies (e.g., dependencies that cannot be
* changed in software) are not included here yet, but should be.
*/
/* OMAP3-specific possible dependencies */
/*
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
*/
static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
{ .clkdm_name = "iva2_clkdm", },
{ .clkdm_name = "mpu_clkdm", },
{ .clkdm_name = "wkup_clkdm", },
{ NULL },
};
/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep per_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "iva2_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep usbhost_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "iva2_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
static struct clkdm_dep mpu_3xxx_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "iva2_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "per_clkdm" },
{ NULL },
};
/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
static struct clkdm_dep iva2_wkdeps[] = {
{ .clkdm_name = "core_l3_clkdm" },
{ .clkdm_name = "core_l4_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "per_clkdm" },
{ NULL },
};
/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
static struct clkdm_dep cam_wkdeps[] = {
{ .clkdm_name = "iva2_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
static struct clkdm_dep dss_wkdeps[] = {
{ .clkdm_name = "iva2_clkdm" },
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm" },
{ NULL },
};
/* 3430: PM_WKDEP_NEON: MPU */
static struct clkdm_dep neon_wkdeps[] = {
{ .clkdm_name = "mpu_clkdm" },
{ NULL },
};
/* Sleep dependency source arrays for OMAP3-specific clkdms */
/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
static struct clkdm_dep dss_sleepdeps[] = {
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "iva2_clkdm" },
{ NULL },
};
/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
static struct clkdm_dep per_sleepdeps[] = {
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "iva2_clkdm" },
{ NULL },
};
/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
static struct clkdm_dep usbhost_sleepdeps[] = {
{ .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "iva2_clkdm" },
{ NULL },
};
/* 3430: CM_SLEEPDEP_CAM: MPU */
static struct clkdm_dep cam_sleepdeps[] = {
{ .clkdm_name = "mpu_clkdm" },
{ NULL },
};
/*
* 3430ES1: CM_SLEEPDEP_GFX: MPU
* 3430ES2: CM_SLEEPDEP_SGX: MPU
* These can share data since they will never be present simultaneously
* on the same device.
*/
static struct clkdm_dep gfx_sgx_sleepdeps[] = {
{ .clkdm_name = "mpu_clkdm" },
{ NULL },
};
/*
* OMAP3 clockdomains
*/
static struct clockdomain mpu_3xxx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
.dep_bit = OMAP3430_EN_MPU_SHIFT,
.wkdep_srcs = mpu_3xxx_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
};
static struct clockdomain neon_clkdm = {
.name = "neon_clkdm",
.pwrdm = { .name = "neon_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = neon_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
};
static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
.pwrdm = { .name = "iva2_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
.wkdep_srcs = iva2_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
};
static struct clockdomain gfx_3430es1_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_sgx_3xxx_wkdeps,
.sleepdep_srcs = gfx_sgx_sleepdeps,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
};
static struct clockdomain sgx_clkdm = {
.name = "sgx_clkdm",
.pwrdm = { .name = "sgx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = gfx_sgx_3xxx_wkdeps,
.sleepdep_srcs = gfx_sgx_sleepdeps,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
};
/*
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
* then that information was removed from the 34xx ES2+ TRM. It is
* unclear whether the core is still there, but the clockdomain logic
* is there, and must be programmed to an appropriate state if the
* CORE clockdomain is to become inactive.
*/
static struct clockdomain d2d_clkdm = {
.name = "d2d_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
* could cause trouble
*/
static struct clockdomain core_l3_3xxx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
};
/*
* XXX add usecounting for clkdm dependencies, otherwise the presence
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
* could cause trouble
*/
static struct clockdomain core_l4_3xxx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
};
/* Another case of bit name collisions between several registers: EN_DSS */
static struct clockdomain dss_3xxx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "dss_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
.wkdep_srcs = dss_wkdeps,
.sleepdep_srcs = dss_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
};
static struct clockdomain cam_clkdm = {
.name = "cam_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = cam_wkdeps,
.sleepdep_srcs = cam_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
};
static struct clockdomain usbhost_clkdm = {
.name = "usbhost_clkdm",
.pwrdm = { .name = "usbhost_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.wkdep_srcs = usbhost_wkdeps,
.sleepdep_srcs = usbhost_sleepdeps,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
};
static struct clockdomain per_clkdm = {
.name = "per_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.dep_bit = OMAP3430_EN_PER_SHIFT,
.wkdep_srcs = per_wkdeps,
.sleepdep_srcs = per_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
};
/*
* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
* switched of even if sdti is in use
*/
static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
};
static struct clockdomain dpll1_clkdm = {
.name = "dpll1_clkdm",
.pwrdm = { .name = "dpll1_pwrdm" },
};
static struct clockdomain dpll2_clkdm = {
.name = "dpll2_clkdm",
.pwrdm = { .name = "dpll2_pwrdm" },
};
static struct clockdomain dpll3_clkdm = {
.name = "dpll3_clkdm",
.pwrdm = { .name = "dpll3_pwrdm" },
};
static struct clockdomain dpll4_clkdm = {
.name = "dpll4_clkdm",
.pwrdm = { .name = "dpll4_pwrdm" },
};
static struct clockdomain dpll5_clkdm = {
.name = "dpll5_clkdm",
.pwrdm = { .name = "dpll5_pwrdm" },
};
/*
* Clockdomain hwsup dependencies
*/
static struct clkdm_autodep clkdm_autodeps[] = {
{
.clkdm = { .name = "mpu_clkdm" },
},
{
.clkdm = { .name = "iva2_clkdm" },
},
{
.clkdm = { .name = NULL },
}
};
/*
*
*/
static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
&wkup_common_clkdm,
&cm_common_clkdm,
&prm_common_clkdm,
&mpu_3xxx_clkdm,
&neon_clkdm,
&iva2_clkdm,
&d2d_clkdm,
&core_l3_3xxx_clkdm,
&core_l4_3xxx_clkdm,
&dss_3xxx_clkdm,
&cam_clkdm,
&per_clkdm,
&emu_clkdm,
&dpll1_clkdm,
&dpll2_clkdm,
&dpll3_clkdm,
&dpll4_clkdm,
NULL
};
static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
&gfx_3430es1_clkdm,
NULL,
};
static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
&sgx_clkdm,
&dpll5_clkdm,
&usbhost_clkdm,
NULL,
};
void __init omap3xxx_clockdomains_init(void)
{
struct clockdomain **sc;
if (!cpu_is_omap34xx())
return;
clkdm_register_platform_funcs(&omap3_clkdm_operations);
clkdm_register_clkdms(clockdomains_omap3430_common);
sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
clockdomains_omap3430es2plus;
clkdm_register_clkdms(sc);
clkdm_register_autodeps(clkdm_autodeps);
clkdm_complete_init();
}

409
arch/arm/mach-omap2/clockdomains44xx_data.c
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@ -34,350 +34,122 @@
/* Static Dependencies for OMAP4 Clock Domains */
static struct clkdm_dep d2d_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_2_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l3_init_clkdm" },
{ .clkdm_name = "l4_cfg_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ NULL },
};
static struct clkdm_dep ducati_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "tesla_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_2_clkdm" },
{ .clkdm_name = "l3_dss_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l3_gfx_clkdm" },
{ .clkdm_name = "l3_init_clkdm" },
{ .clkdm_name = "l4_cfg_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ .clkdm_name = "l4_secure_clkdm" },
{ .clkdm_name = "l4_wkup_clkdm" },
{ .clkdm_name = "tesla_clkdm" },
{ NULL },
};
static struct clkdm_dep iss_wkup_sleep_deps[] = {
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ NULL },
};
static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ NULL },
};
static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ducati_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "ducati_clkdm" },
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_dss_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l3_init_clkdm" },
{ .clkdm_name = "l4_cfg_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ .clkdm_name = "l4_secure_clkdm" },
{ .clkdm_name = "l4_wkup_clkdm" },
{ NULL },
};
static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_2_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ NULL },
};
static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ NULL },
};
static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l4_cfg_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ .clkdm_name = "l4_secure_clkdm" },
{ .clkdm_name = "l4_wkup_clkdm" },
{ NULL },
};
static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ NULL },
};
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ducati_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "tesla_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "ducati_clkdm" },
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_2_clkdm" },
{ .clkdm_name = "l3_dss_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l3_gfx_clkdm" },
{ .clkdm_name = "l3_init_clkdm" },
{ .clkdm_name = "l4_cfg_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ .clkdm_name = "l4_secure_clkdm" },
{ .clkdm_name = "l4_wkup_clkdm" },
{ .clkdm_name = "tesla_clkdm" },
{ NULL },
};
static struct clkdm_dep tesla_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "ivahd_clkdm" },
{ .clkdm_name = "l3_1_clkdm" },
{ .clkdm_name = "l3_2_clkdm" },
{ .clkdm_name = "l3_emif_clkdm" },
{ .clkdm_name = "l3_init_clkdm" },
{ .clkdm_name = "l4_cfg_clkdm" },
{ .clkdm_name = "l4_per_clkdm" },
{ .clkdm_name = "l4_wkup_clkdm" },
{ NULL },
};
@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
.cm_inst = OMAP4430_CM2_CEFUSE_INST,
.clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l4_cfg_44xx_clkdm = {
@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
.clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
.dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain tesla_44xx_clkdm = {
@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = {
.wkdep_srcs = tesla_wkup_sleep_deps,
.sleepdep_srcs = tesla_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_gfx_44xx_clkdm = {
@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
.wkdep_srcs = l3_gfx_wkup_sleep_deps,
.sleepdep_srcs = l3_gfx_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain ivahd_44xx_clkdm = {
@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = {
.wkdep_srcs = ivahd_wkup_sleep_deps,
.sleepdep_srcs = ivahd_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l4_secure_44xx_clkdm = {
@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = {
.wkdep_srcs = l4_secure_wkup_sleep_deps,
.sleepdep_srcs = l4_secure_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l4_per_44xx_clkdm = {
@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = {
.clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
.dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain abe_44xx_clkdm = {
@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = {
.clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
.dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_instr_44xx_clkdm = {
@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_init_44xx_clkdm = {
@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = {
.wkdep_srcs = l3_init_wkup_sleep_deps,
.sleepdep_srcs = l3_init_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain d2d_44xx_clkdm = {
@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = {
.wkdep_srcs = d2d_wkup_sleep_deps,
.sleepdep_srcs = d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain mpu0_44xx_clkdm = {
@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = {
.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain mpu1_44xx_clkdm = {
@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = {
.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_emif_44xx_clkdm = {
@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = {
.clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
.dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l4_ao_44xx_clkdm = {
@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = {
.cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
.clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain ducati_44xx_clkdm = {
@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = {
.wkdep_srcs = ducati_wkup_sleep_deps,
.sleepdep_srcs = ducati_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain mpu_44xx_clkdm = {
@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = {
.wkdep_srcs = mpu_wkup_sleep_deps,
.sleepdep_srcs = mpu_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_2_44xx_clkdm = {
@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = {
.clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
.dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_1_44xx_clkdm = {
@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
.clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
.dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain iss_44xx_clkdm = {
@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = {
.wkdep_srcs = iss_wkup_sleep_deps,
.sleepdep_srcs = iss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_dss_44xx_clkdm = {
@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = {
.wkdep_srcs = l3_dss_wkup_sleep_deps,
.sleepdep_srcs = l3_dss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l4_wkup_44xx_clkdm = {
@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
.clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
.dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain emu_sys_44xx_clkdm = {
@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = {
.cm_inst = OMAP4430_PRM_EMU_CM_INST,
.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_dma_44xx_clkdm = {
@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = {
.wkdep_srcs = l3_dma_wkup_sleep_deps,
.sleepdep_srcs = l3_dma_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* As clockdomains are added or removed above, this list must also be changed */
@ -685,7 +433,10 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
NULL
};
void __init omap44xx_clockdomains_init(void)
{
clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
clkdm_register_platform_funcs(&omap4_clkdm_operations);
clkdm_register_clkdms(clockdomains_omap44xx);
clkdm_complete_init();
}

193
arch/arm/mach-omap2/id.c
Просмотреть файл

@ -28,7 +28,6 @@
#include "control.h"
static struct omap_chip_id omap_chip;
static unsigned int omap_revision;
u32 omap_features;
@ -39,19 +38,6 @@ unsigned int omap_rev(void)
}
EXPORT_SYMBOL(omap_rev);
/**
* omap_chip_is - test whether currently running OMAP matches a chip type
* @oc: omap_chip_t to test against
*
* Test whether the currently-running OMAP chip matches the supplied
* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
*/
int omap_chip_is(struct omap_chip_id oci)
{
return (oci.oc & omap_chip.oc) ? 1 : 0;
}
EXPORT_SYMBOL(omap_chip_is);
int omap_type(void)
{
u32 val = 0;
@ -242,14 +228,12 @@ static void __init ti816x_check_features(void)
omap_features = OMAP3_HAS_NEON;
}
static void __init omap3_check_revision(void)
static void __init omap3_check_revision(const char **cpu_rev)
{
u32 cpuid, idcode;
u16 hawkeye;
u8 rev;
omap_chip.oc = CHIP_IS_OMAP3430;
/*
* We cannot access revision registers on ES1.0.
* If the processor type is Cortex-A8 and the revision is 0x0
@ -258,7 +242,7 @@ static void __init omap3_check_revision(void)
cpuid = read_cpuid(CPUID_ID);
if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES1;
*cpu_rev = "1.0";
return;
}
@ -279,77 +263,85 @@ static void __init omap3_check_revision(void)
case 0: /* Take care of early samples */
case 1:
omap_revision = OMAP3430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
*cpu_rev = "2.0";
break;
case 2:
omap_revision = OMAP3430_REV_ES2_1;
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
*cpu_rev = "2.1";
break;
case 3:
omap_revision = OMAP3430_REV_ES3_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
*cpu_rev = "3.0";
break;
case 4:
omap_revision = OMAP3430_REV_ES3_1;
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
*cpu_rev = "3.1";
break;
case 7:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1_2;
/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
*cpu_rev = "3.1.2";
}
break;
case 0xb868:
/* Handle OMAP35xx/AM35xx devices
/*
* Handle OMAP/AM 3505/3517 devices
*
* Set the device to be OMAP3505 here. Actual device
* Set the device to be OMAP3517 here. Actual device
* is identified later based on the features.
*
* REVISIT: AM3505/AM3517 should have their own CHIP_IS
*/
omap_revision = OMAP3505_REV(rev);
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
switch (rev) {
case 0:
omap_revision = OMAP3517_REV_ES1_0;
*cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
omap_revision = OMAP3517_REV_ES1_1;
*cpu_rev = "1.1";
}
break;
case 0xb891:
/* Handle 36xx devices */
omap_chip.oc |= CHIP_IS_OMAP3630ES1;
switch(rev) {
case 0: /* Take care of early samples */
omap_revision = OMAP3630_REV_ES1_0;
*cpu_rev = "1.0";
break;
case 1:
omap_revision = OMAP3630_REV_ES1_1;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
*cpu_rev = "1.1";
break;
case 2:
/* FALLTHROUGH */
default:
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
omap_revision = OMAP3630_REV_ES1_2;
*cpu_rev = "1.2";
}
break;
case 0xb81e:
omap_chip.oc = CHIP_IS_TI816X;
switch (rev) {
case 0:
omap_revision = TI8168_REV_ES1_0;
*cpu_rev = "1.0";
break;
case 1:
omap_revision = TI8168_REV_ES1_1;
break;
/* FALLTHROUGH */
default:
omap_revision = TI8168_REV_ES1_1;
omap_revision = TI8168_REV_ES1_1;
*cpu_rev = "1.1";
break;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
*cpu_rev = "1.2";
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
}
}
@ -382,24 +374,20 @@ static void __init omap4_check_revision(void)
switch (rev) {
case 0:
omap_revision = OMAP4430_REV_ES1_0;
omap_chip.oc |= CHIP_IS_OMAP4430ES1;
break;
case 1:
default:
omap_revision = OMAP4430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP4430ES2;
}
break;
case 0xb95c:
switch (rev) {
case 3:
omap_revision = OMAP4430_REV_ES2_1;
omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
break;
case 4:
default:
omap_revision = OMAP4430_REV_ES2_2;
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
}
break;
case 0xb94e:
@ -407,14 +395,12 @@ static void __init omap4_check_revision(void)
case 0:
default:
omap_revision = OMAP4460_REV_ES1_0;
omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
break;
}
break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP4430_REV_ES2_2;
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
}
pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@ -425,94 +411,33 @@ static void __init omap4_check_revision(void)
if (omap3_has_ ##feat()) \
printk(#feat" ");
static void __init omap3_cpuinfo(void)
static void __init omap3_cpuinfo(const char *cpu_rev)
{
u8 rev = GET_OMAP_REVISION();
char cpu_name[16], cpu_rev[16];
const char *cpu_name;
/* OMAP3430 and OMAP3530 are assumed to be same.
/*
* OMAP3430 and OMAP3530 are assumed to be same.
*
* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
* on available features. Upon detection, update the CPU id
* and CPU class bits.
*/
if (cpu_is_omap3630()) {
strcpy(cpu_name, "OMAP3630");
} else if (cpu_is_omap3505()) {
/*
* AM35xx devices
*/
if (omap3_has_sgx()) {
omap_revision = OMAP3517_REV(rev);
strcpy(cpu_name, "AM3517");
} else {
/* Already set in omap3_check_revision() */
strcpy(cpu_name, "AM3505");
}
cpu_name = "OMAP3630";
} else if (cpu_is_omap3517()) {
/* AM35xx devices */
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
strcpy(cpu_name, "TI816X");
cpu_name = "TI816X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
cpu_name = "OMAP3430/3530";
} else if (omap3_has_iva()) {
omap_revision = OMAP3525_REV(rev);
strcpy(cpu_name, "OMAP3525");
cpu_name = "OMAP3525";
} else if (omap3_has_sgx()) {
omap_revision = OMAP3515_REV(rev);
strcpy(cpu_name, "OMAP3515");
cpu_name = "OMAP3515";
} else {
omap_revision = OMAP3503_REV(rev);
strcpy(cpu_name, "OMAP3503");
}
if (cpu_is_omap3630() || cpu_is_ti816x()) {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
break;
case OMAP_REVBITS_01:
strcpy(cpu_rev, "1.1");
break;
case OMAP_REVBITS_02:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
strcpy(cpu_rev, "1.2");
}
} else if (cpu_is_omap3505() || cpu_is_omap3517()) {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
break;
case OMAP_REVBITS_01:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
strcpy(cpu_rev, "1.1");
}
} else {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
break;
case OMAP_REVBITS_01:
strcpy(cpu_rev, "2.0");
break;
case OMAP_REVBITS_02:
strcpy(cpu_rev, "2.1");
break;
case OMAP_REVBITS_03:
strcpy(cpu_rev, "3.0");
break;
case OMAP_REVBITS_04:
strcpy(cpu_rev, "3.1");
break;
case OMAP_REVBITS_05:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
strcpy(cpu_rev, "3.1.2");
}
cpu_name = "OMAP3503";
}
/* Print verbose information */
@ -533,6 +458,8 @@ static void __init omap3_cpuinfo(void)
*/
void __init omap2_check_revision(void)
{
const char *cpu_rev;
/*
* At this point we have an idea about the processor revision set
* earlier with omap2_set_globals_tap().
@ -540,7 +467,7 @@ void __init omap2_check_revision(void)
if (cpu_is_omap24xx()) {
omap24xx_check_revision();
} else if (cpu_is_omap34xx()) {
omap3_check_revision();
omap3_check_revision(&cpu_rev);
/* TI816X doesn't have feature register */
if (!cpu_is_ti816x())
@ -548,7 +475,7 @@ void __init omap2_check_revision(void)
else
ti816x_check_features();
omap3_cpuinfo();
omap3_cpuinfo(cpu_rev);
return;
} else if (cpu_is_omap44xx()) {
omap4_check_revision();
@ -557,22 +484,6 @@ void __init omap2_check_revision(void)
} else {
pr_err("OMAP revision unknown, please fix!\n");
}
/*
* OK, now we know the exact revision. Initialize omap_chip bits
* for powerdowmain and clockdomain code.
*/
if (cpu_is_omap243x()) {
/* Currently only supports 2430ES2.1 and 2430-all */
omap_chip.oc |= CHIP_IS_OMAP2430;
return;
} else if (cpu_is_omap242x()) {
/* Currently only supports 2420ES2.1.1 and 2420-all */
omap_chip.oc |= CHIP_IS_OMAP2420;
return;
}
pr_err("Uninitialized omap_chip, please fix!\n");
}
/*

8
arch/arm/mach-omap2/io.c
Просмотреть файл

@ -341,12 +341,12 @@ void __init omap2_init_common_infrastructure(void)
u8 postsetup_state;
if (cpu_is_omap242x()) {
omap2xxx_powerdomains_init();
omap2xxx_clockdomains_init();
omap242x_powerdomains_init();
omap242x_clockdomains_init();
omap2420_hwmod_init();
} else if (cpu_is_omap243x()) {
omap2xxx_powerdomains_init();
omap2xxx_clockdomains_init();
omap243x_powerdomains_init();
omap243x_clockdomains_init();
omap2430_hwmod_init();
} else if (cpu_is_omap34xx()) {
omap3xxx_powerdomains_init();

3
arch/arm/mach-omap2/omap_hwmod.c
Просмотреть файл

@ -1954,9 +1954,6 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
i = 0;
do {
if (!omap_chip_is(ohs[i]->omap_chip))
continue;
r = _register(ohs[i]);
WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
r);

37
arch/arm/mach-omap2/omap_hwmod_2420_data.c
Просмотреть файл

@ -100,7 +100,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
.slaves = omap2420_l3_main_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -206,7 +205,6 @@ static struct omap_hwmod omap2420_l4_core_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
.slaves = omap2420_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -227,7 +225,6 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
.slaves = omap2420_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -243,7 +240,6 @@ static struct omap_hwmod omap2420_mpu_hwmod = {
.main_clk = "mpu_ck",
.masters = omap2420_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/*
@ -271,7 +267,6 @@ static struct omap_hwmod omap2420_iva_hwmod = {
.class = &iva_hwmod_class,
.masters = omap2420_iva_masters,
.masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer1 */
@ -317,7 +312,6 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
.slaves = omap2420_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer2 */
@ -354,7 +348,6 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
.slaves = omap2420_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer3 */
@ -391,7 +384,6 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
.slaves = omap2420_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer4 */
@ -428,7 +420,6 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
.slaves = omap2420_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer5 */
@ -465,7 +456,6 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
.slaves = omap2420_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
@ -503,7 +493,6 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
.slaves = omap2420_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer7 */
@ -540,7 +529,6 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
.slaves = omap2420_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer8 */
@ -577,7 +565,6 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
.slaves = omap2420_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer9 */
@ -614,7 +601,6 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
.slaves = omap2420_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer10 */
@ -651,7 +637,6 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
.slaves = omap2420_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer11 */
@ -688,7 +673,6 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
.slaves = omap2420_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer12 */
@ -725,7 +709,6 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
.slaves = omap2420_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* l4_wkup -> wd_timer2 */
@ -766,7 +749,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
},
.slaves = omap2420_wd_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* UART1 */
@ -792,7 +774,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
.slaves = omap2420_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* UART2 */
@ -818,7 +799,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
.slaves = omap2420_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* UART3 */
@ -844,7 +824,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
.slaves = omap2420_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* dss */
@ -898,7 +877,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
.masters = omap2420_dss_masters,
.masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -938,7 +916,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
},
.slaves = omap2420_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -975,7 +952,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
},
.slaves = omap2420_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -1013,7 +989,6 @@ static struct omap_hwmod omap2420_dss_venc_hwmod = {
},
.slaves = omap2420_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -1064,7 +1039,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
.class = &i2c_class,
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_16BIT_REG,
};
@ -1092,7 +1066,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
.class = &i2c_class,
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_16BIT_REG,
};
@ -1197,7 +1170,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* gpio2 */
@ -1223,7 +1195,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* gpio3 */
@ -1249,7 +1220,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* gpio4 */
@ -1275,7 +1245,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* dma attributes */
@ -1322,7 +1291,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
.masters = omap2420_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
@ -1363,7 +1331,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
},
.slaves = omap2420_mailbox_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* mcspi1 */
@ -1393,7 +1360,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
.class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* mcspi2 */
@ -1423,7 +1389,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
.class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/*
@ -1473,7 +1438,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
},
.slaves = omap2420_mcbsp1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* mcbsp2 */
@ -1514,7 +1478,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
},
.slaves = omap2420_mcbsp2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static __initdata struct omap_hwmod *omap2420_hwmods[] = {

46
arch/arm/mach-omap2/omap_hwmod_2430_data.c
Просмотреть файл

@ -110,7 +110,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
.slaves = omap2430_l3_main_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -192,6 +191,7 @@ static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
.pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_core ->usbhsotg interface */
@ -249,7 +249,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
.slaves = omap2430_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -300,7 +299,6 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
.masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
.slaves = omap2430_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -316,7 +314,6 @@ static struct omap_hwmod omap2430_mpu_hwmod = {
.main_clk = "mpu_ck",
.masters = omap2430_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/*
@ -344,7 +341,6 @@ static struct omap_hwmod omap2430_iva_hwmod = {
.class = &iva_hwmod_class,
.masters = omap2430_iva_masters,
.masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer1 */
@ -390,7 +386,6 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
.slaves = omap2430_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer2 */
@ -427,7 +422,6 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
.slaves = omap2430_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer3 */
@ -464,7 +458,6 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
.slaves = omap2430_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer4 */
@ -501,7 +494,6 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
.slaves = omap2430_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer5 */
@ -538,7 +530,6 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
.slaves = omap2430_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer6 */
@ -575,7 +566,6 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
.slaves = omap2430_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer7 */
@ -612,7 +602,6 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
.slaves = omap2430_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer8 */
@ -649,7 +638,6 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
.slaves = omap2430_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer9 */
@ -686,7 +674,6 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
.slaves = omap2430_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer10 */
@ -723,7 +710,6 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
.slaves = omap2430_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer11 */
@ -760,7 +746,6 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
.slaves = omap2430_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer12 */
@ -797,7 +782,6 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
.slaves = omap2430_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
.class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* l4_wkup -> wd_timer2 */
@ -838,7 +822,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
},
.slaves = omap2430_wd_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* UART1 */
@ -864,7 +847,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
.slaves = omap2430_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* UART2 */
@ -890,7 +872,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
.slaves = omap2430_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* UART3 */
@ -916,7 +897,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
.slaves = omap2430_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* dss */
@ -964,7 +944,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
.masters = omap2430_dss_masters,
.masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -998,7 +977,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
},
.slaves = omap2430_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -1029,7 +1007,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
},
.slaves = omap2430_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -1061,7 +1038,6 @@ static struct omap_hwmod omap2430_dss_venc_hwmod = {
},
.slaves = omap2430_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -1122,7 +1098,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
.class = &i2c_class,
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* I2C2 */
@ -1150,7 +1125,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
.class = &i2c_class,
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* l4_wkup -> gpio1 */
@ -1272,7 +1246,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio2 */
@ -1298,7 +1271,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio3 */
@ -1324,7 +1296,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio4 */
@ -1350,7 +1321,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio5 */
@ -1381,7 +1351,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
.class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* dma attributes */
@ -1428,7 +1397,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
.masters = omap2430_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
@ -1468,7 +1436,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
},
.slaves = omap2430_mailbox_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi1 */
@ -1498,7 +1465,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
.class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi2 */
@ -1528,7 +1494,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
.class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi3 */
@ -1571,7 +1536,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
.class = &omap2xxx_mcspi_class,
.dev_attr = &omap_mcspi3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/*
@ -1627,7 +1591,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
*/
.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/*
@ -1688,7 +1651,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
},
.slaves = omap2430_mcbsp1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcbsp2 */
@ -1730,7 +1692,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
},
.slaves = omap2430_mcbsp2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcbsp3 */
@ -1782,7 +1743,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
},
.slaves = omap2430_mcbsp3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcbsp4 */
@ -1840,7 +1800,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
},
.slaves = omap2430_mcbsp4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcbsp5 */
@ -1898,7 +1857,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
},
.slaves = omap2430_mcbsp5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* MMC/SD/SDIO common */
@ -1965,7 +1923,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
.slaves = omap2430_mmc1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
.class = &omap2430_mmc_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* MMC/SD/SDIO2 */
@ -2009,7 +1966,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
.slaves = omap2430_mmc2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
.class = &omap2430_mmc_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static __initdata struct omap_hwmod *omap2430_hwmods[] = {

173
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
Просмотреть файл

@ -156,7 +156,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
.slaves = omap3xxx_l3_main_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
};
@ -459,7 +458,6 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
.class = &l4_hwmod_class,
.slaves = omap3xxx_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
};
@ -474,7 +472,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
.class = &l4_hwmod_class,
.slaves = omap3xxx_l4_per_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
};
@ -489,7 +486,6 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
.class = &l4_hwmod_class,
.slaves = omap3xxx_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
};
@ -505,7 +501,6 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
.main_clk = "arm_fck",
.masters = omap3xxx_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/*
@ -533,7 +528,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
.class = &iva_hwmod_class,
.masters = omap3xxx_iva_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer class */
@ -613,7 +607,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
.slaves = omap3xxx_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
.class = &omap3xxx_timer_1ms_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer2 */
@ -659,7 +652,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
.slaves = omap3xxx_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
.class = &omap3xxx_timer_1ms_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer3 */
@ -705,7 +697,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
.slaves = omap3xxx_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer4 */
@ -751,7 +742,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
.slaves = omap3xxx_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer5 */
@ -797,7 +787,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
.slaves = omap3xxx_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer6 */
@ -843,7 +832,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
.slaves = omap3xxx_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer7 */
@ -889,7 +877,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
.slaves = omap3xxx_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer8 */
@ -935,7 +922,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
.slaves = omap3xxx_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer9 */
@ -981,7 +967,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
.slaves = omap3xxx_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer10 */
@ -1018,7 +1003,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
.slaves = omap3xxx_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
.class = &omap3xxx_timer_1ms_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer11 */
@ -1055,7 +1039,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
.slaves = omap3xxx_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* timer12*/
@ -1105,7 +1088,6 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
.slaves = omap3xxx_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
.class = &omap3xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* l4_wkup -> wd_timer2 */
@ -1182,7 +1164,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
},
.slaves = omap3xxx_wd_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
/*
* XXX: Use software supervised mode, HW supervised smartidle seems to
* block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@ -1213,7 +1194,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
.slaves = omap3xxx_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* UART2 */
@ -1239,7 +1219,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
.slaves = omap3xxx_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* UART3 */
@ -1265,7 +1244,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
.slaves = omap3xxx_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* UART4 */
@ -1302,7 +1280,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
.slaves = omap3xxx_uart4_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
static struct omap_hwmod_class i2c_class = {
@ -1390,7 +1367,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
.masters = omap3xxx_dss_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
.flags = HWMOD_NO_IDLEST,
};
@ -1415,8 +1391,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
.masters = omap3xxx_dss_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
};
/* l4_core -> dss_dispc */
@ -1454,9 +1428,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
},
.slaves = omap3xxx_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
@ -1518,9 +1489,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
},
.slaves = omap3xxx_dss_dsi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
@ -1558,9 +1526,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
},
.slaves = omap3xxx_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
@ -1599,9 +1564,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
},
.slaves = omap3xxx_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
@ -1637,7 +1599,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
.class = &i2c_class,
.dev_attr = &i2c1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* I2C2 */
@ -1672,7 +1633,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
.class = &i2c_class,
.dev_attr = &i2c2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* I2C3 */
@ -1718,7 +1678,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
.class = &i2c_class,
.dev_attr = &i2c3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* l4_wkup -> gpio1 */
@ -1880,7 +1839,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
.class = &omap3xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* gpio2 */
@ -1912,7 +1870,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
.class = &omap3xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* gpio3 */
@ -1944,7 +1901,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
.class = &omap3xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* gpio4 */
@ -1976,7 +1932,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
.class = &omap3xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* gpio5 */
@ -2013,7 +1968,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
.class = &omap3xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* gpio6 */
@ -2050,7 +2004,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
.class = &omap3xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* dma_system -> L3 */
@ -2134,7 +2087,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.masters = omap3xxx_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
};
@ -2207,7 +2159,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
},
.slaves = omap3xxx_mcbsp1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcbsp2 */
@ -2264,7 +2215,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.slaves = omap3xxx_mcbsp2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
.dev_attr = &omap34xx_mcbsp2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcbsp3 */
@ -2321,7 +2271,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.slaves = omap3xxx_mcbsp3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
.dev_attr = &omap34xx_mcbsp3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcbsp4 */
@ -2379,7 +2328,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
},
.slaves = omap3xxx_mcbsp4_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcbsp5 */
@ -2437,7 +2385,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
},
.slaves = omap3xxx_mcbsp5_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* 'mcbsp sidetone' class */
@ -2498,7 +2445,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
},
.slaves = omap3xxx_mcbsp2_sidetone_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcbsp3_sidetone */
@ -2547,7 +2493,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
},
.slaves = omap3xxx_mcbsp3_sidetone_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@ -2609,9 +2554,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@ -2631,7 +2573,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/* SR2 */
@ -2655,9 +2596,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@ -2677,7 +2615,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/*
@ -2745,7 +2682,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
},
.slaves = omap3xxx_mailbox_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* l4 core -> mcspi1 interface */
@ -2843,7 +2779,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcspi2 */
@ -2873,7 +2808,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcspi3 */
@ -2916,7 +2850,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* SPI4 */
@ -2957,7 +2890,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi4_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/*
@ -3014,7 +2946,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
*/
.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* usb_otg_hs */
@ -3042,7 +2973,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
.slaves = am35xx_usbhsotg_slaves,
.slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
.class = &am35xx_usbotg_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
};
/* MMC/SD/SDIO common */
@ -3108,7 +3038,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
.slaves = omap3xxx_mmc1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
.class = &omap34xx_mmc_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* MMC/SD/SDIO2 */
@ -3151,7 +3080,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
.slaves = omap3xxx_mmc2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
.class = &omap34xx_mmc_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* MMC/SD/SDIO3 */
@ -3193,7 +3121,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
.slaves = omap3xxx_mmc3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
.class = &omap34xx_mmc_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
@ -3224,10 +3151,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_uart1_hwmod,
&omap3xxx_uart2_hwmod,
&omap3xxx_uart3_hwmod,
&omap3xxx_uart4_hwmod,
/* dss class */
&omap3430es1_dss_core_hwmod,
&omap3xxx_dss_core_hwmod,
&omap3xxx_dss_dispc_hwmod,
&omap3xxx_dss_dsi1_hwmod,
&omap3xxx_dss_rfbi_hwmod,
@ -3239,9 +3163,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_i2c3_hwmod,
&omap34xx_sr1_hwmod,
&omap34xx_sr2_hwmod,
&omap36xx_sr1_hwmod,
&omap36xx_sr2_hwmod,
/* gpio class */
&omap3xxx_gpio1_hwmod,
@ -3272,16 +3193,96 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap34xx_mcspi3,
&omap34xx_mcspi4,
/* usbotg class */
&omap3xxx_usbhsotg_hwmod,
/* usbotg for am35x */
&am35xx_usbhsotg_hwmod,
NULL,
};
/* 3430ES1-only hwmods */
static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
&omap3430es1_dss_core_hwmod,
NULL
};
/* 3430ES2+-only hwmods */
static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
&omap3xxx_dss_core_hwmod,
&omap3xxx_usbhsotg_hwmod,
NULL
};
/* 34xx-only hwmods (all ES revisions) */
static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
&omap34xx_sr1_hwmod,
&omap34xx_sr2_hwmod,
NULL
};
/* 36xx-only hwmods (all ES revisions) */
static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
&omap3xxx_uart4_hwmod,
&omap3xxx_dss_core_hwmod,
&omap36xx_sr1_hwmod,
&omap36xx_sr2_hwmod,
&omap3xxx_usbhsotg_hwmod,
NULL
};
static __initdata struct omap_hwmod *am35xx_hwmods[] = {
&omap3xxx_dss_core_hwmod, /* XXX ??? */
&am35xx_usbhsotg_hwmod,
NULL
};
int __init omap3xxx_hwmod_init(void)
{
return omap_hwmod_register(omap3xxx_hwmods);
int r;
struct omap_hwmod **h = NULL;
unsigned int rev;
/* Register hwmods common to all OMAP3 */
r = omap_hwmod_register(omap3xxx_hwmods);
if (!r)
return r;
rev = omap_rev();
/*
* Register hwmods common to individual OMAP3 families, all
* silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
* All possible revisions should be included in this conditional.
*/
if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmods;
} else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
h = am35xx_hwmods;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmods;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
};
r = omap_hwmod_register(h);
if (!r)
return r;
/*
* Register hwmods specific to certain ES levels of a
* particular family of silicon (e.g., 34xx ES1.0)
*/
h = NULL;
if (rev == OMAP3430_REV_ES1_0) {
h = omap3430es1_hwmods;
} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
rev == OMAP3430_REV_ES3_1_2) {
h = omap3430es2plus_hwmods;
};
if (h)
r = omap_hwmod_register(h);
return r;
}

82
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
Просмотреть файл

@ -133,7 +133,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
.slaves = omap44xx_dmm_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
.mpu_irqs = omap44xx_dmm_irqs,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -189,7 +188,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
},
.slaves = omap44xx_emif_fw_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -236,7 +234,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
},
.slaves = omap44xx_l3_instr_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* l3_main_1 */
@ -336,7 +333,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
},
.slaves = omap44xx_l3_main_1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* l3_main_2 */
@ -438,7 +434,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
},
.slaves = omap44xx_l3_main_2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* l3_main_3 */
@ -496,7 +491,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
},
.slaves = omap44xx_l3_main_3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -559,7 +553,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
},
.slaves = omap44xx_l4_abe_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* l4_cfg */
@ -588,7 +581,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
},
.slaves = omap44xx_l4_cfg_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* l4_per */
@ -617,7 +609,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
},
.slaves = omap44xx_l4_per_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* l4_wkup */
@ -646,7 +637,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
},
.slaves = omap44xx_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -677,7 +667,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
.clkdm_name = "mpuss_clkdm",
.slaves = omap44xx_mpu_private_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -828,7 +817,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
.masters = omap44xx_aess_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -856,7 +844,6 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = {
},
.opt_clks = bandgap_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -917,7 +904,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
},
.slaves = omap44xx_counter_32k_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1005,7 +991,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
.masters = omap44xx_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1098,7 +1083,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
},
.slaves = omap44xx_dmic_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1164,7 +1148,6 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct omap_hwmod omap44xx_dsp_hwmod = {
@ -1187,7 +1170,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
.masters = omap44xx_dsp_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1278,7 +1260,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
.masters = omap44xx_dss_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1381,7 +1362,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
.slaves = omap44xx_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1480,7 +1460,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
.slaves = omap44xx_dss_dsi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* dss_dsi2 */
@ -1558,7 +1537,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
.slaves = omap44xx_dss_dsi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1656,7 +1634,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.slaves = omap44xx_dss_hdmi_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1748,7 +1725,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
.slaves = omap44xx_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1817,7 +1793,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
},
.slaves = omap44xx_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -1901,7 +1876,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
.dev_attr = &gpio_dev_attr,
.slaves = omap44xx_gpio1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* gpio2 */
@ -1957,7 +1931,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
.dev_attr = &gpio_dev_attr,
.slaves = omap44xx_gpio2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* gpio3 */
@ -2013,7 +1986,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
.dev_attr = &gpio_dev_attr,
.slaves = omap44xx_gpio3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* gpio4 */
@ -2069,7 +2041,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
.dev_attr = &gpio_dev_attr,
.slaves = omap44xx_gpio4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* gpio5 */
@ -2125,7 +2096,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
.dev_attr = &gpio_dev_attr,
.slaves = omap44xx_gpio5_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* gpio6 */
@ -2181,7 +2151,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.dev_attr = &gpio_dev_attr,
.slaves = omap44xx_gpio6_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2261,7 +2230,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
.masters = omap44xx_hsi_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2345,7 +2313,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
.slaves = omap44xx_i2c1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* i2c2 */
@ -2402,7 +2369,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
.slaves = omap44xx_i2c2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* i2c3 */
@ -2459,7 +2425,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
.slaves = omap44xx_i2c3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* i2c4 */
@ -2516,7 +2481,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
.slaves = omap44xx_i2c4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
.dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2577,7 +2541,6 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* Pseudo hwmod for reset control purpose only */
@ -2593,7 +2556,6 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct omap_hwmod omap44xx_ipu_hwmod = {
@ -2616,7 +2578,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
.masters = omap44xx_ipu_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2706,7 +2667,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
.masters = omap44xx_iss_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2781,7 +2741,6 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* Pseudo hwmod for reset control purpose only */
@ -2797,7 +2756,6 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct omap_hwmod omap44xx_iva_hwmod = {
@ -2820,7 +2778,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
.masters = omap44xx_iva_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2890,7 +2847,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
},
.slaves = omap44xx_kbd_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -2956,7 +2912,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
},
.slaves = omap44xx_mailbox_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -3051,7 +3006,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
},
.slaves = omap44xx_mcbsp1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mcbsp2 */
@ -3127,7 +3081,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
},
.slaves = omap44xx_mcbsp2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mcbsp3 */
@ -3203,7 +3156,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
},
.slaves = omap44xx_mcbsp3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mcbsp4 */
@ -3258,7 +3210,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
},
.slaves = omap44xx_mcbsp4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -3353,7 +3304,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
},
.slaves = omap44xx_mcpdm_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -3442,7 +3392,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.dev_attr = &mcspi1_dev_attr,
.slaves = omap44xx_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mcspi2 */
@ -3505,7 +3454,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.dev_attr = &mcspi2_dev_attr,
.slaves = omap44xx_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mcspi3 */
@ -3568,7 +3516,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.dev_attr = &mcspi3_dev_attr,
.slaves = omap44xx_mcspi3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mcspi4 */
@ -3629,7 +3576,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.dev_attr = &mcspi4_dev_attr,
.slaves = omap44xx_mcspi4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -3718,7 +3664,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
.masters = omap44xx_mmc1_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mmc2 */
@ -3779,7 +3724,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
.masters = omap44xx_mmc2_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mmc3 */
@ -3834,7 +3778,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
},
.slaves = omap44xx_mmc3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mmc4 */
@ -3890,7 +3833,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
},
.slaves = omap44xx_mmc4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* mmc5 */
@ -3945,7 +3887,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
},
.slaves = omap44xx_mmc5_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -3987,7 +3928,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
},
.masters = omap44xx_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -4063,7 +4003,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
},
.slaves = omap44xx_smartreflex_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* smartreflex_iva */
@ -4112,7 +4051,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
},
.slaves = omap44xx_smartreflex_iva_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* smartreflex_mpu */
@ -4161,7 +4099,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
},
.slaves = omap44xx_smartreflex_mpu_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -4224,7 +4161,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
},
.slaves = omap44xx_spinlock_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -4310,7 +4246,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
},
.slaves = omap44xx_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer2 */
@ -4358,7 +4293,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
},
.slaves = omap44xx_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer3 */
@ -4406,7 +4340,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
},
.slaves = omap44xx_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer4 */
@ -4454,7 +4387,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
},
.slaves = omap44xx_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer5 */
@ -4521,7 +4453,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
},
.slaves = omap44xx_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer6 */
@ -4589,7 +4520,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
},
.slaves = omap44xx_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer7 */
@ -4656,7 +4586,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
},
.slaves = omap44xx_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer8 */
@ -4723,7 +4652,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
},
.slaves = omap44xx_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer9 */
@ -4771,7 +4699,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
},
.slaves = omap44xx_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer10 */
@ -4819,7 +4746,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
},
.slaves = omap44xx_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* timer11 */
@ -4867,7 +4793,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
},
.slaves = omap44xx_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -4944,7 +4869,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
},
.slaves = omap44xx_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* uart2 */
@ -4999,7 +4923,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
},
.slaves = omap44xx_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* uart3 */
@ -5055,7 +4978,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
},
.slaves = omap44xx_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* uart4 */
@ -5110,7 +5032,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
},
.slaves = omap44xx_uart4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -5195,7 +5116,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
.masters = omap44xx_usb_otg_hs_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
@ -5266,7 +5186,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
},
.slaves = omap44xx_wd_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* wd_timer3 */
@ -5333,7 +5252,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
},
.slaves = omap44xx_wd_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {

2
arch/arm/mach-omap2/pm.c
Просмотреть файл

@ -130,7 +130,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
} else {
hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
sleep_switch = FORCEWAKEUP_SWITCH;
}
}
@ -156,7 +155,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
return ret;
}
pwrdm_wait_transition(pwrdm);
pwrdm_state_switch(pwrdm);
err:
return ret;

7
arch/arm/mach-omap2/powerdomain-common.c
Просмотреть файл

@ -1,9 +1,8 @@
/*
* linux/arch/arm/mach-omap2/powerdomain-common.c
* Contains common powerdomain framework functions
* Common powerdomain framework functions
*
* Copyright (C) 2010 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2010-2011 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
*
* Derived from mach-omap2/powerdomain.c written by Paul Walmsley
*

86
arch/arm/mach-omap2/powerdomain.c
Просмотреть файл

@ -1,7 +1,7 @@
/*
* OMAP powerdomain control
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
@ -81,9 +81,6 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
if (!pwrdm || !pwrdm->name)
return -EINVAL;
if (!omap_chip_is(pwrdm->omap_chip))
return -EINVAL;
if (cpu_is_omap44xx() &&
pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
@ -194,29 +191,76 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
/* Public functions */
/**
* pwrdm_init - set up the powerdomain layer
* @pwrdm_list: array of struct powerdomain pointers to register
* @custom_funcs: func pointers for arch specific implementations
* pwrdm_register_platform_funcs - register powerdomain implementation fns
* @po: func pointers for arch specific implementations
*
* Loop through the array of powerdomains @pwrdm_list, registering all
* that are available on the current CPU. If pwrdm_list is supplied
* and not null, all of the referenced powerdomains will be
* registered. No return value. XXX pwrdm_list is not really a
* "list"; it is an array. Rename appropriately.
* Register the list of function pointers used to implement the
* powerdomain functions on different OMAP SoCs. Should be called
* before any other pwrdm_register*() function. Returns -EINVAL if
* @po is null, -EEXIST if platform functions have already been
* registered, or 0 upon success.
*/
void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs)
int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
{
if (!po)
return -EINVAL;
if (arch_pwrdm)
return -EEXIST;
arch_pwrdm = po;
return 0;
}
/**
* pwrdm_register_pwrdms - register SoC powerdomains
* @ps: pointer to an array of struct powerdomain to register
*
* Register the powerdomains available on a particular OMAP SoC. Must
* be called after pwrdm_register_platform_funcs(). May be called
* multiple times. Returns -EACCES if called before
* pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
* null; or 0 upon success.
*/
int pwrdm_register_pwrdms(struct powerdomain **ps)
{
struct powerdomain **p = NULL;
if (!custom_funcs)
WARN(1, "powerdomain: No custom pwrdm functions registered\n");
else
arch_pwrdm = custom_funcs;
if (!arch_pwrdm)
return -EEXIST;
if (pwrdm_list) {
for (p = pwrdm_list; *p; p++)
_pwrdm_register(*p);
}
if (!ps)
return -EINVAL;
for (p = ps; *p; p++)
_pwrdm_register(*p);
return 0;
}
/**
* pwrdm_complete_init - set up the powerdomain layer
*
* Do whatever is necessary to initialize registered powerdomains and
* powerdomain code. Currently, this programs the next power state
* for each powerdomain to ON. This prevents powerdomains from
* unexpectedly losing context or entering high wakeup latency modes
* with non-power-management-enabled kernels. Must be called after
* pwrdm_register_pwrdms(). Returns -EACCES if called before
* pwrdm_register_pwrdms(), or 0 upon success.
*/
int pwrdm_complete_init(void)
{
struct powerdomain *temp_p;
if (list_empty(&pwrdm_list))
return -EACCES;
list_for_each_entry(temp_p, &pwrdm_list, node)
pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
return 0;
}
/**

9
arch/arm/mach-omap2/powerdomain.h
Просмотреть файл

@ -78,7 +78,6 @@ struct powerdomain;
/**
* struct powerdomain - OMAP powerdomain
* @name: Powerdomain name
* @omap_chip: represents the OMAP chip types containing this pwrdm
* @prcm_offs: the address offset from CM_BASE/PRM_BASE
* @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
* @pwrsts: Possible powerdomain power states
@ -98,7 +97,6 @@ struct powerdomain;
*/
struct powerdomain {
const char *name;
const struct omap_chip_id omap_chip;
const s16 prcm_offs;
const u8 pwrsts;
const u8 pwrsts_logic_ret;
@ -162,7 +160,9 @@ struct pwrdm_ops {
int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
};
void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
int pwrdm_complete_init(void);
struct powerdomain *pwrdm_lookup(const char *name);
@ -210,7 +210,8 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
extern void omap2xxx_powerdomains_init(void);
extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);

19
arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
Просмотреть файл

@ -1,7 +1,7 @@
/*
* OMAP2/3 common powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
@ -11,20 +11,6 @@
* published by the Free Software Foundation.
*/
/*
* To Do List
* -> Move the Sleep/Wakeup dependencies from Power Domain framework to
* Clock Domain Framework
*/
/*
* This file contains all of the powerdomains that have some element
* of software control for the OMAP24xx and OMAP34xx chips.
*
* This is not an exhaustive listing of powerdomains on the chips; only
* powerdomains that can be controlled in software.
*/
/*
* The names for the DSP/IVA2 powerdomains are confusing.
*
@ -59,8 +45,6 @@
struct powerdomain gfx_omap2_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = GFX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430ES1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
@ -75,6 +59,5 @@ struct powerdomain gfx_omap2_pwrdm = {
struct powerdomain wkup_omap2_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = WKUP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_ON,
};

48
arch/arm/mach-omap2/powerdomains2xxx_data.c
Просмотреть файл

@ -1,7 +1,7 @@
/*
* OMAP2XXX powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
@ -28,7 +28,6 @@
static struct powerdomain dsp_pwrdm = {
.name = "dsp_pwrdm",
.prcm_offs = OMAP24XX_DSP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
@ -43,7 +42,6 @@ static struct powerdomain dsp_pwrdm = {
static struct powerdomain mpu_24xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@ -58,7 +56,6 @@ static struct powerdomain mpu_24xx_pwrdm = {
static struct powerdomain core_24xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.pwrsts = PWRSTS_OFF_RET_ON,
.banks = 3,
.pwrsts_mem_ret = {
@ -78,14 +75,11 @@ static struct powerdomain core_24xx_pwrdm = {
* 2430-specific powerdomains
*/
#ifdef CONFIG_SOC_OMAP2430
/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
static struct powerdomain mdm_pwrdm = {
.name = "mdm_pwrdm",
.prcm_offs = OMAP2430_MDM_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
@ -97,27 +91,41 @@ static struct powerdomain mdm_pwrdm = {
},
};
#endif /* CONFIG_SOC_OMAP2430 */
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
/*
*
*/
static struct powerdomain *powerdomains_omap24xx[] __initdata = {
&wkup_omap2_pwrdm,
&gfx_omap2_pwrdm,
#ifdef CONFIG_ARCH_OMAP2
&dsp_pwrdm,
&mpu_24xx_pwrdm,
&core_24xx_pwrdm,
#endif
#ifdef CONFIG_SOC_OMAP2430
&mdm_pwrdm,
#endif
NULL
};
void __init omap2xxx_powerdomains_init(void)
static struct powerdomain *powerdomains_omap2430[] __initdata = {
&mdm_pwrdm,
NULL
};
void __init omap242x_powerdomains_init(void)
{
pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
if (!cpu_is_omap2420())
return;
pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap24xx);
pwrdm_complete_init();
}
void __init omap243x_powerdomains_init(void)
{
if (!cpu_is_omap2430())
return;
pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap24xx);
pwrdm_register_pwrdms(powerdomains_omap2430);
pwrdm_complete_init();
}

83
arch/arm/mach-omap2/powerdomains3xxx_data.c
Просмотреть файл

@ -1,7 +1,7 @@
/*
* OMAP3 powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Paul Walmsley, Jouni Högander
@ -14,6 +14,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <plat/cpu.h>
#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
@ -27,8 +29,6 @@
* 34XX-specific powerdomains, dependencies
*/
#ifdef CONFIG_ARCH_OMAP3
/*
* Powerdomains
*/
@ -36,7 +36,6 @@
static struct powerdomain iva2_pwrdm = {
.name = "iva2_pwrdm",
.prcm_offs = OMAP3430_IVA2_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 4,
@ -57,7 +56,6 @@ static struct powerdomain iva2_pwrdm = {
static struct powerdomain mpu_3xxx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_MPU_QUIRK,
@ -83,10 +81,6 @@ static struct powerdomain mpu_3xxx_pwrdm = {
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3630ES1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
@ -103,8 +97,6 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
static struct powerdomain core_3xxx_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
CHIP_GE_OMAP3630ES1_1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
/*
@ -125,7 +117,6 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
static struct powerdomain dss_pwrdm = {
.name = "dss_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_DSS_MOD,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
@ -146,7 +137,6 @@ static struct powerdomain dss_pwrdm = {
static struct powerdomain sgx_pwrdm = {
.name = "sgx_pwrdm",
.prcm_offs = OMAP3430ES2_SGX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
/* XXX This is accurate for 3430 SGX, but what about GFX? */
.pwrsts = PWRSTS_OFF_ON,
.pwrsts_logic_ret = PWRSTS_RET,
@ -161,7 +151,6 @@ static struct powerdomain sgx_pwrdm = {
static struct powerdomain cam_pwrdm = {
.name = "cam_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_CAM_MOD,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
@ -177,7 +166,6 @@ static struct powerdomain cam_pwrdm = {
static struct powerdomain per_pwrdm = {
.name = "per_pwrdm",
.prcm_offs = OMAP3430_PER_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@ -192,13 +180,11 @@ static struct powerdomain per_pwrdm = {
static struct powerdomain emu_pwrdm = {
.name = "emu_pwrdm",
.prcm_offs = OMAP3430_EMU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct powerdomain neon_pwrdm = {
.name = "neon_pwrdm",
.prcm_offs = OMAP3430_NEON_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
};
@ -206,7 +192,6 @@ static struct powerdomain neon_pwrdm = {
static struct powerdomain usbhost_pwrdm = {
.name = "usbhost_pwrdm",
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
/*
@ -228,60 +213,92 @@ static struct powerdomain usbhost_pwrdm = {
static struct powerdomain dpll1_pwrdm = {
.name = "dpll1_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct powerdomain dpll2_pwrdm = {
.name = "dpll2_pwrdm",
.prcm_offs = OMAP3430_IVA2_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct powerdomain dpll3_pwrdm = {
.name = "dpll3_pwrdm",
.prcm_offs = PLL_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct powerdomain dpll4_pwrdm = {
.name = "dpll4_pwrdm",
.prcm_offs = PLL_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct powerdomain dpll5_pwrdm = {
.name = "dpll5_pwrdm",
.prcm_offs = PLL_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
&wkup_omap2_pwrdm,
&gfx_omap2_pwrdm,
&iva2_pwrdm,
&mpu_3xxx_pwrdm,
&neon_pwrdm,
&core_3xxx_pre_es3_1_pwrdm,
&core_3xxx_es3_1_pwrdm,
&cam_pwrdm,
&dss_pwrdm,
&per_pwrdm,
&emu_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
&dpll1_pwrdm,
&dpll2_pwrdm,
&dpll3_pwrdm,
&dpll4_pwrdm,
&dpll5_pwrdm,
#endif
NULL
};
static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
&gfx_omap2_pwrdm,
&core_3xxx_pre_es3_1_pwrdm,
NULL
};
/* also includes 3630ES1.0 */
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
&core_3xxx_pre_es3_1_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
&dpll5_pwrdm,
NULL
};
/* also includes 3630ES1.1+ */
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
&core_3xxx_es3_1_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
&dpll5_pwrdm,
NULL
};
void __init omap3xxx_powerdomains_init(void)
{
pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
unsigned int rev;
if (!cpu_is_omap34xx())
return;
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap3430_common);
rev = omap_rev();
if (rev == OMAP3430_REV_ES1_0)
pwrdm_register_pwrdms(powerdomains_omap3430es1);
else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
else
WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
pwrdm_complete_init();
}

20
arch/arm/mach-omap2/powerdomains44xx_data.c
Просмотреть файл

@ -35,7 +35,6 @@ static struct powerdomain core_44xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = OMAP4430_PRM_CORE_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 5,
@ -61,7 +60,6 @@ static struct powerdomain gfx_44xx_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = OMAP4430_PRM_GFX_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
@ -78,7 +76,6 @@ static struct powerdomain abe_44xx_pwrdm = {
.name = "abe_pwrdm",
.prcm_offs = OMAP4430_PRM_ABE_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 2,
@ -98,7 +95,6 @@ static struct powerdomain dss_44xx_pwrdm = {
.name = "dss_pwrdm",
.prcm_offs = OMAP4430_PRM_DSS_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1,
@ -116,7 +112,6 @@ static struct powerdomain tesla_44xx_pwrdm = {
.name = "tesla_pwrdm",
.prcm_offs = OMAP4430_PRM_TESLA_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
@ -138,7 +133,6 @@ static struct powerdomain wkup_44xx_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = OMAP4430_PRM_WKUP_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_ON,
.banks = 1,
.pwrsts_mem_ret = {
@ -154,7 +148,6 @@ static struct powerdomain cpu0_44xx_pwrdm = {
.name = "cpu0_pwrdm",
.prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@ -171,7 +164,6 @@ static struct powerdomain cpu1_44xx_pwrdm = {
.name = "cpu1_pwrdm",
.prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@ -188,7 +180,6 @@ static struct powerdomain emu_44xx_pwrdm = {
.name = "emu_pwrdm",
.prcm_offs = OMAP4430_PRM_EMU_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
@ -204,7 +195,6 @@ static struct powerdomain mpu_44xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = OMAP4430_PRM_MPU_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
@ -225,7 +215,6 @@ static struct powerdomain ivahd_44xx_pwrdm = {
.name = "ivahd_pwrdm",
.prcm_offs = OMAP4430_PRM_IVAHD_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 4,
@ -249,7 +238,6 @@ static struct powerdomain cam_44xx_pwrdm = {
.name = "cam_pwrdm",
.prcm_offs = OMAP4430_PRM_CAM_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
@ -266,7 +254,6 @@ static struct powerdomain l3init_44xx_pwrdm = {
.name = "l3init_pwrdm",
.prcm_offs = OMAP4430_PRM_L3INIT_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@ -284,7 +271,6 @@ static struct powerdomain l4per_44xx_pwrdm = {
.name = "l4per_pwrdm",
.prcm_offs = OMAP4430_PRM_L4PER_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
@ -307,7 +293,6 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
.name = "always_on_core_pwrdm",
.prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_ON,
};
@ -316,7 +301,6 @@ static struct powerdomain cefuse_44xx_pwrdm = {
.name = "cefuse_pwrdm",
.prcm_offs = OMAP4430_PRM_CEFUSE_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
@ -352,5 +336,7 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = {
void __init omap44xx_powerdomains_init(void)
{
pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap44xx);
pwrdm_complete_init();
}

1
arch/arm/mach-shmobile/board-ap4evb.c
Просмотреть файл

@ -1412,6 +1412,7 @@ static void __init ap4evb_init(void)
fsi_init_pm_clock();
sh7372_pm_init();
pm_clk_add(&fsi_device.dev, "spu2");
pm_clk_add(&lcdc1_device.dev, "hdmi");
}
static void __init ap4evb_timer_init(void)

1
arch/arm/mach-shmobile/board-mackerel.c
Просмотреть файл

@ -1588,6 +1588,7 @@ static void __init mackerel_init(void)
hdmi_init_pm_clock();
sh7372_pm_init();
pm_clk_add(&fsi_device.dev, "spu2");
pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
}
static void __init mackerel_timer_init(void)

2
arch/arm/mach-shmobile/clock-sh7372.c
Просмотреть файл

@ -655,6 +655,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
&div6_reparent_clks[DIV6_HDMI]),
CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),

2
arch/arm/plat-omap/include/plat/clock.h
Просмотреть файл

@ -80,8 +80,6 @@ struct clkops {
*
* @div is the divisor that should be applied to the parent clock's rate
* to produce the current clock's rate.
*
* XXX @flags probably should be replaced with an struct omap_chip.
*/
struct clksel_rate {
u32 val;

108
arch/arm/plat-omap/include/plat/cpu.h
Просмотреть файл

@ -44,13 +44,6 @@
int omap_type(void);
struct omap_chip_id {
u16 oc;
u8 type;
};
#define OMAP_CHIP_INIT(x) { .oc = x }
/*
* omap_rev bits:
* CPU id bits (0730, 1510, 1710, 2422...) [31:16]
@ -59,19 +52,6 @@ struct omap_chip_id {
*/
unsigned int omap_rev(void);
/*
* Define CPU revision bits
*
* Verbose meaning of the revision bits may be different for a silicon
* family. This difference can be handled separately.
*/
#define OMAP_REVBITS_00 0x00
#define OMAP_REVBITS_01 0x01
#define OMAP_REVBITS_02 0x02
#define OMAP_REVBITS_03 0x03
#define OMAP_REVBITS_04 0x04
#define OMAP_REVBITS_05 0x05
/*
* Get the CPU revision for OMAP devices
*/
@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
IS_OMAP_TYPE(2423, 0x2423)
IS_OMAP_TYPE(2430, 0x2430)
IS_OMAP_TYPE(3430, 0x3430)
IS_OMAP_TYPE(3505, 0x3505)
IS_OMAP_TYPE(3505, 0x3517)
IS_OMAP_TYPE(3517, 0x3517)
#define cpu_is_omap310() 0
@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
(!omap3_has_sgx()) && \
(omap3_has_iva()))
# define cpu_is_omap3530() (cpu_is_omap3430())
# define cpu_is_omap3505() is_omap3505()
# define cpu_is_omap3517() is_omap3517()
# define cpu_is_omap3505() (cpu_is_omap3517() && \
!omap3_has_sgx())
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
# define cpu_is_ti816x() is_ti816x()
@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
#define OMAP243X_CLASS 0x24300024
#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
#define OMAP343X_CLASS 0x34300034
#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
#define OMAP363X_CLASS 0x36300034
#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
#define OMAP35XX_CLASS 0x35000034
#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
#define OMAP3517_CLASS 0x35170034
#define OMAP3517_REV_ES1_0 OMAP3517_CLASS
#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (0x1 << 8))
#define TI816X_CLASS 0x81600034
#define TI8168_REV_ES1_0 TI816X_CLASS
#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP446X_CLASS 0x44600044
#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
/*
* omap_chip bits
*
* CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
* valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
* something that is only valid on that particular ES revision.
*
* These bits may be ORed together to indicate structures that are
* available on multiple chip types.
*
* To test whether a particular structure matches the current OMAP chip type,
* use omap_chip_is().
*
*/
#define CHIP_IS_OMAP2420 (1 << 0)
#define CHIP_IS_OMAP2430 (1 << 1)
#define CHIP_IS_OMAP3430 (1 << 2)
#define CHIP_IS_OMAP3430ES1 (1 << 3)
#define CHIP_IS_OMAP3430ES2 (1 << 4)
#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
#define CHIP_IS_OMAP3630ES1 (1 << 7)
#define CHIP_IS_OMAP4430ES1 (1 << 8)
#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
#define CHIP_IS_OMAP4430ES2 (1 << 11)
#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
#define CHIP_IS_TI816X (1 << 14)
#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
CHIP_IS_OMAP4430ES2 | \
CHIP_IS_OMAP4430ES2_1 | \
CHIP_IS_OMAP4430ES2_2 | \
CHIP_IS_OMAP4460ES1_0)
/*
* "GE" here represents "greater than or equal to" in terms of ES
* levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
* chips at ES2 and beyond, but not, for example, any OMAP lines after
* OMAP3.
*/
#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
CHIP_IS_OMAP3430ES3_0 | \
CHIP_GE_OMAP3430ES3_1)
#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
CHIP_IS_OMAP3630ES1 | \
CHIP_GE_OMAP3630ES1_1)
#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \
CHIP_IS_OMAP3630ES1_2)
int omap_chip_is(struct omap_chip_id oci);
void omap2_check_revision(void);
/*

2
arch/arm/plat-omap/include/plat/omap_hwmod.h
Просмотреть файл

@ -496,7 +496,6 @@ struct omap_hwmod_class {
* @_state: internal-use hwmod state
* @_postsetup_state: internal-use state to leave the hwmod in after _setup()
* @flags: hwmod flags (documented below)
* @omap_chip: OMAP chips this hwmod is present on
* @_lock: spinlock serializing operations on this hwmod
* @node: list node for hwmod list (internal use)
*
@ -545,7 +544,6 @@ struct omap_hwmod {
u8 _int_flags;
u8 _state;
u8 _postsetup_state;
const struct omap_chip_id omap_chip;
};
int omap_hwmod_register(struct omap_hwmod **ohs);

3
arch/arm/plat-omap/omap_device.c
Просмотреть файл

@ -622,7 +622,8 @@ static struct dev_pm_domain omap_device_pm_domain = {
SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
_od_runtime_idle)
USE_PLATFORM_PM_SLEEP_OPS
SET_SYSTEM_SLEEP_PM_OPS(_od_suspend_noirq, _od_resume_noirq)
.suspend_noirq = _od_suspend_noirq,
.resume_noirq = _od_resume_noirq,
}
};

2
arch/avr32/kernel/syscall_table.S
Просмотреть файл

@ -158,7 +158,7 @@ sys_call_table:
.long sys_sched_rr_get_interval
.long sys_nanosleep
.long sys_poll
.long sys_nfsservctl /* 145 */
.long sys_ni_syscall /* 145 was nfsservctl */
.long sys_setresgid
.long sys_getresgid
.long sys_prctl

2
arch/blackfin/mach-common/entry.S
Просмотреть файл

@ -1543,7 +1543,7 @@ ENTRY(_sys_call_table)
.long _sys_ni_syscall /* for vm86 */
.long _sys_ni_syscall /* old "query_module" */
.long _sys_ni_syscall /* sys_poll */
.long _sys_nfsservctl
.long _sys_ni_syscall /* old nfsservctl */
.long _sys_setresgid /* setresgid16 */ /* 170 */
.long _sys_getresgid /* getresgid16 */
.long _sys_prctl

2
arch/cris/arch-v10/kernel/entry.S
Просмотреть файл

@ -771,7 +771,7 @@ sys_call_table:
.long sys_ni_syscall /* sys_vm86 */
.long sys_ni_syscall /* Old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* old nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

2
arch/cris/arch-v32/kernel/entry.S
Просмотреть файл

@ -714,7 +714,7 @@ sys_call_table:
.long sys_ni_syscall /* sys_vm86 */
.long sys_ni_syscall /* Old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* Old nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

9
arch/cris/include/asm/serial.h Normal file
Просмотреть файл

@ -0,0 +1,9 @@
#ifndef _ASM_SERIAL_H
#define _ASM_SERIAL_H
/*
* This assumes you have a 1.8432 MHz clock for your UART.
*/
#define BASE_BAUD (1843200 / 16)
#endif /* _ASM_SERIAL_H */

2
arch/frv/kernel/entry.S
Просмотреть файл

@ -1358,7 +1358,7 @@ sys_call_table:
.long sys_ni_syscall /* for vm86 */
.long sys_ni_syscall /* Old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* Old nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

2
arch/h8300/kernel/syscalls.S
Просмотреть файл

@ -183,7 +183,7 @@ SYMBOL_NAME_LABEL(sys_call_table)
.long SYMBOL_NAME(sys_ni_syscall) /* for vm86 */
.long SYMBOL_NAME(sys_ni_syscall) /* sys_query_module */
.long SYMBOL_NAME(sys_poll)
.long SYMBOL_NAME(sys_nfsservctl)
.long SYMBOL_NAME(sys_ni_syscall) /* old nfsservctl */
.long SYMBOL_NAME(sys_setresgid16) /* 170 */
.long SYMBOL_NAME(sys_getresgid16)
.long SYMBOL_NAME(sys_prctl)

2
arch/ia64/kernel/entry.S
Просмотреть файл

@ -1614,7 +1614,7 @@ sys_call_table:
data8 sys_sched_get_priority_min
data8 sys_sched_rr_get_interval
data8 sys_nanosleep
data8 sys_nfsservctl
data8 sys_ni_syscall // old nfsservctl
data8 sys_prctl // 1170
data8 sys_getpagesize
data8 sys_mmap2

2
arch/m32r/kernel/syscall_table.S
Просмотреть файл

@ -168,7 +168,7 @@ ENTRY(sys_call_table)
.long sys_tas /* vm86 syscall holder */
.long sys_ni_syscall /* query_module syscall holder */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* was nfsservctl */
.long sys_setresgid /* 170 */
.long sys_getresgid
.long sys_prctl

2
arch/m68k/include/asm/page_mm.h
Просмотреть файл

@ -162,7 +162,7 @@ static inline __attribute_const__ int __virt_to_node_shift(void)
pgdat->node_mem_map + (__pfn - pgdat->node_start_pfn); \
})
#define page_to_pfn(_page) ({ \
struct page *__p = (_page); \
const struct page *__p = (_page); \
struct pglist_data *pgdat; \
pgdat = &pg_data_map[page_to_nid(__p)]; \
((__p) - pgdat->node_mem_map) + pgdat->node_start_pfn; \

2
arch/m68k/kernel/syscalltable.S
Просмотреть файл

@ -189,7 +189,7 @@ ENTRY(sys_call_table)
.long sys_getpagesize
.long sys_ni_syscall /* old "query_module" */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* old nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

2
arch/microblaze/kernel/syscall_table.S
Просмотреть файл

@ -173,7 +173,7 @@ ENTRY(sys_call_table)
.long sys_ni_syscall /* sys_vm86 */
.long sys_ni_syscall /* Old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* old nfsservctl */
.long sys_setresgid /* 170 */
.long sys_getresgid
.long sys_prctl

2
arch/mips/kernel/scall32-o32.S
Просмотреть файл

@ -424,7 +424,7 @@ einval: li v0, -ENOSYS
sys sys_getresuid 3
sys sys_ni_syscall 0 /* was sys_query_module */
sys sys_poll 3
sys sys_nfsservctl 3
sys sys_ni_syscall 0 /* was nfsservctl */
sys sys_setresgid 3 /* 4190 */
sys sys_getresgid 3
sys sys_prctl 5

2
arch/mips/kernel/scall64-64.S
Просмотреть файл

@ -299,7 +299,7 @@ sys_call_table:
PTR sys_ni_syscall /* 5170, was get_kernel_syms */
PTR sys_ni_syscall /* was query_module */
PTR sys_quotactl
PTR sys_nfsservctl
PTR sys_ni_syscall /* was nfsservctl */
PTR sys_ni_syscall /* res. for getpmsg */
PTR sys_ni_syscall /* 5175 for putpmsg */
PTR sys_ni_syscall /* res. for afs_syscall */

2
arch/mips/kernel/scall64-n32.S
Просмотреть файл

@ -294,7 +294,7 @@ EXPORT(sysn32_call_table)
PTR sys_ni_syscall /* 6170, was get_kernel_syms */
PTR sys_ni_syscall /* was query_module */
PTR sys_quotactl
PTR compat_sys_nfsservctl
PTR sys_ni_syscall /* was nfsservctl */
PTR sys_ni_syscall /* res. for getpmsg */
PTR sys_ni_syscall /* 6175 for putpmsg */
PTR sys_ni_syscall /* res. for afs_syscall */

2
arch/mips/kernel/scall64-o32.S
Просмотреть файл

@ -392,7 +392,7 @@ sys_call_table:
PTR sys_getresuid
PTR sys_ni_syscall /* was query_module */
PTR sys_poll
PTR compat_sys_nfsservctl
PTR sys_ni_syscall /* was nfsservctl */
PTR sys_setresgid /* 4190 */
PTR sys_getresgid
PTR sys_prctl

2
arch/mn10300/kernel/entry.S
Просмотреть файл

@ -589,7 +589,7 @@ ENTRY(sys_call_table)
.long sys_ni_syscall /* vm86 */
.long sys_ni_syscall /* Old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* was nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

5
arch/powerpc/sysdev/fsl_rio.c
Просмотреть файл

@ -54,6 +54,7 @@
#define ODSR_CLEAR 0x1c00
#define LTLEECSR_ENABLE_ALL 0xFFC000FC
#define ESCSR_CLEAR 0x07120204
#define IECSR_CLEAR 0x80000000
#define RIO_PORT1_EDCSR 0x0640
#define RIO_PORT2_EDCSR 0x0680
@ -1089,11 +1090,11 @@ static void port_error_handler(struct rio_mport *port, int offset)
if (offset == 0) {
out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), 0);
out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
} else {
out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), 0);
out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
}
}

6
arch/s390/kernel/compat_wrapper.S
Просмотреть файл

@ -665,12 +665,6 @@ ENTRY(sys32_poll_wrapper)
lgfr %r4,%r4 # long
jg sys_poll # branch to system call
ENTRY(compat_sys_nfsservctl_wrapper)
lgfr %r2,%r2 # int
llgtr %r3,%r3 # struct compat_nfsctl_arg*
llgtr %r4,%r4 # union compat_nfsctl_res*
jg compat_sys_nfsservctl # branch to system call
ENTRY(sys32_setresgid16_wrapper)
llgfr %r2,%r2 # __kernel_old_gid_emu31_t
llgfr %r3,%r3 # __kernel_old_gid_emu31_t

14
arch/s390/kernel/early.c
Просмотреть файл

@ -396,17 +396,19 @@ static __init void detect_machine_facilities(void)
static __init void rescue_initrd(void)
{
#ifdef CONFIG_BLK_DEV_INITRD
unsigned long min_initrd_addr = (unsigned long) _end + (4UL << 20);
/*
* Move the initrd right behind the bss section in case it starts
* within the bss section. So we don't overwrite it when the bss
* section gets cleared.
* Just like in case of IPL from VM reader we make sure there is a
* gap of 4MB between end of kernel and start of initrd.
* That way we can also be sure that saving an NSS will succeed,
* which however only requires different segments.
*/
if (!INITRD_START || !INITRD_SIZE)
return;
if (INITRD_START >= (unsigned long) __bss_stop)
if (INITRD_START >= min_initrd_addr)
return;
memmove(__bss_stop, (void *) INITRD_START, INITRD_SIZE);
INITRD_START = (unsigned long) __bss_stop;
memmove((void *) min_initrd_addr, (void *) INITRD_START, INITRD_SIZE);
INITRD_START = min_initrd_addr;
#endif
}

7
arch/s390/kernel/ipl.c
Просмотреть файл

@ -1220,7 +1220,7 @@ static int __init reipl_fcp_init(void)
/* sysfs: create fcp kset for mixing attr group and bin attrs */
reipl_fcp_kset = kset_create_and_add(IPL_FCP_STR, NULL,
&reipl_kset->kobj);
if (!reipl_kset) {
if (!reipl_fcp_kset) {
free_page((unsigned long) reipl_block_fcp);
return -ENOMEM;
}
@ -1618,7 +1618,8 @@ static struct shutdown_action vmcmd_action = {SHUTDOWN_ACTION_VMCMD_STR,
static void stop_run(struct shutdown_trigger *trigger)
{
if (strcmp(trigger->name, ON_PANIC_STR) == 0)
if (strcmp(trigger->name, ON_PANIC_STR) == 0 ||
strcmp(trigger->name, ON_RESTART_STR) == 0)
disabled_wait((unsigned long) __builtin_return_address(0));
while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
cpu_relax();
@ -1717,7 +1718,7 @@ static void do_panic(void)
/* on restart */
static struct shutdown_trigger on_restart_trigger = {ON_RESTART_STR,
&reipl_action};
&stop_action};
static ssize_t on_restart_show(struct kobject *kobj,
struct kobj_attribute *attr, char *page)

2
arch/s390/kernel/syscalls.S
Просмотреть файл

@ -177,7 +177,7 @@ SYSCALL(sys_getresuid16,sys_ni_syscall,sys32_getresuid16_wrapper) /* 165 old get
NI_SYSCALL /* for vm86 */
NI_SYSCALL /* old sys_query_module */
SYSCALL(sys_poll,sys_poll,sys32_poll_wrapper)
SYSCALL(sys_nfsservctl,sys_nfsservctl,compat_sys_nfsservctl_wrapper)
NI_SYSCALL /* old nfsservctl */
SYSCALL(sys_setresgid16,sys_ni_syscall,sys32_setresgid16_wrapper) /* 170 old setresgid16 syscall */
SYSCALL(sys_getresgid16,sys_ni_syscall,sys32_getresgid16_wrapper) /* old getresgid16 syscall */
SYSCALL(sys_prctl,sys_prctl,sys32_prctl_wrapper)

2
arch/sh/kernel/syscalls_32.S
Просмотреть файл

@ -185,7 +185,7 @@ ENTRY(sys_call_table)
.long sys_ni_syscall /* vm86 */
.long sys_ni_syscall /* old "query_module" */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* was nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

2
arch/sh/kernel/syscalls_64.S
Просмотреть файл

@ -189,7 +189,7 @@ sys_call_table:
.long sys_ni_syscall /* vm86 */
.long sys_ni_syscall /* old "query_module" */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* was nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

14
arch/sparc/include/asm/sigcontext.h
Просмотреть файл

@ -45,6 +45,19 @@ typedef struct {
int si_mask;
} __siginfo32_t;
#define __SIGC_MAXWIN 7
typedef struct {
unsigned long locals[8];
unsigned long ins[8];
} __siginfo_reg_window;
typedef struct {
int wsaved;
__siginfo_reg_window reg_window[__SIGC_MAXWIN];
unsigned long rwbuf_stkptrs[__SIGC_MAXWIN];
} __siginfo_rwin_t;
#ifdef CONFIG_SPARC64
typedef struct {
unsigned int si_float_regs [64];
@ -73,6 +86,7 @@ struct sigcontext {
unsigned long ss_size;
} sigc_stack;
unsigned long sigc_mask;
__siginfo_rwin_t * sigc_rwin_save;
};
#else

1
arch/sparc/kernel/Makefile
Просмотреть файл

@ -32,6 +32,7 @@ obj-$(CONFIG_SPARC32) += sun4m_irq.o sun4c_irq.o sun4d_irq.o
obj-y += process_$(BITS).o
obj-y += signal_$(BITS).o
obj-y += sigutil_$(BITS).o
obj-$(CONFIG_SPARC32) += ioport.o
obj-y += setup_$(BITS).o
obj-y += idprom.o

184
arch/sparc/kernel/signal32.c
Просмотреть файл

@ -29,6 +29,8 @@
#include <asm/visasm.h>
#include <asm/compat_signal.h>
#include "sigutil.h"
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
/* This magic should be in g_upper[0] for all upper parts
@ -44,14 +46,14 @@ typedef struct {
struct signal_frame32 {
struct sparc_stackf32 ss;
__siginfo32_t info;
/* __siginfo_fpu32_t * */ u32 fpu_save;
/* __siginfo_fpu_t * */ u32 fpu_save;
unsigned int insns[2];
unsigned int extramask[_COMPAT_NSIG_WORDS - 1];
unsigned int extra_size; /* Should be sizeof(siginfo_extra_v8plus_t) */
/* Only valid if (info.si_regs.psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS */
siginfo_extra_v8plus_t v8plus;
__siginfo_fpu_t fpu_state;
};
/* __siginfo_rwin_t * */u32 rwin_save;
} __attribute__((aligned(8)));
typedef struct compat_siginfo{
int si_signo;
@ -110,18 +112,14 @@ struct rt_signal_frame32 {
compat_siginfo_t info;
struct pt_regs32 regs;
compat_sigset_t mask;
/* __siginfo_fpu32_t * */ u32 fpu_save;
/* __siginfo_fpu_t * */ u32 fpu_save;
unsigned int insns[2];
stack_t32 stack;
unsigned int extra_size; /* Should be sizeof(siginfo_extra_v8plus_t) */
/* Only valid if (regs.psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS */
siginfo_extra_v8plus_t v8plus;
__siginfo_fpu_t fpu_state;
};
/* Align macros */
#define SF_ALIGNEDSZ (((sizeof(struct signal_frame32) + 15) & (~15)))
#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 15) & (~15)))
/* __siginfo_rwin_t * */u32 rwin_save;
} __attribute__((aligned(8)));
int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
{
@ -192,30 +190,13 @@ int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
return 0;
}
static int restore_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
unsigned long *fpregs = current_thread_info()->fpregs;
unsigned long fprs;
int err;
err = __get_user(fprs, &fpu->si_fprs);
fprs_write(0);
regs->tstate &= ~TSTATE_PEF;
if (fprs & FPRS_DL)
err |= copy_from_user(fpregs, &fpu->si_float_regs[0], (sizeof(unsigned int) * 32));
if (fprs & FPRS_DU)
err |= copy_from_user(fpregs+16, &fpu->si_float_regs[32], (sizeof(unsigned int) * 32));
err |= __get_user(current_thread_info()->xfsr[0], &fpu->si_fsr);
err |= __get_user(current_thread_info()->gsr[0], &fpu->si_gsr);
current_thread_info()->fpsaved[0] |= fprs;
return err;
}
void do_sigreturn32(struct pt_regs *regs)
{
struct signal_frame32 __user *sf;
compat_uptr_t fpu_save;
compat_uptr_t rwin_save;
unsigned int psr;
unsigned pc, npc, fpu_save;
unsigned pc, npc;
sigset_t set;
unsigned seta[_COMPAT_NSIG_WORDS];
int err, i;
@ -273,8 +254,13 @@ void do_sigreturn32(struct pt_regs *regs)
pt_regs_clear_syscall(regs);
err |= __get_user(fpu_save, &sf->fpu_save);
if (fpu_save)
err |= restore_fpu_state32(regs, &sf->fpu_state);
if (!err && fpu_save)
err |= restore_fpu_state(regs, compat_ptr(fpu_save));
err |= __get_user(rwin_save, &sf->rwin_save);
if (!err && rwin_save) {
if (restore_rwin_state(compat_ptr(rwin_save)))
goto segv;
}
err |= __get_user(seta[0], &sf->info.si_mask);
err |= copy_from_user(seta+1, &sf->extramask,
(_COMPAT_NSIG_WORDS - 1) * sizeof(unsigned int));
@ -300,7 +286,9 @@ segv:
asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
{
struct rt_signal_frame32 __user *sf;
unsigned int psr, pc, npc, fpu_save, u_ss_sp;
unsigned int psr, pc, npc, u_ss_sp;
compat_uptr_t fpu_save;
compat_uptr_t rwin_save;
mm_segment_t old_fs;
sigset_t set;
compat_sigset_t seta;
@ -359,8 +347,8 @@ asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
pt_regs_clear_syscall(regs);
err |= __get_user(fpu_save, &sf->fpu_save);
if (fpu_save)
err |= restore_fpu_state32(regs, &sf->fpu_state);
if (!err && fpu_save)
err |= restore_fpu_state(regs, compat_ptr(fpu_save));
err |= copy_from_user(&seta, &sf->mask, sizeof(compat_sigset_t));
err |= __get_user(u_ss_sp, &sf->stack.ss_sp);
st.ss_sp = compat_ptr(u_ss_sp);
@ -376,6 +364,12 @@ asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
do_sigaltstack((stack_t __user *) &st, NULL, (unsigned long)sf);
set_fs(old_fs);
err |= __get_user(rwin_save, &sf->rwin_save);
if (!err && rwin_save) {
if (restore_rwin_state(compat_ptr(rwin_save)))
goto segv;
}
switch (_NSIG_WORDS) {
case 4: set.sig[3] = seta.sig[6] + (((long)seta.sig[7]) << 32);
case 3: set.sig[2] = seta.sig[4] + (((long)seta.sig[5]) << 32);
@ -433,26 +427,6 @@ static void __user *get_sigframe(struct sigaction *sa, struct pt_regs *regs, uns
return (void __user *) sp;
}
static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
unsigned long *fpregs = current_thread_info()->fpregs;
unsigned long fprs;
int err = 0;
fprs = current_thread_info()->fpsaved[0];
if (fprs & FPRS_DL)
err |= copy_to_user(&fpu->si_float_regs[0], fpregs,
(sizeof(unsigned int) * 32));
if (fprs & FPRS_DU)
err |= copy_to_user(&fpu->si_float_regs[32], fpregs+16,
(sizeof(unsigned int) * 32));
err |= __put_user(current_thread_info()->xfsr[0], &fpu->si_fsr);
err |= __put_user(current_thread_info()->gsr[0], &fpu->si_gsr);
err |= __put_user(fprs, &fpu->si_fprs);
return err;
}
/* The I-cache flush instruction only works in the primary ASI, which
* right now is the nucleus, aka. kernel space.
*
@ -515,18 +489,23 @@ static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
int signo, sigset_t *oldset)
{
struct signal_frame32 __user *sf;
int i, err, wsaved;
void __user *tail;
int sigframe_size;
u32 psr;
int i, err;
unsigned int seta[_COMPAT_NSIG_WORDS];
/* 1. Make sure everything is clean */
synchronize_user_stack();
save_and_clear_fpu();
sigframe_size = SF_ALIGNEDSZ;
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF))
sigframe_size -= sizeof(__siginfo_fpu_t);
wsaved = get_thread_wsaved();
sigframe_size = sizeof(*sf);
if (current_thread_info()->fpsaved[0] & FPRS_FEF)
sigframe_size += sizeof(__siginfo_fpu_t);
if (wsaved)
sigframe_size += sizeof(__siginfo_rwin_t);
sf = (struct signal_frame32 __user *)
get_sigframe(&ka->sa, regs, sigframe_size);
@ -534,8 +513,7 @@ static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
if (invalid_frame_pointer(sf, sigframe_size))
goto sigill;
if (get_thread_wsaved() != 0)
goto sigill;
tail = (sf + 1);
/* 2. Save the current process state */
if (test_thread_flag(TIF_32BIT)) {
@ -560,11 +538,22 @@ static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
&sf->v8plus.asi);
if (psr & PSR_EF) {
err |= save_fpu_state32(regs, &sf->fpu_state);
err |= __put_user((u64)&sf->fpu_state, &sf->fpu_save);
__siginfo_fpu_t __user *fp = tail;
tail += sizeof(*fp);
err |= save_fpu_state(regs, fp);
err |= __put_user((u64)fp, &sf->fpu_save);
} else {
err |= __put_user(0, &sf->fpu_save);
}
if (wsaved) {
__siginfo_rwin_t __user *rwp = tail;
tail += sizeof(*rwp);
err |= save_rwin_state(wsaved, rwp);
err |= __put_user((u64)rwp, &sf->rwin_save);
set_thread_wsaved(0);
} else {
err |= __put_user(0, &sf->rwin_save);
}
switch (_NSIG_WORDS) {
case 4: seta[7] = (oldset->sig[3] >> 32);
@ -580,10 +569,21 @@ static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
err |= __copy_to_user(sf->extramask, seta + 1,
(_COMPAT_NSIG_WORDS - 1) * sizeof(unsigned int));
err |= copy_in_user((u32 __user *)sf,
(u32 __user *)(regs->u_regs[UREG_FP]),
sizeof(struct reg_window32));
if (!wsaved) {
err |= copy_in_user((u32 __user *)sf,
(u32 __user *)(regs->u_regs[UREG_FP]),
sizeof(struct reg_window32));
} else {
struct reg_window *rp;
rp = &current_thread_info()->reg_window[wsaved - 1];
for (i = 0; i < 8; i++)
err |= __put_user(rp->locals[i], &sf->ss.locals[i]);
for (i = 0; i < 6; i++)
err |= __put_user(rp->ins[i], &sf->ss.ins[i]);
err |= __put_user(rp->ins[6], &sf->ss.fp);
err |= __put_user(rp->ins[7], &sf->ss.callers_pc);
}
if (err)
goto sigsegv;
@ -613,7 +613,6 @@ static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
err |= __put_user(0x91d02010, &sf->insns[1]); /*t 0x10*/
if (err)
goto sigsegv;
flush_signal_insns(address);
}
return 0;
@ -632,18 +631,23 @@ static int setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
siginfo_t *info)
{
struct rt_signal_frame32 __user *sf;
int i, err, wsaved;
void __user *tail;
int sigframe_size;
u32 psr;
int i, err;
compat_sigset_t seta;
/* 1. Make sure everything is clean */
synchronize_user_stack();
save_and_clear_fpu();
sigframe_size = RT_ALIGNEDSZ;
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF))
sigframe_size -= sizeof(__siginfo_fpu_t);
wsaved = get_thread_wsaved();
sigframe_size = sizeof(*sf);
if (current_thread_info()->fpsaved[0] & FPRS_FEF)
sigframe_size += sizeof(__siginfo_fpu_t);
if (wsaved)
sigframe_size += sizeof(__siginfo_rwin_t);
sf = (struct rt_signal_frame32 __user *)
get_sigframe(&ka->sa, regs, sigframe_size);
@ -651,8 +655,7 @@ static int setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
if (invalid_frame_pointer(sf, sigframe_size))
goto sigill;
if (get_thread_wsaved() != 0)
goto sigill;
tail = (sf + 1);
/* 2. Save the current process state */
if (test_thread_flag(TIF_32BIT)) {
@ -677,11 +680,22 @@ static int setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
&sf->v8plus.asi);
if (psr & PSR_EF) {
err |= save_fpu_state32(regs, &sf->fpu_state);
err |= __put_user((u64)&sf->fpu_state, &sf->fpu_save);
__siginfo_fpu_t __user *fp = tail;
tail += sizeof(*fp);
err |= save_fpu_state(regs, fp);
err |= __put_user((u64)fp, &sf->fpu_save);
} else {
err |= __put_user(0, &sf->fpu_save);
}
if (wsaved) {
__siginfo_rwin_t __user *rwp = tail;
tail += sizeof(*rwp);
err |= save_rwin_state(wsaved, rwp);
err |= __put_user((u64)rwp, &sf->rwin_save);
set_thread_wsaved(0);
} else {
err |= __put_user(0, &sf->rwin_save);
}
/* Update the siginfo structure. */
err |= copy_siginfo_to_user32(&sf->info, info);
@ -703,9 +717,21 @@ static int setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
}
err |= __copy_to_user(&sf->mask, &seta, sizeof(compat_sigset_t));
err |= copy_in_user((u32 __user *)sf,
(u32 __user *)(regs->u_regs[UREG_FP]),
sizeof(struct reg_window32));
if (!wsaved) {
err |= copy_in_user((u32 __user *)sf,
(u32 __user *)(regs->u_regs[UREG_FP]),
sizeof(struct reg_window32));
} else {
struct reg_window *rp;
rp = &current_thread_info()->reg_window[wsaved - 1];
for (i = 0; i < 8; i++)
err |= __put_user(rp->locals[i], &sf->ss.locals[i]);
for (i = 0; i < 6; i++)
err |= __put_user(rp->ins[i], &sf->ss.ins[i]);
err |= __put_user(rp->ins[6], &sf->ss.fp);
err |= __put_user(rp->ins[7], &sf->ss.callers_pc);
}
if (err)
goto sigsegv;

172
arch/sparc/kernel/signal_32.c
Просмотреть файл

@ -26,6 +26,8 @@
#include <asm/pgtable.h>
#include <asm/cacheflush.h> /* flush_sig_insns */
#include "sigutil.h"
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
@ -39,8 +41,8 @@ struct signal_frame {
unsigned long insns[2] __attribute__ ((aligned (8)));
unsigned int extramask[_NSIG_WORDS - 1];
unsigned int extra_size; /* Should be 0 */
__siginfo_fpu_t fpu_state;
};
__siginfo_rwin_t __user *rwin_save;
} __attribute__((aligned(8)));
struct rt_signal_frame {
struct sparc_stackf ss;
@ -51,8 +53,8 @@ struct rt_signal_frame {
unsigned int insns[2];
stack_t stack;
unsigned int extra_size; /* Should be 0 */
__siginfo_fpu_t fpu_state;
};
__siginfo_rwin_t __user *rwin_save;
} __attribute__((aligned(8)));
/* Align macros */
#define SF_ALIGNEDSZ (((sizeof(struct signal_frame) + 7) & (~7)))
@ -79,43 +81,13 @@ asmlinkage int sys_sigsuspend(old_sigset_t set)
return _sigpause_common(set);
}
static inline int
restore_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
int err;
#ifdef CONFIG_SMP
if (test_tsk_thread_flag(current, TIF_USEDFPU))
regs->psr &= ~PSR_EF;
#else
if (current == last_task_used_math) {
last_task_used_math = NULL;
regs->psr &= ~PSR_EF;
}
#endif
set_used_math();
clear_tsk_thread_flag(current, TIF_USEDFPU);
if (!access_ok(VERIFY_READ, fpu, sizeof(*fpu)))
return -EFAULT;
err = __copy_from_user(&current->thread.float_regs[0], &fpu->si_float_regs[0],
(sizeof(unsigned long) * 32));
err |= __get_user(current->thread.fsr, &fpu->si_fsr);
err |= __get_user(current->thread.fpqdepth, &fpu->si_fpqdepth);
if (current->thread.fpqdepth != 0)
err |= __copy_from_user(&current->thread.fpqueue[0],
&fpu->si_fpqueue[0],
((sizeof(unsigned long) +
(sizeof(unsigned long *)))*16));
return err;
}
asmlinkage void do_sigreturn(struct pt_regs *regs)
{
struct signal_frame __user *sf;
unsigned long up_psr, pc, npc;
sigset_t set;
__siginfo_fpu_t __user *fpu_save;
__siginfo_rwin_t __user *rwin_save;
int err;
/* Always make any pending restarted system calls return -EINTR */
@ -150,9 +122,11 @@ asmlinkage void do_sigreturn(struct pt_regs *regs)
pt_regs_clear_syscall(regs);
err |= __get_user(fpu_save, &sf->fpu_save);
if (fpu_save)
err |= restore_fpu_state(regs, fpu_save);
err |= __get_user(rwin_save, &sf->rwin_save);
if (rwin_save)
err |= restore_rwin_state(rwin_save);
/* This is pretty much atomic, no amount locking would prevent
* the races which exist anyways.
@ -180,6 +154,7 @@ asmlinkage void do_rt_sigreturn(struct pt_regs *regs)
struct rt_signal_frame __user *sf;
unsigned int psr, pc, npc;
__siginfo_fpu_t __user *fpu_save;
__siginfo_rwin_t __user *rwin_save;
mm_segment_t old_fs;
sigset_t set;
stack_t st;
@ -207,8 +182,7 @@ asmlinkage void do_rt_sigreturn(struct pt_regs *regs)
pt_regs_clear_syscall(regs);
err |= __get_user(fpu_save, &sf->fpu_save);
if (fpu_save)
if (!err && fpu_save)
err |= restore_fpu_state(regs, fpu_save);
err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t));
@ -228,6 +202,12 @@ asmlinkage void do_rt_sigreturn(struct pt_regs *regs)
do_sigaltstack((const stack_t __user *) &st, NULL, (unsigned long)sf);
set_fs(old_fs);
err |= __get_user(rwin_save, &sf->rwin_save);
if (!err && rwin_save) {
if (restore_rwin_state(rwin_save))
goto segv;
}
sigdelsetmask(&set, ~_BLOCKABLE);
spin_lock_irq(&current->sighand->siglock);
current->blocked = set;
@ -280,53 +260,23 @@ static inline void __user *get_sigframe(struct sigaction *sa, struct pt_regs *re
return (void __user *) sp;
}
static inline int
save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
int err = 0;
#ifdef CONFIG_SMP
if (test_tsk_thread_flag(current, TIF_USEDFPU)) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
regs->psr &= ~(PSR_EF);
clear_tsk_thread_flag(current, TIF_USEDFPU);
}
#else
if (current == last_task_used_math) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
last_task_used_math = NULL;
regs->psr &= ~(PSR_EF);
}
#endif
err |= __copy_to_user(&fpu->si_float_regs[0],
&current->thread.float_regs[0],
(sizeof(unsigned long) * 32));
err |= __put_user(current->thread.fsr, &fpu->si_fsr);
err |= __put_user(current->thread.fpqdepth, &fpu->si_fpqdepth);
if (current->thread.fpqdepth != 0)
err |= __copy_to_user(&fpu->si_fpqueue[0],
&current->thread.fpqueue[0],
((sizeof(unsigned long) +
(sizeof(unsigned long *)))*16));
clear_used_math();
return err;
}
static int setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
int signo, sigset_t *oldset)
{
struct signal_frame __user *sf;
int sigframe_size, err;
int sigframe_size, err, wsaved;
void __user *tail;
/* 1. Make sure everything is clean */
synchronize_user_stack();
sigframe_size = SF_ALIGNEDSZ;
if (!used_math())
sigframe_size -= sizeof(__siginfo_fpu_t);
wsaved = current_thread_info()->w_saved;
sigframe_size = sizeof(*sf);
if (used_math())
sigframe_size += sizeof(__siginfo_fpu_t);
if (wsaved)
sigframe_size += sizeof(__siginfo_rwin_t);
sf = (struct signal_frame __user *)
get_sigframe(&ka->sa, regs, sigframe_size);
@ -334,8 +284,7 @@ static int setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
if (invalid_frame_pointer(sf, sigframe_size))
goto sigill_and_return;
if (current_thread_info()->w_saved != 0)
goto sigill_and_return;
tail = sf + 1;
/* 2. Save the current process state */
err = __copy_to_user(&sf->info.si_regs, regs, sizeof(struct pt_regs));
@ -343,17 +292,34 @@ static int setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
err |= __put_user(0, &sf->extra_size);
if (used_math()) {
err |= save_fpu_state(regs, &sf->fpu_state);
err |= __put_user(&sf->fpu_state, &sf->fpu_save);
__siginfo_fpu_t __user *fp = tail;
tail += sizeof(*fp);
err |= save_fpu_state(regs, fp);
err |= __put_user(fp, &sf->fpu_save);
} else {
err |= __put_user(0, &sf->fpu_save);
}
if (wsaved) {
__siginfo_rwin_t __user *rwp = tail;
tail += sizeof(*rwp);
err |= save_rwin_state(wsaved, rwp);
err |= __put_user(rwp, &sf->rwin_save);
} else {
err |= __put_user(0, &sf->rwin_save);
}
err |= __put_user(oldset->sig[0], &sf->info.si_mask);
err |= __copy_to_user(sf->extramask, &oldset->sig[1],
(_NSIG_WORDS - 1) * sizeof(unsigned int));
err |= __copy_to_user(sf, (char *) regs->u_regs[UREG_FP],
sizeof(struct reg_window32));
if (!wsaved) {
err |= __copy_to_user(sf, (char *) regs->u_regs[UREG_FP],
sizeof(struct reg_window32));
} else {
struct reg_window32 *rp;
rp = &current_thread_info()->reg_window[wsaved - 1];
err |= __copy_to_user(sf, rp, sizeof(struct reg_window32));
}
if (err)
goto sigsegv;
@ -399,21 +365,24 @@ static int setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
int signo, sigset_t *oldset, siginfo_t *info)
{
struct rt_signal_frame __user *sf;
int sigframe_size;
int sigframe_size, wsaved;
void __user *tail;
unsigned int psr;
int err;
synchronize_user_stack();
sigframe_size = RT_ALIGNEDSZ;
if (!used_math())
sigframe_size -= sizeof(__siginfo_fpu_t);
wsaved = current_thread_info()->w_saved;
sigframe_size = sizeof(*sf);
if (used_math())
sigframe_size += sizeof(__siginfo_fpu_t);
if (wsaved)
sigframe_size += sizeof(__siginfo_rwin_t);
sf = (struct rt_signal_frame __user *)
get_sigframe(&ka->sa, regs, sigframe_size);
if (invalid_frame_pointer(sf, sigframe_size))
goto sigill;
if (current_thread_info()->w_saved != 0)
goto sigill;
tail = sf + 1;
err = __put_user(regs->pc, &sf->regs.pc);
err |= __put_user(regs->npc, &sf->regs.npc);
err |= __put_user(regs->y, &sf->regs.y);
@ -425,11 +394,21 @@ static int setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
err |= __put_user(0, &sf->extra_size);
if (psr & PSR_EF) {
err |= save_fpu_state(regs, &sf->fpu_state);
err |= __put_user(&sf->fpu_state, &sf->fpu_save);
__siginfo_fpu_t *fp = tail;
tail += sizeof(*fp);
err |= save_fpu_state(regs, fp);
err |= __put_user(fp, &sf->fpu_save);
} else {
err |= __put_user(0, &sf->fpu_save);
}
if (wsaved) {
__siginfo_rwin_t *rwp = tail;
tail += sizeof(*rwp);
err |= save_rwin_state(wsaved, rwp);
err |= __put_user(rwp, &sf->rwin_save);
} else {
err |= __put_user(0, &sf->rwin_save);
}
err |= __copy_to_user(&sf->mask, &oldset->sig[0], sizeof(sigset_t));
/* Setup sigaltstack */
@ -437,8 +416,15 @@ static int setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
err |= __put_user(sas_ss_flags(regs->u_regs[UREG_FP]), &sf->stack.ss_flags);
err |= __put_user(current->sas_ss_size, &sf->stack.ss_size);
err |= __copy_to_user(sf, (char *) regs->u_regs[UREG_FP],
sizeof(struct reg_window32));
if (!wsaved) {
err |= __copy_to_user(sf, (char *) regs->u_regs[UREG_FP],
sizeof(struct reg_window32));
} else {
struct reg_window32 *rp;
rp = &current_thread_info()->reg_window[wsaved - 1];
err |= __copy_to_user(sf, rp, sizeof(struct reg_window32));
}
err |= copy_siginfo_to_user(&sf->info, info);

108
arch/sparc/kernel/signal_64.c
Просмотреть файл

@ -34,6 +34,7 @@
#include "entry.h"
#include "systbls.h"
#include "sigutil.h"
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
@ -236,7 +237,7 @@ struct rt_signal_frame {
__siginfo_fpu_t __user *fpu_save;
stack_t stack;
sigset_t mask;
__siginfo_fpu_t fpu_state;
__siginfo_rwin_t *rwin_save;
};
static long _sigpause_common(old_sigset_t set)
@ -266,33 +267,12 @@ asmlinkage long sys_sigsuspend(old_sigset_t set)
return _sigpause_common(set);
}
static inline int
restore_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
unsigned long *fpregs = current_thread_info()->fpregs;
unsigned long fprs;
int err;
err = __get_user(fprs, &fpu->si_fprs);
fprs_write(0);
regs->tstate &= ~TSTATE_PEF;
if (fprs & FPRS_DL)
err |= copy_from_user(fpregs, &fpu->si_float_regs[0],
(sizeof(unsigned int) * 32));
if (fprs & FPRS_DU)
err |= copy_from_user(fpregs+16, &fpu->si_float_regs[32],
(sizeof(unsigned int) * 32));
err |= __get_user(current_thread_info()->xfsr[0], &fpu->si_fsr);
err |= __get_user(current_thread_info()->gsr[0], &fpu->si_gsr);
current_thread_info()->fpsaved[0] |= fprs;
return err;
}
void do_rt_sigreturn(struct pt_regs *regs)
{
struct rt_signal_frame __user *sf;
unsigned long tpc, tnpc, tstate;
__siginfo_fpu_t __user *fpu_save;
__siginfo_rwin_t __user *rwin_save;
sigset_t set;
int err;
@ -325,8 +305,8 @@ void do_rt_sigreturn(struct pt_regs *regs)
regs->tstate |= (tstate & (TSTATE_ASI | TSTATE_ICC | TSTATE_XCC));
err |= __get_user(fpu_save, &sf->fpu_save);
if (fpu_save)
err |= restore_fpu_state(regs, &sf->fpu_state);
if (!err && fpu_save)
err |= restore_fpu_state(regs, fpu_save);
err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t));
err |= do_sigaltstack(&sf->stack, NULL, (unsigned long)sf);
@ -334,6 +314,12 @@ void do_rt_sigreturn(struct pt_regs *regs)
if (err)
goto segv;
err |= __get_user(rwin_save, &sf->rwin_save);
if (!err && rwin_save) {
if (restore_rwin_state(rwin_save))
goto segv;
}
regs->tpc = tpc;
regs->tnpc = tnpc;
@ -351,34 +337,13 @@ segv:
}
/* Checks if the fp is valid */
static int invalid_frame_pointer(void __user *fp, int fplen)
static int invalid_frame_pointer(void __user *fp)
{
if (((unsigned long) fp) & 15)
return 1;
return 0;
}
static inline int
save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
unsigned long *fpregs = current_thread_info()->fpregs;
unsigned long fprs;
int err = 0;
fprs = current_thread_info()->fpsaved[0];
if (fprs & FPRS_DL)
err |= copy_to_user(&fpu->si_float_regs[0], fpregs,
(sizeof(unsigned int) * 32));
if (fprs & FPRS_DU)
err |= copy_to_user(&fpu->si_float_regs[32], fpregs+16,
(sizeof(unsigned int) * 32));
err |= __put_user(current_thread_info()->xfsr[0], &fpu->si_fsr);
err |= __put_user(current_thread_info()->gsr[0], &fpu->si_gsr);
err |= __put_user(fprs, &fpu->si_fprs);
return err;
}
static inline void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, unsigned long framesize)
{
unsigned long sp = regs->u_regs[UREG_FP] + STACK_BIAS;
@ -414,34 +379,48 @@ setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
int signo, sigset_t *oldset, siginfo_t *info)
{
struct rt_signal_frame __user *sf;
int sigframe_size, err;
int wsaved, err, sf_size;
void __user *tail;
/* 1. Make sure everything is clean */
synchronize_user_stack();
save_and_clear_fpu();
sigframe_size = sizeof(struct rt_signal_frame);
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF))
sigframe_size -= sizeof(__siginfo_fpu_t);
wsaved = get_thread_wsaved();
sf_size = sizeof(struct rt_signal_frame);
if (current_thread_info()->fpsaved[0] & FPRS_FEF)
sf_size += sizeof(__siginfo_fpu_t);
if (wsaved)
sf_size += sizeof(__siginfo_rwin_t);
sf = (struct rt_signal_frame __user *)
get_sigframe(ka, regs, sigframe_size);
if (invalid_frame_pointer (sf, sigframe_size))
get_sigframe(ka, regs, sf_size);
if (invalid_frame_pointer (sf))
goto sigill;
if (get_thread_wsaved() != 0)
goto sigill;
tail = (sf + 1);
/* 2. Save the current process state */
err = copy_to_user(&sf->regs, regs, sizeof (*regs));
if (current_thread_info()->fpsaved[0] & FPRS_FEF) {
err |= save_fpu_state(regs, &sf->fpu_state);
err |= __put_user((u64)&sf->fpu_state, &sf->fpu_save);
__siginfo_fpu_t __user *fpu_save = tail;
tail += sizeof(__siginfo_fpu_t);
err |= save_fpu_state(regs, fpu_save);
err |= __put_user((u64)fpu_save, &sf->fpu_save);
} else {
err |= __put_user(0, &sf->fpu_save);
}
if (wsaved) {
__siginfo_rwin_t __user *rwin_save = tail;
tail += sizeof(__siginfo_rwin_t);
err |= save_rwin_state(wsaved, rwin_save);
err |= __put_user((u64)rwin_save, &sf->rwin_save);
set_thread_wsaved(0);
} else {
err |= __put_user(0, &sf->rwin_save);
}
/* Setup sigaltstack */
err |= __put_user(current->sas_ss_sp, &sf->stack.ss_sp);
@ -450,10 +429,17 @@ setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
err |= copy_to_user(&sf->mask, oldset, sizeof(sigset_t));
err |= copy_in_user((u64 __user *)sf,
(u64 __user *)(regs->u_regs[UREG_FP]+STACK_BIAS),
sizeof(struct reg_window));
if (!wsaved) {
err |= copy_in_user((u64 __user *)sf,
(u64 __user *)(regs->u_regs[UREG_FP] +
STACK_BIAS),
sizeof(struct reg_window));
} else {
struct reg_window *rp;
rp = &current_thread_info()->reg_window[wsaved - 1];
err |= copy_to_user(sf, rp, sizeof(struct reg_window));
}
if (info)
err |= copy_siginfo_to_user(&sf->info, info);
else {

9
arch/sparc/kernel/sigutil.h Normal file
Просмотреть файл

@ -0,0 +1,9 @@
#ifndef _SIGUTIL_H
#define _SIGUTIL_H
int save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu);
int restore_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu);
int save_rwin_state(int wsaved, __siginfo_rwin_t __user *rwin);
int restore_rwin_state(__siginfo_rwin_t __user *rp);
#endif /* _SIGUTIL_H */

120
arch/sparc/kernel/sigutil_32.c Normal file
Просмотреть файл

@ -0,0 +1,120 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/thread_info.h>
#include <linux/uaccess.h>
#include <linux/sched.h>
#include <asm/sigcontext.h>
#include <asm/fpumacro.h>
#include <asm/ptrace.h>
#include "sigutil.h"
int save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
int err = 0;
#ifdef CONFIG_SMP
if (test_tsk_thread_flag(current, TIF_USEDFPU)) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
regs->psr &= ~(PSR_EF);
clear_tsk_thread_flag(current, TIF_USEDFPU);
}
#else
if (current == last_task_used_math) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
last_task_used_math = NULL;
regs->psr &= ~(PSR_EF);
}
#endif
err |= __copy_to_user(&fpu->si_float_regs[0],
&current->thread.float_regs[0],
(sizeof(unsigned long) * 32));
err |= __put_user(current->thread.fsr, &fpu->si_fsr);
err |= __put_user(current->thread.fpqdepth, &fpu->si_fpqdepth);
if (current->thread.fpqdepth != 0)
err |= __copy_to_user(&fpu->si_fpqueue[0],
&current->thread.fpqueue[0],
((sizeof(unsigned long) +
(sizeof(unsigned long *)))*16));
clear_used_math();
return err;
}
int restore_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
int err;
#ifdef CONFIG_SMP
if (test_tsk_thread_flag(current, TIF_USEDFPU))
regs->psr &= ~PSR_EF;
#else
if (current == last_task_used_math) {
last_task_used_math = NULL;
regs->psr &= ~PSR_EF;
}
#endif
set_used_math();
clear_tsk_thread_flag(current, TIF_USEDFPU);
if (!access_ok(VERIFY_READ, fpu, sizeof(*fpu)))
return -EFAULT;
err = __copy_from_user(&current->thread.float_regs[0], &fpu->si_float_regs[0],
(sizeof(unsigned long) * 32));
err |= __get_user(current->thread.fsr, &fpu->si_fsr);
err |= __get_user(current->thread.fpqdepth, &fpu->si_fpqdepth);
if (current->thread.fpqdepth != 0)
err |= __copy_from_user(&current->thread.fpqueue[0],
&fpu->si_fpqueue[0],
((sizeof(unsigned long) +
(sizeof(unsigned long *)))*16));
return err;
}
int save_rwin_state(int wsaved, __siginfo_rwin_t __user *rwin)
{
int i, err = __put_user(wsaved, &rwin->wsaved);
for (i = 0; i < wsaved; i++) {
struct reg_window32 *rp;
unsigned long fp;
rp = &current_thread_info()->reg_window[i];
fp = current_thread_info()->rwbuf_stkptrs[i];
err |= copy_to_user(&rwin->reg_window[i], rp,
sizeof(struct reg_window32));
err |= __put_user(fp, &rwin->rwbuf_stkptrs[i]);
}
return err;
}
int restore_rwin_state(__siginfo_rwin_t __user *rp)
{
struct thread_info *t = current_thread_info();
int i, wsaved, err;
__get_user(wsaved, &rp->wsaved);
if (wsaved > NSWINS)
return -EFAULT;
err = 0;
for (i = 0; i < wsaved; i++) {
err |= copy_from_user(&t->reg_window[i],
&rp->reg_window[i],
sizeof(struct reg_window32));
err |= __get_user(t->rwbuf_stkptrs[i],
&rp->rwbuf_stkptrs[i]);
}
if (err)
return err;
t->w_saved = wsaved;
synchronize_user_stack();
if (t->w_saved)
return -EFAULT;
return 0;
}

93
arch/sparc/kernel/sigutil_64.c Normal file
Просмотреть файл

@ -0,0 +1,93 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/thread_info.h>
#include <linux/uaccess.h>
#include <asm/sigcontext.h>
#include <asm/fpumacro.h>
#include <asm/ptrace.h>
#include "sigutil.h"
int save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
unsigned long *fpregs = current_thread_info()->fpregs;
unsigned long fprs;
int err = 0;
fprs = current_thread_info()->fpsaved[0];
if (fprs & FPRS_DL)
err |= copy_to_user(&fpu->si_float_regs[0], fpregs,
(sizeof(unsigned int) * 32));
if (fprs & FPRS_DU)
err |= copy_to_user(&fpu->si_float_regs[32], fpregs+16,
(sizeof(unsigned int) * 32));
err |= __put_user(current_thread_info()->xfsr[0], &fpu->si_fsr);
err |= __put_user(current_thread_info()->gsr[0], &fpu->si_gsr);
err |= __put_user(fprs, &fpu->si_fprs);
return err;
}
int restore_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
{
unsigned long *fpregs = current_thread_info()->fpregs;
unsigned long fprs;
int err;
err = __get_user(fprs, &fpu->si_fprs);
fprs_write(0);
regs->tstate &= ~TSTATE_PEF;
if (fprs & FPRS_DL)
err |= copy_from_user(fpregs, &fpu->si_float_regs[0],
(sizeof(unsigned int) * 32));
if (fprs & FPRS_DU)
err |= copy_from_user(fpregs+16, &fpu->si_float_regs[32],
(sizeof(unsigned int) * 32));
err |= __get_user(current_thread_info()->xfsr[0], &fpu->si_fsr);
err |= __get_user(current_thread_info()->gsr[0], &fpu->si_gsr);
current_thread_info()->fpsaved[0] |= fprs;
return err;
}
int save_rwin_state(int wsaved, __siginfo_rwin_t __user *rwin)
{
int i, err = __put_user(wsaved, &rwin->wsaved);
for (i = 0; i < wsaved; i++) {
struct reg_window *rp = &current_thread_info()->reg_window[i];
unsigned long fp = current_thread_info()->rwbuf_stkptrs[i];
err |= copy_to_user(&rwin->reg_window[i], rp,
sizeof(struct reg_window));
err |= __put_user(fp, &rwin->rwbuf_stkptrs[i]);
}
return err;
}
int restore_rwin_state(__siginfo_rwin_t __user *rp)
{
struct thread_info *t = current_thread_info();
int i, wsaved, err;
__get_user(wsaved, &rp->wsaved);
if (wsaved > NSWINS)
return -EFAULT;
err = 0;
for (i = 0; i < wsaved; i++) {
err |= copy_from_user(&t->reg_window[i],
&rp->reg_window[i],
sizeof(struct reg_window));
err |= __get_user(t->rwbuf_stkptrs[i],
&rp->rwbuf_stkptrs[i]);
}
if (err)
return err;
set_thread_wsaved(wsaved);
synchronize_user_stack();
if (get_thread_wsaved())
return -EFAULT;
return 0;
}

1
arch/sparc/kernel/sys32.S
Просмотреть файл

@ -81,7 +81,6 @@ SIGN2(sys32_fadvise64, compat_sys_fadvise64, %o0, %o4)
SIGN2(sys32_fadvise64_64, compat_sys_fadvise64_64, %o0, %o5)
SIGN2(sys32_bdflush, sys_bdflush, %o0, %o1)
SIGN1(sys32_mlockall, sys_mlockall, %o0)
SIGN1(sys32_nfsservctl, compat_sys_nfsservctl, %o0)
SIGN1(sys32_clock_nanosleep, compat_sys_clock_nanosleep, %o1)
SIGN1(sys32_timer_settime, compat_sys_timer_settime, %o1)
SIGN1(sys32_io_submit, compat_sys_io_submit, %o1)

2
arch/sparc/kernel/systbls_32.S
Просмотреть файл

@ -67,7 +67,7 @@ sys_call_table:
/*235*/ .long sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys_mlockall
/*240*/ .long sys_munlockall, sys_sched_setparam, sys_sched_getparam, sys_sched_setscheduler, sys_sched_getscheduler
/*245*/ .long sys_sched_yield, sys_sched_get_priority_max, sys_sched_get_priority_min, sys_sched_rr_get_interval, sys_nanosleep
/*250*/ .long sys_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nfsservctl
/*250*/ .long sys_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_ni_syscall
/*255*/ .long sys_sync_file_range, sys_clock_settime, sys_clock_gettime, sys_clock_getres, sys_clock_nanosleep
/*260*/ .long sys_sched_getaffinity, sys_sched_setaffinity, sys_timer_settime, sys_timer_gettime, sys_timer_getoverrun
/*265*/ .long sys_timer_delete, sys_timer_create, sys_nis_syscall, sys_io_setup, sys_io_destroy

2
arch/sparc/kernel/systbls_64.S
Просмотреть файл

@ -145,7 +145,7 @@ sys_call_table:
.word sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys_mlockall
/*240*/ .word sys_munlockall, sys_sched_setparam, sys_sched_getparam, sys_sched_setscheduler, sys_sched_getscheduler
.word sys_sched_yield, sys_sched_get_priority_max, sys_sched_get_priority_min, sys_sched_rr_get_interval, sys_nanosleep
/*250*/ .word sys_64_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nfsservctl
/*250*/ .word sys_64_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nis_syscall
.word sys_sync_file_range, sys_clock_settime, sys_clock_gettime, sys_clock_getres, sys_clock_nanosleep
/*260*/ .word sys_sched_getaffinity, sys_sched_setaffinity, sys_timer_settime, sys_timer_gettime, sys_timer_getoverrun
.word sys_timer_delete, sys_timer_create, sys_ni_syscall, sys_io_setup, sys_io_destroy

2
arch/x86/ia32/ia32entry.S
Просмотреть файл

@ -672,7 +672,7 @@ ia32_sys_call_table:
.quad sys32_vm86_warning /* vm86 */
.quad quiet_ni_syscall /* query_module */
.quad sys_poll
.quad compat_sys_nfsservctl
.quad quiet_ni_syscall /* old nfsservctl */
.quad sys_setresgid16 /* 170 */
.quad sys_getresgid16
.quad sys_prctl

2
arch/x86/include/asm/unistd_64.h
Просмотреть файл

@ -414,7 +414,7 @@ __SYSCALL(__NR_query_module, sys_ni_syscall)
__SYSCALL(__NR_quotactl, sys_quotactl)
#define __NR_nfsservctl 180
__SYSCALL(__NR_nfsservctl, sys_nfsservctl)
__SYSCALL(__NR_nfsservctl, sys_ni_syscall)
/* reserved for LiS/STREAMS */
#define __NR_getpmsg 181

1
arch/x86/kernel/apic/x2apic_uv_x.c
Просмотреть файл

@ -207,7 +207,6 @@ static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_ri
((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
APIC_DM_INIT;
uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
mdelay(10);
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |

2
arch/x86/kernel/cpu/mtrr/main.c
Просмотреть файл

@ -149,7 +149,6 @@ struct set_mtrr_data {
*/
static int mtrr_rendezvous_handler(void *info)
{
#ifdef CONFIG_SMP
struct set_mtrr_data *data = info;
/*
@ -171,7 +170,6 @@ static int mtrr_rendezvous_handler(void *info)
} else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
mtrr_if->set_all();
}
#endif
return 0;
}

8
arch/x86/kernel/entry_32.S
Просмотреть файл

@ -54,6 +54,7 @@
#include <asm/ftrace.h>
#include <asm/irq_vectors.h>
#include <asm/cpufeature.h>
#include <asm/alternative-asm.h>
/* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */
#include <linux/elf-em.h>
@ -873,12 +874,7 @@ ENTRY(simd_coprocessor_error)
661: pushl_cfi $do_general_protection
662:
.section .altinstructions,"a"
.balign 4
.long 661b
.long 663f
.word X86_FEATURE_XMM
.byte 662b-661b
.byte 664f-663f
altinstruction_entry 661b, 663f, X86_FEATURE_XMM, 662b-661b, 664f-663f
.previous
.section .altinstr_replacement,"ax"
663: pushl $do_simd_coprocessor_error

2
arch/x86/kernel/syscall_table_32.S
Просмотреть файл

@ -168,7 +168,7 @@ ENTRY(sys_call_table)
.long ptregs_vm86
.long sys_ni_syscall /* Old sys_query_module */
.long sys_poll
.long sys_nfsservctl
.long sys_ni_syscall /* Old nfsservctl */
.long sys_setresgid16 /* 170 */
.long sys_getresgid16
.long sys_prctl

4
arch/x86/platform/mrst/mrst.c
Просмотреть файл

@ -689,7 +689,9 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
irq_attr.trigger = 1;
irq_attr.polarity = 1;
io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
}
} else
pentry->irq = 0; /* No irq */
switch (pentry->type) {
case SFI_DEV_TYPE_IPC:
/* ID as IRQ is a hack that will go away */

4
arch/x86/platform/olpc/olpc.c
Просмотреть файл

@ -161,13 +161,13 @@ restart:
if (inbuf && inlen) {
/* write data to EC */
for (i = 0; i < inlen; i++) {
pr_devel("olpc-ec: sending cmd arg 0x%x\n", inbuf[i]);
outb(inbuf[i], 0x68);
if (wait_on_ibf(0x6c, 0)) {
printk(KERN_ERR "olpc-ec: timeout waiting for"
" EC accept data!\n");
goto err;
}
pr_devel("olpc-ec: sending cmd arg 0x%x\n", inbuf[i]);
outb(inbuf[i], 0x68);
}
}
if (outbuf && outlen) {

2
arch/x86/vdso/vdso32/sysenter.S
Просмотреть файл

@ -43,7 +43,7 @@ __kernel_vsyscall:
.space 7,0x90
/* 14: System call restart point is here! (SYSENTER_RETURN-2) */
jmp .Lenter_kernel
int $0x80
/* 16: System call normal return point is here! */
VDSO32_SYSENTER_RETURN: /* Symbol used by sysenter.c via vdso32-syms.h */
pop %ebp

2
arch/xtensa/include/asm/unistd.h
Просмотреть файл

@ -455,7 +455,7 @@ __SYSCALL(203, sys_reboot, 3)
#define __NR_quotactl 204
__SYSCALL(204, sys_quotactl, 4)
#define __NR_nfsservctl 205
__SYSCALL(205, sys_nfsservctl, 3)
__SYSCALL(205, sys_ni_syscall, 0)
#define __NR__sysctl 206
__SYSCALL(206, sys_sysctl, 1)
#define __NR_bdflush 207

1
drivers/base/devres.c
Просмотреть файл

@ -397,6 +397,7 @@ static int remove_nodes(struct device *dev,
static int release_nodes(struct device *dev, struct list_head *first,
struct list_head *end, unsigned long flags)
__releases(&dev->devres_lock)
{
LIST_HEAD(todo);
int cnt;

2
drivers/base/devtmpfs.c
Просмотреть файл

@ -376,7 +376,7 @@ int devtmpfs_mount(const char *mntdir)
return err;
}
static __initdata DECLARE_COMPLETION(setup_done);
static DECLARE_COMPLETION(setup_done);
static int handle(const char *name, mode_t mode, struct device *dev)
{

11
drivers/base/firmware_class.c
Просмотреть файл

@ -521,11 +521,6 @@ static int _request_firmware(const struct firmware **firmware_p,
if (!firmware_p)
return -EINVAL;
if (WARN_ON(usermodehelper_is_disabled())) {
dev_err(device, "firmware: %s will not be loaded\n", name);
return -EBUSY;
}
*firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
if (!firmware) {
dev_err(device, "%s: kmalloc(struct firmware) failed\n",
@ -539,6 +534,12 @@ static int _request_firmware(const struct firmware **firmware_p,
return 0;
}
if (WARN_ON(usermodehelper_is_disabled())) {
dev_err(device, "firmware: %s will not be loaded\n", name);
retval = -EBUSY;
goto out;
}
if (uevent)
dev_dbg(device, "firmware: requesting %s\n", name);

2
drivers/base/platform.c
Просмотреть файл

@ -33,7 +33,7 @@ EXPORT_SYMBOL_GPL(platform_bus);
/**
* arch_setup_pdev_archdata - Allow manipulation of archdata before its used
* @dev: platform device
* @pdev: platform device
*
* This is called before platform_device_add() such that any pdev_archdata may
* be setup before the platform_notifier is called. So if a user needs to

40
drivers/base/power/clock_ops.c
Просмотреть файл

@ -19,7 +19,7 @@
struct pm_clk_data {
struct list_head clock_list;
struct mutex lock;
spinlock_t lock;
};
enum pce_status {
@ -73,9 +73,9 @@ int pm_clk_add(struct device *dev, const char *con_id)
}
}
mutex_lock(&pcd->lock);
spin_lock_irq(&pcd->lock);
list_add_tail(&ce->node, &pcd->clock_list);
mutex_unlock(&pcd->lock);
spin_unlock_irq(&pcd->lock);
return 0;
}
@ -83,8 +83,8 @@ int pm_clk_add(struct device *dev, const char *con_id)
* __pm_clk_remove - Destroy PM clock entry.
* @ce: PM clock entry to destroy.
*
* This routine must be called under the mutex protecting the PM list of clocks
* corresponding the the @ce's device.
* This routine must be called under the spinlock protecting the PM list of
* clocks corresponding the the @ce's device.
*/
static void __pm_clk_remove(struct pm_clock_entry *ce)
{
@ -123,7 +123,7 @@ void pm_clk_remove(struct device *dev, const char *con_id)
if (!pcd)
return;
mutex_lock(&pcd->lock);
spin_lock_irq(&pcd->lock);
list_for_each_entry(ce, &pcd->clock_list, node) {
if (!con_id && !ce->con_id) {
@ -137,7 +137,7 @@ void pm_clk_remove(struct device *dev, const char *con_id)
}
}
mutex_unlock(&pcd->lock);
spin_unlock_irq(&pcd->lock);
}
/**
@ -158,7 +158,7 @@ int pm_clk_init(struct device *dev)
}
INIT_LIST_HEAD(&pcd->clock_list);
mutex_init(&pcd->lock);
spin_lock_init(&pcd->lock);
dev->power.subsys_data = pcd;
return 0;
}
@ -181,12 +181,12 @@ void pm_clk_destroy(struct device *dev)
dev->power.subsys_data = NULL;
mutex_lock(&pcd->lock);
spin_lock_irq(&pcd->lock);
list_for_each_entry_safe_reverse(ce, c, &pcd->clock_list, node)
__pm_clk_remove(ce);
mutex_unlock(&pcd->lock);
spin_unlock_irq(&pcd->lock);
kfree(pcd);
}
@ -220,13 +220,14 @@ int pm_clk_suspend(struct device *dev)
{
struct pm_clk_data *pcd = __to_pcd(dev);
struct pm_clock_entry *ce;
unsigned long flags;
dev_dbg(dev, "%s()\n", __func__);
if (!pcd)
return 0;
mutex_lock(&pcd->lock);
spin_lock_irqsave(&pcd->lock, flags);
list_for_each_entry_reverse(ce, &pcd->clock_list, node) {
if (ce->status == PCE_STATUS_NONE)
@ -238,7 +239,7 @@ int pm_clk_suspend(struct device *dev)
}
}
mutex_unlock(&pcd->lock);
spin_unlock_irqrestore(&pcd->lock, flags);
return 0;
}
@ -251,13 +252,14 @@ int pm_clk_resume(struct device *dev)
{
struct pm_clk_data *pcd = __to_pcd(dev);
struct pm_clock_entry *ce;
unsigned long flags;
dev_dbg(dev, "%s()\n", __func__);
if (!pcd)
return 0;
mutex_lock(&pcd->lock);
spin_lock_irqsave(&pcd->lock, flags);
list_for_each_entry(ce, &pcd->clock_list, node) {
if (ce->status == PCE_STATUS_NONE)
@ -269,7 +271,7 @@ int pm_clk_resume(struct device *dev)
}
}
mutex_unlock(&pcd->lock);
spin_unlock_irqrestore(&pcd->lock, flags);
return 0;
}
@ -344,6 +346,7 @@ int pm_clk_suspend(struct device *dev)
{
struct pm_clk_data *pcd = __to_pcd(dev);
struct pm_clock_entry *ce;
unsigned long flags;
dev_dbg(dev, "%s()\n", __func__);
@ -351,12 +354,12 @@ int pm_clk_suspend(struct device *dev)
if (!pcd || !dev->driver)
return 0;
mutex_lock(&pcd->lock);
spin_lock_irqsave(&pcd->lock, flags);
list_for_each_entry_reverse(ce, &pcd->clock_list, node)
clk_disable(ce->clk);
mutex_unlock(&pcd->lock);
spin_unlock_irqrestore(&pcd->lock, flags);
return 0;
}
@ -369,6 +372,7 @@ int pm_clk_resume(struct device *dev)
{
struct pm_clk_data *pcd = __to_pcd(dev);
struct pm_clock_entry *ce;
unsigned long flags;
dev_dbg(dev, "%s()\n", __func__);
@ -376,12 +380,12 @@ int pm_clk_resume(struct device *dev)
if (!pcd || !dev->driver)
return 0;
mutex_lock(&pcd->lock);
spin_lock_irqsave(&pcd->lock, flags);
list_for_each_entry(ce, &pcd->clock_list, node)
clk_enable(ce->clk);
mutex_unlock(&pcd->lock);
spin_unlock_irqrestore(&pcd->lock, flags);
return 0;
}

5
drivers/char/msm_smd_pkt.c
Просмотреть файл

@ -379,9 +379,8 @@ static int __init smd_pkt_init(void)
for (i = 0; i < NUM_SMD_PKT_PORTS; ++i) {
smd_pkt_devp[i] = kzalloc(sizeof(struct smd_pkt_dev),
GFP_KERNEL);
if (IS_ERR(smd_pkt_devp[i])) {
r = PTR_ERR(smd_pkt_devp[i]);
pr_err("kmalloc() failed %d\n", r);
if (!smd_pkt_devp[i]) {
pr_err("kmalloc() failed\n");
goto clean_cdevs;
}

4
drivers/firewire/sbp2.c
Просмотреть файл

@ -1198,6 +1198,10 @@ static int sbp2_remove(struct device *dev)
{
struct fw_unit *unit = fw_unit(dev);
struct sbp2_target *tgt = dev_get_drvdata(&unit->device);
struct sbp2_logical_unit *lu;
list_for_each_entry(lu, &tgt->lu_list, link)
cancel_delayed_work_sync(&lu->work);
sbp2_target_put(tgt);
return 0;

2
drivers/firmware/google/gsmi.c
Просмотреть файл

@ -420,7 +420,7 @@ static efi_status_t gsmi_get_next_variable(unsigned long *name_size,
static efi_status_t gsmi_set_variable(efi_char16_t *name,
efi_guid_t *vendor,
unsigned long attr,
u32 attr,
unsigned long data_size,
void *data)
{

4
drivers/gpu/drm/i915/intel_display.c
Просмотреть файл

@ -878,7 +878,7 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
int pp_reg, lvds_reg;
u32 val;
enum pipe panel_pipe = PIPE_A;
bool locked = locked;
bool locked = true;
if (HAS_PCH_SPLIT(dev_priv->dev)) {
pp_reg = PCH_PP_CONTROL;
@ -7238,8 +7238,6 @@ static void intel_setup_outputs(struct drm_device *dev)
intel_encoder_clones(dev, encoder->clone_mask);
}
intel_panel_setup_backlight(dev);
/* disable all the possible outputs/crtcs before entering KMS mode */
drm_helper_disable_unused_functions(dev);
}

10
drivers/gpu/drm/radeon/radeon_connectors.c
Просмотреть файл

@ -466,6 +466,16 @@ static bool radeon_connector_needs_extended_probe(struct radeon_device *dev,
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
return true;
}
/* TOSHIBA Satellite L300D with ATI Mobility Radeon x1100
* (RS690M) sends data to i2c bus for a HDMI connector that
* is not implemented */
if ((dev->pdev->device == 0x791f) &&
(dev->pdev->subsystem_vendor == 0x1179) &&
(dev->pdev->subsystem_device == 0xff68)) {
if ((connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
return true;
}
/* Default: no EDID header probe required for DDC probing */
return false;

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