drm/radeon: handle broken disabled rb mask gracefully
If the disabled rb mask register is not properly initialized program a sane default based on the number of RBs for the asic. This avoids a potential divide by 0 when calculating the backend mask. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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55b615aec6
Коммит
cedb655a3a
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@ -2261,6 +2261,14 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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}
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/* enabled rb are just the one not disabled :) */
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disabled_rb_mask = tmp;
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tmp = 0;
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for (i = 0; i < rdev->config.evergreen.max_backends; i++)
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tmp |= (1 << i);
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/* if all the backends are disabled, fix it up here */
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if ((disabled_rb_mask & tmp) == tmp) {
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for (i = 0; i < rdev->config.evergreen.max_backends; i++)
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disabled_rb_mask &= ~(1 << i);
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}
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WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
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WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
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@ -615,6 +615,14 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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}
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/* enabled rb are just the one not disabled :) */
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disabled_rb_mask = tmp;
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tmp = 0;
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for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
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tmp |= (1 << i);
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/* if all the backends are disabled, fix it up here */
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if ((disabled_rb_mask & tmp) == tmp) {
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for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
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disabled_rb_mask &= ~(1 << i);
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}
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WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
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WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
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