xhci: Fix memory leak when caching protocol extended capability PSI tables - take 2
xhci driver assumed that xHC controllers have at most one custom
supported speed table (PSI) for all usb 3.x ports.
Memory was allocated for one PSI table under the xhci hub structure.
Turns out this is not the case, some controllers have a separate
"supported protocol capability" entry with a PSI table for each port.
This means each usb3 roothub port can in theory support different custom
speeds.
To solve this, cache all supported protocol capabilities with their PSI
tables in an array, and add pointers to the xhci port structure so that
every port points to its capability entry in the array.
When creating the SuperSpeedPlus USB Device Capability BOS descriptor
for the xhci USB 3.1 roothub we for now will use only data from the
first USB 3.1 capable protocol capability entry in the array.
This could be improved later, this patch focuses resolving
the memory leak.
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reported-by: Sajja Venkateswara Rao <VenkateswaraRao.Sajja@amd.com>
Fixes: 47189098f8 ("xhci: parse xhci protocol speed ID list for usb 3.1 usage")
Cc: stable <stable@vger.kernel.org> # v4.4+
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20200211150158.14475-1-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mathias Nyman
Greg Kroah-Hartman
Родитель
67f68f977a
Коммит
cf0ee7c60c
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@ -55,6 +55,7 @@ static u8 usb_bos_descriptor [] = {
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static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
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u16 wLength)
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{
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struct xhci_port_cap *port_cap = NULL;
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int i, ssa_count;
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u32 temp;
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u16 desc_size, ssp_cap_size, ssa_size = 0;
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@ -64,16 +65,24 @@ static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
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ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
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/* does xhci support USB 3.1 Enhanced SuperSpeed */
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if (xhci->usb3_rhub.min_rev >= 0x01) {
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for (i = 0; i < xhci->num_port_caps; i++) {
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if (xhci->port_caps[i].maj_rev == 0x03 &&
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xhci->port_caps[i].min_rev >= 0x01) {
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usb3_1 = true;
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port_cap = &xhci->port_caps[i];
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break;
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}
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}
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if (usb3_1) {
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/* does xhci provide a PSI table for SSA speed attributes? */
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if (xhci->usb3_rhub.psi_count) {
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if (port_cap->psi_count) {
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/* two SSA entries for each unique PSI ID, RX and TX */
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ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
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ssa_count = port_cap->psi_uid_count * 2;
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ssa_size = ssa_count * sizeof(u32);
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ssp_cap_size -= 16; /* skip copying the default SSA */
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}
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desc_size += ssp_cap_size;
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usb3_1 = true;
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}
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memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
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@ -99,7 +108,7 @@ static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
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}
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/* If PSI table exists, add the custom speed attributes from it */
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if (usb3_1 && xhci->usb3_rhub.psi_count) {
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if (usb3_1 && port_cap->psi_count) {
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u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
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int offset;
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@ -111,7 +120,7 @@ static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
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/* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
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bm_attrib = (ssa_count - 1) & 0x1f;
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bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
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bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
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put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
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if (wLength < desc_size + ssa_size)
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@ -124,8 +133,8 @@ static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
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* USB 3.1 requires two SSA entries (RX and TX) for every link
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*/
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offset = desc_size;
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for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
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psi = xhci->usb3_rhub.psi[i];
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for (i = 0; i < port_cap->psi_count; i++) {
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psi = port_cap->psi[i];
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psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
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psi_exp = XHCI_EXT_PORT_PSIE(psi);
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psi_mant = XHCI_EXT_PORT_PSIM(psi);
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@ -1915,17 +1915,17 @@ no_bw:
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xhci->usb3_rhub.num_ports = 0;
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xhci->num_active_eps = 0;
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kfree(xhci->usb2_rhub.ports);
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kfree(xhci->usb2_rhub.psi);
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kfree(xhci->usb3_rhub.ports);
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kfree(xhci->usb3_rhub.psi);
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kfree(xhci->hw_ports);
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kfree(xhci->rh_bw);
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kfree(xhci->ext_caps);
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for (i = 0; i < xhci->num_port_caps; i++)
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kfree(xhci->port_caps[i].psi);
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kfree(xhci->port_caps);
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xhci->num_port_caps = 0;
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xhci->usb2_rhub.ports = NULL;
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xhci->usb2_rhub.psi = NULL;
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xhci->usb3_rhub.ports = NULL;
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xhci->usb3_rhub.psi = NULL;
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xhci->hw_ports = NULL;
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xhci->rh_bw = NULL;
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xhci->ext_caps = NULL;
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@ -2126,6 +2126,7 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
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u8 major_revision, minor_revision;
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struct xhci_hub *rhub;
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struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
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struct xhci_port_cap *port_cap;
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temp = readl(addr);
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major_revision = XHCI_EXT_PORT_MAJOR(temp);
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@ -2160,31 +2161,39 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
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/* WTF? "Valid values are ‘1’ to MaxPorts" */
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return;
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rhub->psi_count = XHCI_EXT_PORT_PSIC(temp);
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if (rhub->psi_count) {
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rhub->psi = kcalloc_node(rhub->psi_count, sizeof(*rhub->psi),
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GFP_KERNEL, dev_to_node(dev));
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if (!rhub->psi)
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rhub->psi_count = 0;
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port_cap = &xhci->port_caps[xhci->num_port_caps++];
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if (xhci->num_port_caps > max_caps)
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return;
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rhub->psi_uid_count++;
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for (i = 0; i < rhub->psi_count; i++) {
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rhub->psi[i] = readl(addr + 4 + i);
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port_cap->maj_rev = major_revision;
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port_cap->min_rev = minor_revision;
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port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
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if (port_cap->psi_count) {
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port_cap->psi = kcalloc_node(port_cap->psi_count,
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sizeof(*port_cap->psi),
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GFP_KERNEL, dev_to_node(dev));
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if (!port_cap->psi)
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port_cap->psi_count = 0;
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port_cap->psi_uid_count++;
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for (i = 0; i < port_cap->psi_count; i++) {
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port_cap->psi[i] = readl(addr + 4 + i);
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/* count unique ID values, two consecutive entries can
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* have the same ID if link is assymetric
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*/
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if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) !=
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XHCI_EXT_PORT_PSIV(rhub->psi[i - 1])))
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rhub->psi_uid_count++;
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if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) !=
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XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
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port_cap->psi_uid_count++;
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xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
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XHCI_EXT_PORT_PSIV(rhub->psi[i]),
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XHCI_EXT_PORT_PSIE(rhub->psi[i]),
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XHCI_EXT_PORT_PLT(rhub->psi[i]),
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XHCI_EXT_PORT_PFD(rhub->psi[i]),
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XHCI_EXT_PORT_LP(rhub->psi[i]),
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XHCI_EXT_PORT_PSIM(rhub->psi[i]));
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XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
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XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
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XHCI_EXT_PORT_PLT(port_cap->psi[i]),
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XHCI_EXT_PORT_PFD(port_cap->psi[i]),
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XHCI_EXT_PORT_LP(port_cap->psi[i]),
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XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
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}
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}
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/* cache usb2 port capabilities */
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@ -2219,6 +2228,7 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
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continue;
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}
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hw_port->rhub = rhub;
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hw_port->port_cap = port_cap;
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rhub->num_ports++;
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}
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/* FIXME: Should we disable ports not in the Extended Capabilities? */
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@ -2309,6 +2319,11 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
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if (!xhci->ext_caps)
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return -ENOMEM;
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xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps),
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flags, dev_to_node(dev));
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if (!xhci->port_caps)
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return -ENOMEM;
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offset = cap_start;
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while (offset) {
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@ -1702,12 +1702,20 @@ struct xhci_bus_state {
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* Intel Lynx Point LP xHCI host.
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*/
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#define XHCI_MAX_REXIT_TIMEOUT_MS 20
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struct xhci_port_cap {
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u32 *psi; /* array of protocol speed ID entries */
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u8 psi_count;
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u8 psi_uid_count;
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u8 maj_rev;
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u8 min_rev;
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};
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struct xhci_port {
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__le32 __iomem *addr;
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int hw_portnum;
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int hcd_portnum;
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struct xhci_hub *rhub;
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struct xhci_port_cap *port_cap;
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};
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struct xhci_hub {
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@ -1719,9 +1727,6 @@ struct xhci_hub {
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/* supported prococol extended capabiliy values */
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u8 maj_rev;
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u8 min_rev;
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u32 *psi; /* array of protocol speed ID entries */
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u8 psi_count;
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u8 psi_uid_count;
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};
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/* There is one xhci_hcd structure per controller */
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@ -1880,6 +1885,9 @@ struct xhci_hcd {
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/* cached usb2 extened protocol capabilites */
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u32 *ext_caps;
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unsigned int num_ext_caps;
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/* cached extended protocol port capabilities */
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struct xhci_port_cap *port_caps;
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unsigned int num_port_caps;
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/* Compliance Mode Recovery Data */
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struct timer_list comp_mode_recovery_timer;
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u32 port_status_u0;
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