ARM: 6679/1: SPEAr: make clk API functions more generic
- Add a dummy clk_set_rate() function. This is required for compilation of a few drivers. - Make functions in plat-spear/clock.c more generic over all SPEAr platforms. - Add div_factor in struct clk for clks with .recalc = follow_parent - Change type of register pointers to void __iomem * Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
viresh kumar
Russell King
Родитель
5c881d9ae9
Коммит
cf285434ac
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@ -39,10 +39,25 @@ static struct clk rtc_clk = {
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};
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/* clock derived from 24 MHz osc clk */
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/* pll masks structure */
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static struct pll_clk_masks pll1_masks = {
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.mode_mask = PLL_MODE_MASK,
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.mode_shift = PLL_MODE_SHIFT,
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.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
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.norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
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.dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
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.dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
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.div_p_mask = PLL_DIV_P_MASK,
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.div_p_shift = PLL_DIV_P_SHIFT,
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.div_n_mask = PLL_DIV_N_MASK,
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.div_n_shift = PLL_DIV_N_SHIFT,
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};
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/* pll1 configuration structure */
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static struct pll_clk_config pll1_config = {
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.mode_reg = PLL1_CTR,
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.cfg_reg = PLL1_FRQ,
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.masks = &pll1_masks,
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};
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/* PLL1 clock */
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@ -50,7 +65,7 @@ static struct clk pll1_clk = {
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.pclk = &osc_24m_clk,
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.en_reg = PLL1_CTR,
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.en_reg_bit = PLL_ENABLE,
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.recalc = &pll1_clk_recalc,
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.recalc = &pll_clk_recalc,
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.private_data = &pll1_config,
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};
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@ -76,11 +91,16 @@ static struct clk cpu_clk = {
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.recalc = &follow_parent,
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};
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/* ahb masks structure */
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static struct bus_clk_masks ahb_masks = {
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.mask = PLL_HCLK_RATIO_MASK,
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.shift = PLL_HCLK_RATIO_SHIFT,
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};
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/* ahb configuration structure */
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static struct bus_clk_config ahb_config = {
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.reg = CORE_CLK_CFG,
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.mask = PLL_HCLK_RATIO_MASK,
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.shift = PLL_HCLK_RATIO_SHIFT,
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.masks = &ahb_masks,
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};
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/* ahb clock */
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@ -91,9 +111,22 @@ static struct clk ahb_clk = {
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.private_data = &ahb_config,
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};
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/* auxiliary synthesizers masks */
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static struct aux_clk_masks aux_masks = {
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.eq_sel_mask = AUX_EQ_SEL_MASK,
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.eq_sel_shift = AUX_EQ_SEL_SHIFT,
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.eq1_mask = AUX_EQ1_SEL,
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.eq2_mask = AUX_EQ2_SEL,
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.xscale_sel_mask = AUX_XSCALE_MASK,
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.xscale_sel_shift = AUX_XSCALE_SHIFT,
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.yscale_sel_mask = AUX_YSCALE_MASK,
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.yscale_sel_shift = AUX_YSCALE_SHIFT,
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};
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/* uart configurations */
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static struct aux_clk_config uart_config = {
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.synth_reg = UART_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* uart parents */
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@ -130,6 +163,7 @@ static struct clk uart_clk = {
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/* firda configurations */
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static struct aux_clk_config firda_config = {
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.synth_reg = FIRDA_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* firda parents */
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@ -184,9 +218,18 @@ static struct pclk_sel gpt_pclk_sel = {
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt synthesizer masks */
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static struct gpt_clk_masks gpt_masks = {
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.mscale_sel_mask = GPT_MSCALE_MASK,
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.mscale_sel_shift = GPT_MSCALE_SHIFT,
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.nscale_sel_mask = GPT_NSCALE_MASK,
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.nscale_sel_shift = GPT_NSCALE_SHIFT,
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};
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/* gpt0 configurations */
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static struct aux_clk_config gpt0_config = {
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static struct gpt_clk_config gpt0_config = {
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.synth_reg = PRSC1_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt0 timer clock */
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@ -199,8 +242,9 @@ static struct clk gpt0_clk = {
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};
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/* gpt1 configurations */
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static struct aux_clk_config gpt1_config = {
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static struct gpt_clk_config gpt1_config = {
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.synth_reg = PRSC2_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt1 timer clock */
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@ -214,8 +258,9 @@ static struct clk gpt1_clk = {
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};
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/* gpt2 configurations */
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static struct aux_clk_config gpt2_config = {
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static struct gpt_clk_config gpt2_config = {
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.synth_reg = PRSC3_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt2 timer clock */
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@ -253,11 +298,16 @@ static struct clk clcd_clk = {
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};
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/* clock derived from ahb clk */
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/* apb masks structure */
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static struct bus_clk_masks apb_masks = {
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.mask = HCLK_PCLK_RATIO_MASK,
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.shift = HCLK_PCLK_RATIO_SHIFT,
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};
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/* apb configuration structure */
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static struct bus_clk_config apb_config = {
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.reg = CORE_CLK_CFG,
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.mask = HCLK_PCLK_RATIO_MASK,
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.shift = HCLK_PCLK_RATIO_SHIFT,
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.masks = &apb_masks,
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};
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/* apb clock */
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@ -39,10 +39,25 @@ static struct clk rtc_clk = {
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};
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/* clock derived from 30 MHz osc clk */
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/* pll masks structure */
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static struct pll_clk_masks pll1_masks = {
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.mode_mask = PLL_MODE_MASK,
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.mode_shift = PLL_MODE_SHIFT,
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.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
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.norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
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.dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
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.dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
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.div_p_mask = PLL_DIV_P_MASK,
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.div_p_shift = PLL_DIV_P_SHIFT,
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.div_n_mask = PLL_DIV_N_MASK,
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.div_n_shift = PLL_DIV_N_SHIFT,
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};
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/* pll1 configuration structure */
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static struct pll_clk_config pll1_config = {
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.mode_reg = PLL1_CTR,
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.cfg_reg = PLL1_FRQ,
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.masks = &pll1_masks,
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};
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/* PLL1 clock */
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@ -50,7 +65,7 @@ static struct clk pll1_clk = {
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.pclk = &osc_30m_clk,
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.en_reg = PLL1_CTR,
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.en_reg_bit = PLL_ENABLE,
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.recalc = &pll1_clk_recalc,
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.recalc = &pll_clk_recalc,
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.private_data = &pll1_config,
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};
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@ -76,11 +91,16 @@ static struct clk cpu_clk = {
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.recalc = &follow_parent,
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};
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/* ahb masks structure */
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static struct bus_clk_masks ahb_masks = {
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.mask = PLL_HCLK_RATIO_MASK,
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.shift = PLL_HCLK_RATIO_SHIFT,
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};
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/* ahb configuration structure */
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static struct bus_clk_config ahb_config = {
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.reg = CORE_CLK_CFG,
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.mask = PLL_HCLK_RATIO_MASK,
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.shift = PLL_HCLK_RATIO_SHIFT,
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.masks = &ahb_masks,
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};
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/* ahb clock */
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@ -112,9 +132,22 @@ static struct pclk_sel uart_pclk_sel = {
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.pclk_sel_mask = UART_CLK_MASK,
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};
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/* auxiliary synthesizers masks */
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static struct aux_clk_masks aux_masks = {
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.eq_sel_mask = AUX_EQ_SEL_MASK,
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.eq_sel_shift = AUX_EQ_SEL_SHIFT,
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.eq1_mask = AUX_EQ1_SEL,
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.eq2_mask = AUX_EQ2_SEL,
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.xscale_sel_mask = AUX_XSCALE_MASK,
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.xscale_sel_shift = AUX_XSCALE_SHIFT,
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.yscale_sel_mask = AUX_YSCALE_MASK,
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.yscale_sel_shift = AUX_YSCALE_SHIFT,
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};
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/* uart configurations */
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static struct aux_clk_config uart_config = {
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.synth_reg = UART_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* uart0 clock */
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@ -140,6 +173,7 @@ static struct clk uart1_clk = {
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/* firda configurations */
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static struct aux_clk_config firda_config = {
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.synth_reg = FIRDA_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* firda parents */
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@ -176,6 +210,7 @@ static struct clk firda_clk = {
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/* clcd configurations */
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static struct aux_clk_config clcd_config = {
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.synth_reg = CLCD_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* clcd parents */
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@ -230,9 +265,18 @@ static struct pclk_sel gpt_pclk_sel = {
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt synthesizer masks */
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static struct gpt_clk_masks gpt_masks = {
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.mscale_sel_mask = GPT_MSCALE_MASK,
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.mscale_sel_shift = GPT_MSCALE_SHIFT,
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.nscale_sel_mask = GPT_NSCALE_MASK,
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.nscale_sel_shift = GPT_NSCALE_SHIFT,
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};
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/* gpt0_1 configurations */
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static struct aux_clk_config gpt0_1_config = {
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static struct gpt_clk_config gpt0_1_config = {
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.synth_reg = PRSC1_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt0 ARM1 subsystem timer clock */
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@ -254,8 +298,9 @@ static struct clk gpt1_clk = {
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};
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/* gpt2 configurations */
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static struct aux_clk_config gpt2_config = {
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static struct gpt_clk_config gpt2_config = {
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.synth_reg = PRSC2_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt2 timer clock */
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@ -269,8 +314,9 @@ static struct clk gpt2_clk = {
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};
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/* gpt3 configurations */
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static struct aux_clk_config gpt3_config = {
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static struct gpt_clk_config gpt3_config = {
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.synth_reg = PRSC3_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt3 timer clock */
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@ -309,11 +355,16 @@ static struct clk usbd_clk = {
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};
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/* clock derived from ahb clk */
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/* apb masks structure */
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static struct bus_clk_masks apb_masks = {
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.mask = HCLK_PCLK_RATIO_MASK,
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.shift = HCLK_PCLK_RATIO_SHIFT,
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};
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/* apb configuration structure */
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static struct bus_clk_config apb_config = {
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.reg = CORE_CLK_CFG,
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.mask = HCLK_PCLK_RATIO_MASK,
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.shift = HCLK_PCLK_RATIO_SHIFT,
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.masks = &apb_masks,
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};
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/* apb clock */
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@ -17,7 +17,6 @@
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <mach/misc_regs.h>
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#include <plat/clock.h>
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static DEFINE_SPINLOCK(clocks_lock);
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@ -187,6 +186,20 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
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}
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EXPORT_SYMBOL(clk_set_parent);
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/**
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* clk_set_rate - set the clock rate for a clock source
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* @clk: clock source
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* @rate: desired clock rate in Hz
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*
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* Returns success (0) or negative errno.
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*/
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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/* TODO */
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return -EINVAL;
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}
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EXPORT_SYMBOL(clk_set_rate);
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/* registers clock in platform clock framework */
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void clk_register(struct clk_lookup *cl)
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{
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@ -212,6 +225,7 @@ void clk_register(struct clk_lookup *cl)
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list_add(&clk->sibling, &clk->pclk->children);
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} else {
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/* add clocks with > 1 parent to 1st parent's children list */
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clk->pclk = clk->pclk_sel->pclk_info[0].pclk;
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list_add(&clk->sibling,
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&clk->pclk_sel->pclk_info[0].pclk->children);
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}
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@ -283,29 +297,31 @@ static void change_parent(struct clk *cclk, struct clk *pclk)
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* In Dithered mode
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* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
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*/
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void pll1_clk_recalc(struct clk *clk)
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void pll_clk_recalc(struct clk *clk)
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{
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struct pll_clk_config *config = clk->private_data;
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unsigned int num = 2, den = 0, val, mode = 0;
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
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PLL_MODE_MASK;
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mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
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config->masks->mode_mask;
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val = readl(config->cfg_reg);
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/* calculate denominator */
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den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
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den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
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den = 1 << den;
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den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
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den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
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/* calculate numerator & denominator */
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if (!mode) {
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/* Normal mode */
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num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
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num *= (val >> config->masks->norm_fdbk_m_shift) &
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config->masks->norm_fdbk_m_mask;
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} else {
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/* Dithered mode */
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num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
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num *= (val >> config->masks->dith_fdbk_m_shift) &
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config->masks->dith_fdbk_m_mask;
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den *= 256;
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}
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@ -321,7 +337,8 @@ void bus_clk_recalc(struct clk *clk)
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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div = ((readl(config->reg) >> config->shift) & config->mask) + 1;
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div = ((readl(config->reg) >> config->masks->shift) &
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config->masks->mask) + 1;
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clk->rate = (unsigned long)clk->pclk->rate / div;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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@ -359,15 +376,18 @@ void aux_clk_recalc(struct clk *clk)
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if (pclk_info->scalable) {
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val = readl(config->synth_reg);
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eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK;
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if (eqn == AUX_EQ1_SEL)
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eqn = (val >> config->masks->eq_sel_shift) &
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config->masks->eq_sel_mask;
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if (eqn == config->masks->eq1_mask)
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den *= 2;
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/* calculate numerator */
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num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK;
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num = (val >> config->masks->xscale_sel_shift) &
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config->masks->xscale_sel_mask;
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/* calculate denominator */
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den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK;
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den *= (val >> config->masks->yscale_sel_shift) &
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config->masks->yscale_sel_mask;
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val = (((clk->pclk->rate/10000) * num) / den) * 10000;
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} else
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val = clk->pclk->rate;
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@ -383,7 +403,7 @@ void aux_clk_recalc(struct clk *clk)
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*/
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void gpt_clk_recalc(struct clk *clk)
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{
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struct aux_clk_config *config = clk->private_data;
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struct gpt_clk_config *config = clk->private_data;
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struct pclk_info *pclk_info = NULL;
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unsigned int div = 1, val;
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unsigned long flags;
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|
@ -402,8 +422,10 @@ void gpt_clk_recalc(struct clk *clk)
|
|||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (pclk_info->scalable) {
|
||||
val = readl(config->synth_reg);
|
||||
div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK;
|
||||
div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
|
||||
div += (val >> config->masks->mscale_sel_shift) &
|
||||
config->masks->mscale_sel_mask;
|
||||
div *= 1 << (((val >> config->masks->nscale_sel_shift) &
|
||||
config->masks->nscale_sel_mask) + 1);
|
||||
}
|
||||
|
||||
clk->rate = (unsigned long)clk->pclk->rate / div;
|
||||
|
|
@ -411,15 +433,16 @@ void gpt_clk_recalc(struct clk *clk)
|
|||
}
|
||||
|
||||
/*
|
||||
* Used for clocks that always have same value as the parent clock divided by a
|
||||
* Used for clocks that always have value as the parent clock divided by a
|
||||
* fixed divisor
|
||||
*/
|
||||
void follow_parent(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
clk->rate = clk->pclk->rate;
|
||||
clk->rate = clk->pclk->rate/div_factor;
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ struct pclk_info {
|
|||
struct pclk_sel {
|
||||
struct pclk_info *pclk_info;
|
||||
u8 pclk_count;
|
||||
unsigned int *pclk_sel_reg;
|
||||
void __iomem *pclk_sel_reg;
|
||||
unsigned int pclk_sel_mask;
|
||||
};
|
||||
|
||||
|
|
@ -67,6 +67,7 @@ struct pclk_sel {
|
|||
* @en_reg_bit: clk enable/disable bit
|
||||
* @ops: clk enable/disable ops - generic_clkops selected if NULL
|
||||
* @recalc: pointer to clock rate recalculate function
|
||||
* @div_factor: division factor to parent clock. Only for recalc = follow_parent
|
||||
* @pclk: current parent clk
|
||||
* @pclk_sel: pointer to parent selection structure
|
||||
* @pclk_sel_shift: register shift for selecting parent of this clock
|
||||
|
|
@ -78,10 +79,11 @@ struct clk {
|
|||
unsigned int usage_count;
|
||||
unsigned int flags;
|
||||
unsigned long rate;
|
||||
unsigned int *en_reg;
|
||||
void __iomem *en_reg;
|
||||
u8 en_reg_bit;
|
||||
const struct clkops *ops;
|
||||
void (*recalc) (struct clk *);
|
||||
unsigned int div_factor;
|
||||
|
||||
struct clk *pclk;
|
||||
struct pclk_sel *pclk_sel;
|
||||
|
|
@ -93,23 +95,65 @@ struct clk {
|
|||
};
|
||||
|
||||
/* pll configuration structure */
|
||||
struct pll_clk_masks {
|
||||
u32 mode_mask;
|
||||
u32 mode_shift;
|
||||
|
||||
u32 norm_fdbk_m_mask;
|
||||
u32 norm_fdbk_m_shift;
|
||||
u32 dith_fdbk_m_mask;
|
||||
u32 dith_fdbk_m_shift;
|
||||
u32 div_p_mask;
|
||||
u32 div_p_shift;
|
||||
u32 div_n_mask;
|
||||
u32 div_n_shift;
|
||||
};
|
||||
|
||||
struct pll_clk_config {
|
||||
unsigned int *mode_reg;
|
||||
unsigned int *cfg_reg;
|
||||
void __iomem *mode_reg;
|
||||
void __iomem *cfg_reg;
|
||||
struct pll_clk_masks *masks;
|
||||
};
|
||||
|
||||
/* ahb and apb bus configuration structure */
|
||||
struct bus_clk_config {
|
||||
unsigned int *reg;
|
||||
unsigned int mask;
|
||||
unsigned int shift;
|
||||
struct bus_clk_masks {
|
||||
u32 mask;
|
||||
u32 shift;
|
||||
};
|
||||
|
||||
struct bus_clk_config {
|
||||
void __iomem *reg;
|
||||
struct bus_clk_masks *masks;
|
||||
};
|
||||
|
||||
/* Aux clk configuration structure: applicable to UART and FIRDA */
|
||||
struct aux_clk_masks {
|
||||
u32 eq_sel_mask;
|
||||
u32 eq_sel_shift;
|
||||
u32 eq1_mask;
|
||||
u32 eq2_mask;
|
||||
u32 xscale_sel_mask;
|
||||
u32 xscale_sel_shift;
|
||||
u32 yscale_sel_mask;
|
||||
u32 yscale_sel_shift;
|
||||
};
|
||||
|
||||
/*
|
||||
* Aux clk configuration structure: applicable to GPT, UART and FIRDA
|
||||
*/
|
||||
struct aux_clk_config {
|
||||
unsigned int *synth_reg;
|
||||
void __iomem *synth_reg;
|
||||
struct aux_clk_masks *masks;
|
||||
};
|
||||
|
||||
/* GPT clk configuration structure */
|
||||
struct gpt_clk_masks {
|
||||
u32 mscale_sel_mask;
|
||||
u32 mscale_sel_shift;
|
||||
u32 nscale_sel_mask;
|
||||
u32 nscale_sel_shift;
|
||||
};
|
||||
|
||||
struct gpt_clk_config {
|
||||
void __iomem *synth_reg;
|
||||
struct gpt_clk_masks *masks;
|
||||
};
|
||||
|
||||
/* platform specific clock functions */
|
||||
|
|
@ -118,7 +162,7 @@ void recalc_root_clocks(void);
|
|||
|
||||
/* clock recalc functions */
|
||||
void follow_parent(struct clk *clk);
|
||||
void pll1_clk_recalc(struct clk *clk);
|
||||
void pll_clk_recalc(struct clk *clk);
|
||||
void bus_clk_recalc(struct clk *clk);
|
||||
void gpt_clk_recalc(struct clk *clk);
|
||||
void aux_clk_recalc(struct clk *clk);
|
||||
|
|
|
|||
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