liquidio CN23XX: VF interrupt
Adds support for VF interrupt processing. Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raghu Vatsavayi
David S. Miller
Родитель
f7cdd64bed
Коммит
cf39faf542
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@ -27,6 +27,26 @@
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#include "octeon_main.h"
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#include "octeon_mailbox.h"
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u32 cn23xx_vf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)
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{
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/* This gives the SLI clock per microsec */
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u32 oqticks_per_us = (u32)oct->pfvf_hsword.coproc_tics_per_us;
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/* This gives the clock cycles per millisecond */
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oqticks_per_us *= 1000;
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/* This gives the oq ticks (1024 core clock cycles) per millisecond */
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oqticks_per_us /= 1024;
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/* time_intr is in microseconds. The next 2 steps gives the oq ticks
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* corressponding to time_intr.
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*/
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oqticks_per_us *= time_intr_in_us;
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oqticks_per_us /= 1000;
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return oqticks_per_us;
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}
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static int cn23xx_vf_reset_io_queues(struct octeon_device *oct, u32 num_queues)
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{
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u32 loop = BUSY_READING_REG_VF_LOOP_COUNT;
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@ -212,6 +232,11 @@ static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no)
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*/
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pkt_in_done = readq(iq->inst_cnt_reg);
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if (oct->msix_on) {
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/* Set CINT_ENB to enable IQ interrupt */
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writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),
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iq->inst_cnt_reg);
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}
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iq->reset_instr_cnt = 0;
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}
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@ -342,6 +367,240 @@ static void cn23xx_disable_vf_io_queues(struct octeon_device *oct)
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cn23xx_vf_reset_io_queues(oct, num_queues);
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}
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void cn23xx_vf_ask_pf_to_do_flr(struct octeon_device *oct)
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{
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struct octeon_mbox_cmd mbox_cmd;
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mbox_cmd.msg.u64 = 0;
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mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
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mbox_cmd.msg.s.resp_needed = 0;
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mbox_cmd.msg.s.cmd = OCTEON_VF_FLR_REQUEST;
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mbox_cmd.msg.s.len = 1;
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mbox_cmd.q_no = 0;
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mbox_cmd.recv_len = 0;
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mbox_cmd.recv_status = 0;
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mbox_cmd.fn = NULL;
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mbox_cmd.fn_arg = 0;
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octeon_mbox_write(oct, &mbox_cmd);
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}
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static void octeon_pfvf_hs_callback(struct octeon_device *oct,
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struct octeon_mbox_cmd *cmd,
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void *arg)
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{
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u32 major = 0;
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memcpy((uint8_t *)&oct->pfvf_hsword, cmd->msg.s.params,
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CN23XX_MAILBOX_MSGPARAM_SIZE);
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if (cmd->recv_len > 1) {
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major = ((struct lio_version *)(cmd->data))->major;
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major = major << 16;
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}
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atomic_set((atomic_t *)arg, major | 1);
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}
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int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct)
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{
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struct octeon_mbox_cmd mbox_cmd;
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u32 q_no, count = 0;
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atomic_t status;
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u32 pfmajor;
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u32 vfmajor;
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u32 ret;
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/* Sending VF_ACTIVE indication to the PF driver */
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dev_dbg(&oct->pci_dev->dev, "requesting info from pf\n");
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mbox_cmd.msg.u64 = 0;
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mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
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mbox_cmd.msg.s.resp_needed = 1;
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mbox_cmd.msg.s.cmd = OCTEON_VF_ACTIVE;
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mbox_cmd.msg.s.len = 2;
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mbox_cmd.data[0] = 0;
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((struct lio_version *)&mbox_cmd.data[0])->major =
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LIQUIDIO_BASE_MAJOR_VERSION;
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((struct lio_version *)&mbox_cmd.data[0])->minor =
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LIQUIDIO_BASE_MINOR_VERSION;
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((struct lio_version *)&mbox_cmd.data[0])->micro =
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LIQUIDIO_BASE_MICRO_VERSION;
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mbox_cmd.q_no = 0;
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mbox_cmd.recv_len = 0;
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mbox_cmd.recv_status = 0;
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mbox_cmd.fn = (octeon_mbox_callback_t)octeon_pfvf_hs_callback;
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mbox_cmd.fn_arg = &status;
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/* Interrupts are not enabled at this point.
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* Enable them with default oq ticks
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*/
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oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR);
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octeon_mbox_write(oct, &mbox_cmd);
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atomic_set(&status, 0);
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do {
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schedule_timeout_uninterruptible(1);
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} while ((!atomic_read(&status)) && (count++ < 100000));
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/* Disable the interrupt so that the interrupsts will be reenabled
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* with the oq ticks received from the PF
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*/
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oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
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ret = atomic_read(&status);
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if (!ret) {
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dev_err(&oct->pci_dev->dev, "octeon_pfvf_handshake timeout\n");
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return 1;
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}
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for (q_no = 0 ; q_no < oct->num_iqs ; q_no++)
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oct->instr_queue[q_no]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
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vfmajor = LIQUIDIO_BASE_MAJOR_VERSION;
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pfmajor = ret >> 16;
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if (pfmajor != vfmajor) {
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dev_err(&oct->pci_dev->dev,
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"VF Liquidio driver (major version %d) is not compatible with Liquidio PF driver (major version %d)\n",
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vfmajor, pfmajor);
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return 1;
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}
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dev_dbg(&oct->pci_dev->dev,
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"VF Liquidio driver (major version %d), Liquidio PF driver (major version %d)\n",
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vfmajor, pfmajor);
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dev_dbg(&oct->pci_dev->dev, "got data from pf pkind is %d\n",
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oct->pfvf_hsword.pkind);
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return 0;
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}
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static void cn23xx_handle_vf_mbox_intr(struct octeon_ioq_vector *ioq_vector)
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{
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struct octeon_device *oct = ioq_vector->oct_dev;
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u64 mbox_int_val;
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if (!ioq_vector->droq_index) {
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/* read and clear by writing 1 */
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mbox_int_val = readq(oct->mbox[0]->mbox_int_reg);
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writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg);
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if (octeon_mbox_read(oct->mbox[0]))
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schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work,
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msecs_to_jiffies(0));
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}
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}
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static u64 cn23xx_vf_msix_interrupt_handler(void *dev)
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{
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struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
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struct octeon_device *oct = ioq_vector->oct_dev;
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struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
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u64 pkts_sent;
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u64 ret = 0;
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dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);
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pkts_sent = readq(droq->pkts_sent_reg);
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/* If our device has interrupted, then proceed. Also check
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* for all f's if interrupt was triggered on an error
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* and the PCI read fails.
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*/
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if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL))
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return ret;
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/* Write count reg in sli_pkt_cnts to clear these int. */
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if ((pkts_sent & CN23XX_INTR_PO_INT) ||
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(pkts_sent & CN23XX_INTR_PI_INT)) {
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if (pkts_sent & CN23XX_INTR_PO_INT)
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ret |= MSIX_PO_INT;
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}
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if (pkts_sent & CN23XX_INTR_PI_INT)
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/* We will clear the count when we update the read_index. */
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ret |= MSIX_PI_INT;
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if (pkts_sent & CN23XX_INTR_MBOX_INT) {
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cn23xx_handle_vf_mbox_intr(ioq_vector);
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ret |= MSIX_MBOX_INT;
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}
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return ret;
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}
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static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag)
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{
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struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
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u32 q_no, time_threshold;
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if (intr_flag & OCTEON_OUTPUT_INTR) {
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for (q_no = 0; q_no < oct->num_oqs; q_no++) {
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/* Set up interrupt packet and time thresholds
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* for all the OQs
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*/
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time_threshold = cn23xx_vf_get_oq_ticks(
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oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
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octeon_write_csr64(
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oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
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(CFG_GET_OQ_INTR_PKT(cn23xx->conf) |
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((u64)time_threshold << 32)));
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}
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}
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if (intr_flag & OCTEON_INPUT_INTR) {
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for (q_no = 0; q_no < oct->num_oqs; q_no++) {
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/* Set CINT_ENB to enable IQ interrupt */
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octeon_write_csr64(
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oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
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((octeon_read_csr64(
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oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) &
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~CN23XX_PKT_IN_DONE_CNT_MASK) |
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CN23XX_INTR_CINT_ENB));
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}
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}
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/* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */
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if (intr_flag & OCTEON_MBOX_INTR) {
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octeon_write_csr64(
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oct, CN23XX_VF_SLI_PKT_MBOX_INT(0),
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(octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) |
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CN23XX_INTR_MBOX_ENB));
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}
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}
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static void cn23xx_disable_vf_interrupt(struct octeon_device *oct, u8 intr_flag)
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{
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u32 q_no;
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if (intr_flag & OCTEON_OUTPUT_INTR) {
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for (q_no = 0; q_no < oct->num_oqs; q_no++) {
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/* Write all 1's in INT_LEVEL reg to disable PO_INT */
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octeon_write_csr64(
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oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
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0x3fffffffffffff);
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}
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}
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if (intr_flag & OCTEON_INPUT_INTR) {
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for (q_no = 0; q_no < oct->num_oqs; q_no++) {
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octeon_write_csr64(
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oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
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(octeon_read_csr64(
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oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) &
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~(CN23XX_INTR_CINT_ENB |
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CN23XX_PKT_IN_DONE_CNT_MASK)));
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}
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}
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if (intr_flag & OCTEON_MBOX_INTR) {
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octeon_write_csr64(
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oct, CN23XX_VF_SLI_PKT_MBOX_INT(0),
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(octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) &
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~CN23XX_INTR_MBOX_ENB));
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}
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}
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int cn23xx_setup_octeon_vf_device(struct octeon_device *oct)
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{
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struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
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@ -397,8 +656,14 @@ int cn23xx_setup_octeon_vf_device(struct octeon_device *oct)
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oct->fn_list.setup_oq_regs = cn23xx_setup_vf_oq_regs;
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oct->fn_list.setup_mbox = cn23xx_setup_vf_mbox;
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oct->fn_list.free_mbox = cn23xx_free_vf_mbox;
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oct->fn_list.msix_interrupt_handler = cn23xx_vf_msix_interrupt_handler;
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oct->fn_list.setup_device_regs = cn23xx_setup_vf_device_regs;
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oct->fn_list.enable_interrupt = cn23xx_enable_vf_interrupt;
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oct->fn_list.disable_interrupt = cn23xx_disable_vf_interrupt;
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oct->fn_list.enable_io_queues = cn23xx_enable_vf_io_queues;
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oct->fn_list.disable_io_queues = cn23xx_disable_vf_io_queues;
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@ -34,6 +34,12 @@ struct octeon_cn23xx_vf {
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#define BUSY_READING_REG_VF_LOOP_COUNT 10000
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#define CN23XX_MAILBOX_MSGPARAM_SIZE 6
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void cn23xx_vf_ask_pf_to_do_flr(struct octeon_device *oct);
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int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct);
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int cn23xx_setup_octeon_vf_device(struct octeon_device *oct);
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void cn23xx_dump_vf_initialized_regs(struct octeon_device *oct);
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@ -85,13 +85,6 @@ void octeon_update_tx_completion_counters(void *buf, int reqtype,
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}
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(*pkts_compl)++;
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/*TODO, Use some other pound define to suggest
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* the fact that iqs are not tied to netdevs
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* and can take traffic from different netdevs
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* hence bql reporting is done per packet
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* than in bulk. Usage of NO_NAPI in txq completion is
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* a little confusing
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*/
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*bytes_compl += skb->len;
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}
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@ -59,6 +59,118 @@ static struct pci_driver liquidio_vf_pci_driver = {
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.remove = liquidio_vf_remove,
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};
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static
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int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret)
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{
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struct octeon_device *oct = droq->oct_dev;
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struct octeon_device_priv *oct_priv =
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(struct octeon_device_priv *)oct->priv;
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if (droq->ops.poll_mode) {
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droq->ops.napi_fn(droq);
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} else {
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if (ret & MSIX_PO_INT) {
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dev_err(&oct->pci_dev->dev,
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"should not come here should not get rx when poll mode = 0 for vf\n");
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tasklet_schedule(&oct_priv->droq_tasklet);
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return 1;
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}
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/* this will be flushed periodically by check iq db */
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if (ret & MSIX_PI_INT)
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return 0;
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}
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return 0;
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}
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static irqreturn_t
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liquidio_msix_intr_handler(int irq __attribute__((unused)), void *dev)
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{
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struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
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struct octeon_device *oct = ioq_vector->oct_dev;
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struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
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u64 ret;
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ret = oct->fn_list.msix_interrupt_handler(ioq_vector);
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if ((ret & MSIX_PO_INT) || (ret & MSIX_PI_INT))
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liquidio_schedule_msix_droq_pkt_handler(droq, ret);
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return IRQ_HANDLED;
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}
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/**
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* \brief Setup interrupt for octeon device
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* @param oct octeon device
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*
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* Enable interrupt in Octeon device as given in the PCI interrupt mask.
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*/
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static int octeon_setup_interrupt(struct octeon_device *oct)
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{
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struct msix_entry *msix_entries;
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int num_alloc_ioq_vectors;
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int num_ioq_vectors;
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int irqret;
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int i;
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if (oct->msix_on) {
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oct->num_msix_irqs = oct->sriov_info.rings_per_vf;
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oct->msix_entries = kcalloc(
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oct->num_msix_irqs, sizeof(struct msix_entry), GFP_KERNEL);
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if (!oct->msix_entries)
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return 1;
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msix_entries = (struct msix_entry *)oct->msix_entries;
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for (i = 0; i < oct->num_msix_irqs; i++)
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msix_entries[i].entry = i;
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num_alloc_ioq_vectors = pci_enable_msix_range(
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oct->pci_dev, msix_entries,
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oct->num_msix_irqs,
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oct->num_msix_irqs);
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if (num_alloc_ioq_vectors < 0) {
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dev_err(&oct->pci_dev->dev, "unable to Allocate MSI-X interrupts\n");
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kfree(oct->msix_entries);
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oct->msix_entries = NULL;
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return 1;
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}
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dev_dbg(&oct->pci_dev->dev, "OCTEON: Enough MSI-X interrupts are allocated...\n");
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num_ioq_vectors = oct->num_msix_irqs;
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for (i = 0; i < num_ioq_vectors; i++) {
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irqret = request_irq(msix_entries[i].vector,
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liquidio_msix_intr_handler, 0,
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"octeon", &oct->ioq_vector[i]);
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if (irqret) {
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dev_err(&oct->pci_dev->dev,
|
||||
"OCTEON: Request_irq failed for MSIX interrupt Error: %d\n",
|
||||
irqret);
|
||||
|
||||
while (i) {
|
||||
i--;
|
||||
irq_set_affinity_hint(
|
||||
msix_entries[i].vector, NULL);
|
||||
free_irq(msix_entries[i].vector,
|
||||
&oct->ioq_vector[i]);
|
||||
}
|
||||
pci_disable_msix(oct->pci_dev);
|
||||
kfree(oct->msix_entries);
|
||||
oct->msix_entries = NULL;
|
||||
return 1;
|
||||
}
|
||||
oct->ioq_vector[i].vector = msix_entries[i].vector;
|
||||
/* assign the cpu mask for this msix interrupt vector */
|
||||
irq_set_affinity_hint(
|
||||
msix_entries[i].vector,
|
||||
(&oct->ioq_vector[i].affinity_mask));
|
||||
}
|
||||
dev_dbg(&oct->pci_dev->dev,
|
||||
"OCTEON[%d]: MSI-X enabled\n", oct->octeon_id);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief PCI probe handler
|
||||
* @param pdev PCI device structure
|
||||
|
|
@ -77,6 +189,7 @@ liquidio_vf_probe(struct pci_dev *pdev,
|
|||
dev_err(&pdev->dev, "Unable to allocate device\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
oct_dev->msix_on = LIO_FLAG_MSIX_ENABLED;
|
||||
|
||||
dev_info(&pdev->dev, "Initializing device %x:%x.\n",
|
||||
(u32)pdev->vendor, (u32)pdev->device);
|
||||
|
|
@ -140,9 +253,37 @@ static void octeon_pci_flr(struct octeon_device *oct)
|
|||
*/
|
||||
static void octeon_destroy_resources(struct octeon_device *oct)
|
||||
{
|
||||
struct msix_entry *msix_entries;
|
||||
int i;
|
||||
|
||||
switch (atomic_read(&oct->status)) {
|
||||
case OCT_DEV_INTR_SET_DONE:
|
||||
/* Disable interrupts */
|
||||
oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
|
||||
|
||||
if (oct->msix_on) {
|
||||
msix_entries = (struct msix_entry *)oct->msix_entries;
|
||||
for (i = 0; i < oct->num_msix_irqs; i++) {
|
||||
irq_set_affinity_hint(msix_entries[i].vector,
|
||||
NULL);
|
||||
free_irq(msix_entries[i].vector,
|
||||
&oct->ioq_vector[i]);
|
||||
}
|
||||
pci_disable_msix(oct->pci_dev);
|
||||
kfree(oct->msix_entries);
|
||||
oct->msix_entries = NULL;
|
||||
}
|
||||
/* Soft reset the octeon device before exiting */
|
||||
if (oct->pci_dev->reset_fn)
|
||||
octeon_pci_flr(oct);
|
||||
else
|
||||
cn23xx_vf_ask_pf_to_do_flr(oct);
|
||||
|
||||
/* fallthrough */
|
||||
case OCT_DEV_MSIX_ALLOC_VECTOR_DONE:
|
||||
octeon_free_ioq_vector(oct);
|
||||
|
||||
/* fallthrough */
|
||||
case OCT_DEV_MBOX_SETUP_DONE:
|
||||
oct->fn_list.free_mbox(oct);
|
||||
|
||||
|
|
@ -326,6 +467,27 @@ static int octeon_device_init(struct octeon_device *oct)
|
|||
}
|
||||
atomic_set(&oct->status, OCT_DEV_MBOX_SETUP_DONE);
|
||||
|
||||
if (octeon_allocate_ioq_vector(oct)) {
|
||||
dev_err(&oct->pci_dev->dev, "ioq vector allocation failed\n");
|
||||
return 1;
|
||||
}
|
||||
atomic_set(&oct->status, OCT_DEV_MSIX_ALLOC_VECTOR_DONE);
|
||||
|
||||
dev_info(&oct->pci_dev->dev, "OCTEON_CN23XX VF Version: %s, %d ioqs\n",
|
||||
LIQUIDIO_VERSION, oct->sriov_info.rings_per_vf);
|
||||
|
||||
/* Setup the interrupt handler and record the INT SUM register address*/
|
||||
if (octeon_setup_interrupt(oct))
|
||||
return 1;
|
||||
|
||||
if (cn23xx_octeon_pfvf_handshake(oct))
|
||||
return 1;
|
||||
|
||||
/* Enable Octeon device interrupts */
|
||||
oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR);
|
||||
|
||||
atomic_set(&oct->status, OCT_DEV_INTR_SET_DONE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -754,6 +754,9 @@ octeon_allocate_ioq_vector(struct octeon_device *oct)
|
|||
|
||||
if (OCTEON_CN23XX_PF(oct))
|
||||
num_ioqs = oct->sriov_info.num_pf_rings;
|
||||
else if (OCTEON_CN23XX_VF(oct))
|
||||
num_ioqs = oct->sriov_info.rings_per_vf;
|
||||
|
||||
size = sizeof(struct octeon_ioq_vector) * num_ioqs;
|
||||
|
||||
oct->ioq_vector = vmalloc(size);
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ enum {
|
|||
NUM_OCTEON_CONFS,
|
||||
};
|
||||
|
||||
#define OCTEON_INPUT_INTR (1)
|
||||
#define OCTEON_OUTPUT_INTR (2)
|
||||
#define OCTEON_MBOX_INTR (4)
|
||||
#define OCTEON_ALL_INTR 0xff
|
||||
|
|
@ -294,6 +295,7 @@ struct octdev_props {
|
|||
#define LIO_FLAG_MSIX_ENABLED 0x1
|
||||
#define MSIX_PO_INT 0x1
|
||||
#define MSIX_PI_INT 0x2
|
||||
#define MSIX_MBOX_INT 0x4
|
||||
|
||||
struct octeon_pf_vf_hs_word {
|
||||
#ifdef __LITTLE_ENDIAN_BITFIELD
|
||||
|
|
|
|||
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