[PATCH] i386: Factor out common io apic routing entry access
The IO APIC code had lots of duplicated code to read/write 64bit routing entries into the IO-APIC. Factor this out int common read/write functions In a few cases the IO APIC lock is taken more often now, but this isn't a problem because it's all initialization/shutdown only slow path code. Similar to earlier x86-64 patch. Includes a fix by Jiri Slaby for a mistake that broke resume Signed-off-by: Andi Kleen <ak@suse.de>
This commit is contained in:
Andi Kleen
Andi Kleen
Родитель
eea0e11c1f
Коммит
cf4c6a2f27
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@ -94,6 +94,34 @@ int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
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#define vector_to_irq(vector) (vector)
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#endif
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union entry_union {
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struct { u32 w1, w2; };
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struct IO_APIC_route_entry entry;
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};
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static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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{
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union entry_union eu;
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unsigned long flags;
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spin_lock_irqsave(&ioapic_lock, flags);
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eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
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eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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return eu.entry;
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}
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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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unsigned long flags;
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union entry_union eu;
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eu.entry = e;
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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/*
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* The common case is 1:1 IRQ<->pin mappings. Sometimes there are
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* shared ISA-space IRQs, so we have to support them. We are super
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@ -201,13 +229,9 @@ static void unmask_IO_APIC_irq (unsigned int irq)
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static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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{
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struct IO_APIC_route_entry entry;
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unsigned long flags;
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/* Check delivery_mode to be sure we're not clearing an SMI pin */
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spin_lock_irqsave(&ioapic_lock, flags);
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*(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
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*(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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entry = ioapic_read_entry(apic, pin);
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if (entry.delivery_mode == dest_SMI)
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return;
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@ -216,10 +240,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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*/
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memset(&entry, 0, sizeof(entry));
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entry.mask = 1;
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
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io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
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spin_unlock_irqrestore(&ioapic_lock, flags);
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ioapic_write_entry(apic, pin, entry);
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}
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static void clear_IO_APIC (void)
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@ -1284,9 +1305,8 @@ static void __init setup_IO_APIC_irqs(void)
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if (!apic && (irq < 16))
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disable_8259A_irq(irq);
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}
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ioapic_write_entry(apic, pin, entry);
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
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io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
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set_native_irq_info(irq, TARGET_CPUS);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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@ -1302,7 +1322,6 @@ static void __init setup_IO_APIC_irqs(void)
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static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
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{
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struct IO_APIC_route_entry entry;
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unsigned long flags;
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memset(&entry,0,sizeof(entry));
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@ -1332,10 +1351,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
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/*
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* Add it to the IO-APIC irq-routing table:
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*/
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
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io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
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spin_unlock_irqrestore(&ioapic_lock, flags);
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ioapic_write_entry(apic, pin, entry);
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enable_8259A_irq(0);
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}
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@ -1445,10 +1461,7 @@ void __init print_IO_APIC(void)
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for (i = 0; i <= reg_01.bits.entries; i++) {
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struct IO_APIC_route_entry entry;
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spin_lock_irqsave(&ioapic_lock, flags);
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*(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
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*(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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entry = ioapic_read_entry(apic, i);
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printk(KERN_DEBUG " %02x %03X %02X ",
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i,
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@ -1667,10 +1680,7 @@ static void __init enable_IO_APIC(void)
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/* See if any of the pins is in ExtINT mode */
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for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
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struct IO_APIC_route_entry entry;
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spin_lock_irqsave(&ioapic_lock, flags);
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*(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
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*(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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entry = ioapic_read_entry(apic, pin);
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/* If the interrupt line is enabled and in ExtInt mode
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@ -1727,7 +1737,6 @@ void disable_IO_APIC(void)
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*/
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if (ioapic_i8259.pin != -1) {
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struct IO_APIC_route_entry entry;
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unsigned long flags;
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memset(&entry, 0, sizeof(entry));
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entry.mask = 0; /* Enabled */
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@ -1744,12 +1753,7 @@ void disable_IO_APIC(void)
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/*
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* Add it to the IO-APIC irq-routing table:
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*/
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
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*(((int *)&entry)+1));
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io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
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*(((int *)&entry)+0));
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spin_unlock_irqrestore(&ioapic_lock, flags);
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ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
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}
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disconnect_bsp_APIC(ioapic_i8259.pin != -1);
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}
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@ -2214,17 +2218,13 @@ static inline void unlock_ExtINT_logic(void)
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int apic, pin, i;
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struct IO_APIC_route_entry entry0, entry1;
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unsigned char save_control, save_freq_select;
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unsigned long flags;
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pin = find_isa_irq_pin(8, mp_INT);
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apic = find_isa_irq_apic(8, mp_INT);
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if (pin == -1)
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return;
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spin_lock_irqsave(&ioapic_lock, flags);
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*(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
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*(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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entry0 = ioapic_read_entry(apic, pin);
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clear_IO_APIC_pin(apic, pin);
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memset(&entry1, 0, sizeof(entry1));
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@ -2237,10 +2237,7 @@ static inline void unlock_ExtINT_logic(void)
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entry1.trigger = 0;
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entry1.vector = 0;
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
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io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
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spin_unlock_irqrestore(&ioapic_lock, flags);
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ioapic_write_entry(apic, pin, entry1);
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save_control = CMOS_READ(RTC_CONTROL);
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save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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@ -2259,10 +2256,7 @@ static inline void unlock_ExtINT_logic(void)
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CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
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clear_IO_APIC_pin(apic, pin);
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
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io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
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spin_unlock_irqrestore(&ioapic_lock, flags);
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ioapic_write_entry(apic, pin, entry0);
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}
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int timer_uses_ioapic_pin_0;
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@ -2462,17 +2456,12 @@ static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct IO_APIC_route_entry *entry;
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struct sysfs_ioapic_data *data;
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unsigned long flags;
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int i;
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data = container_of(dev, struct sysfs_ioapic_data, dev);
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entry = data->entry;
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spin_lock_irqsave(&ioapic_lock, flags);
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for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
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*(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
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*(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
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}
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spin_unlock_irqrestore(&ioapic_lock, flags);
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for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
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entry[i] = ioapic_read_entry(dev->id, i);
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return 0;
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}
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@ -2494,11 +2483,9 @@ static int ioapic_resume(struct sys_device *dev)
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reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
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io_apic_write(dev->id, 0, reg_00.raw);
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}
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for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
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io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
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io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
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}
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spin_unlock_irqrestore(&ioapic_lock, flags);
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for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
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ioapic_write_entry(dev->id, i, entry[i]);
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return 0;
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}
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@ -2695,9 +2682,8 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
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if (!ioapic && (irq < 16))
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disable_8259A_irq(irq);
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ioapic_write_entry(ioapic, pin, entry);
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
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io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
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set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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