arm64: dts: k3-am6: Add PCIe Root Complex DT node
Add PCIe Root Complex DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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cfa6437a71
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@ -265,6 +265,21 @@
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#size-cells = <1>;
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ranges = <0x0 0x0 0x00100000 0x1c000>;
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pcie0_mode: pcie-mode@4060 {
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compatible = "syscon";
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reg = <0x00004060 0x4>;
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};
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pcie1_mode: pcie-mode@4070 {
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compatible = "syscon";
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reg = <0x00004070 0x4>;
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};
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pcie_devid: pcie-devid@210 {
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compatible = "syscon";
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reg = <0x00000210 0x4>;
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};
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serdes0_clk: serdes_clk@4080 {
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compatible = "syscon";
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reg = <0x00004080 0x4>;
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@ -431,4 +446,42 @@
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clocks = <&k3_clks 58 0>;
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clock-names = "gpio";
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};
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pcie0_rc: pcie@5500000 {
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compatible = "ti,am654-pcie-rc";
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reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
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reg-names = "app", "dbics", "config", "atu";
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power-domains = <&k3_pds 120>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
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0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
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ti,syscon-pcie-id = <&pcie_devid>;
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ti,syscon-pcie-mode = <&pcie0_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <3>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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};
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pcie1_rc: pcie@5600000 {
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compatible = "ti,am654-pcie-rc";
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reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
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reg-names = "app", "dbics", "config", "atu";
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power-domains = <&k3_pds 121>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
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0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
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ti,syscon-pcie-id = <&pcie_devid>;
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ti,syscon-pcie-mode = <&pcie1_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <3>;
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x10000 0x10000>;
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};
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};
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@ -69,6 +69,7 @@
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
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<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
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<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
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/* MCUSS Range */
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
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