sparc: Fix single-pcr perf event counter management.
It is important to clear the hw->state value for non-stopped events when they are added into the PMU. Otherwise when the event is scheduled out, we won't read the counter because HES_UPTODATE is still set. This breaks 'perf stat' and similar use cases, causing all the events to show zero. This worked for multi-pcr because we make explicit sparc_pmu_start() calls in calculate_multiple_pcrs(). calculate_single_pcr() doesn't do this because the idea there is to accumulate all of the counter settings into the single pcr value. So we have to add explicit hw->state handling there. Like x86, we use the PERF_HES_ARCH bit to track truly stopped events so that we don't accidently start them on a reload. Related to all of this, sparc_pmu_start() is missing a userpage update so add it. Signed-off-by: David S. Miller <davem@davemloft.net>
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Родитель
7c26701a77
Коммит
cfdc3170d2
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@ -927,6 +927,8 @@ static void read_in_all_counters(struct cpu_hw_events *cpuc)
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sparc_perf_event_update(cp, &cp->hw,
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sparc_perf_event_update(cp, &cp->hw,
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cpuc->current_idx[i]);
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cpuc->current_idx[i]);
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cpuc->current_idx[i] = PIC_NO_INDEX;
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cpuc->current_idx[i] = PIC_NO_INDEX;
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if (cp->hw.state & PERF_HES_STOPPED)
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cp->hw.state |= PERF_HES_ARCH;
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}
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}
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}
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}
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}
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}
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@ -959,10 +961,12 @@ static void calculate_single_pcr(struct cpu_hw_events *cpuc)
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enc = perf_event_get_enc(cpuc->events[i]);
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enc = perf_event_get_enc(cpuc->events[i]);
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cpuc->pcr[0] &= ~mask_for_index(idx);
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cpuc->pcr[0] &= ~mask_for_index(idx);
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if (hwc->state & PERF_HES_STOPPED)
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if (hwc->state & PERF_HES_ARCH) {
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cpuc->pcr[0] |= nop_for_index(idx);
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cpuc->pcr[0] |= nop_for_index(idx);
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else
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} else {
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cpuc->pcr[0] |= event_encoding(enc, idx);
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cpuc->pcr[0] |= event_encoding(enc, idx);
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hwc->state = 0;
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}
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}
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}
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out:
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out:
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cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
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cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
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@ -988,6 +992,9 @@ static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
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cpuc->current_idx[i] = idx;
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cpuc->current_idx[i] = idx;
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if (cp->hw.state & PERF_HES_ARCH)
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continue;
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sparc_pmu_start(cp, PERF_EF_RELOAD);
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sparc_pmu_start(cp, PERF_EF_RELOAD);
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}
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}
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out:
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out:
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@ -1079,6 +1086,8 @@ static void sparc_pmu_start(struct perf_event *event, int flags)
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event->hw.state = 0;
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event->hw.state = 0;
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sparc_pmu_enable_event(cpuc, &event->hw, idx);
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sparc_pmu_enable_event(cpuc, &event->hw, idx);
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perf_event_update_userpage(event);
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}
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}
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static void sparc_pmu_stop(struct perf_event *event, int flags)
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static void sparc_pmu_stop(struct perf_event *event, int flags)
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@ -1371,9 +1380,9 @@ static int sparc_pmu_add(struct perf_event *event, int ef_flags)
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cpuc->events[n0] = event->hw.event_base;
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cpuc->events[n0] = event->hw.event_base;
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cpuc->current_idx[n0] = PIC_NO_INDEX;
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cpuc->current_idx[n0] = PIC_NO_INDEX;
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event->hw.state = PERF_HES_UPTODATE;
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (!(ef_flags & PERF_EF_START))
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if (!(ef_flags & PERF_EF_START))
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event->hw.state |= PERF_HES_STOPPED;
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event->hw.state |= PERF_HES_ARCH;
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/*
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/*
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* If group events scheduling transaction was started,
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* If group events scheduling transaction was started,
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