drm/i915: Implement IS_* macros using static tables
Instead of using the IS_I9XX etc macros that expand to a ton of comparisons, use new struct intel_device_info to capture the capabilities of the different chipsets. The drm_i915_private struct will be initialized to point to the device info that correspond to the actual device and this way, testing for a specific capability is just a matter of checking a bit field. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kristian Høgsberg
Eric Anholt
Родитель
49ae35f2dd
Коммит
cfdf1fa23f
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@ -1360,7 +1360,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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resource_size_t base, size;
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int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
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int ret = 0, mmio_bar;
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uint32_t agp_size, prealloc_size, prealloc_start;
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/* i915 has 4 more counters */
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@ -1376,8 +1376,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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dev->dev_private = (void *)dev_priv;
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dev_priv->dev = dev;
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dev_priv->info = (struct intel_device_info *) flags;
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/* Add register map (needed for suspend/resume) */
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mmio_bar = IS_I9XX(dev) ? 0 : 1;
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base = drm_get_resource_start(dev, mmio_bar);
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size = drm_get_resource_len(dev, mmio_bar);
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@ -47,46 +47,122 @@ module_param_named(powersave, i915_powersave, int, 0400);
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static struct drm_driver driver;
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#define INTEL_VGA_DEVICE(id) { \
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#define INTEL_VGA_DEVICE(id, info) { \
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.class = PCI_CLASS_DISPLAY_VGA << 8, \
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.class_mask = 0xffff00, \
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.vendor = 0x8086, \
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.device = id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.driver_data = 0 }
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.driver_data = (unsigned long) info }
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static struct pci_device_id pciidlist[] = {
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INTEL_VGA_DEVICE(0x3577),
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INTEL_VGA_DEVICE(0x2562),
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INTEL_VGA_DEVICE(0x3582),
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INTEL_VGA_DEVICE(0x2572),
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INTEL_VGA_DEVICE(0x2582),
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INTEL_VGA_DEVICE(0x258a),
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INTEL_VGA_DEVICE(0x2592),
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INTEL_VGA_DEVICE(0x2772),
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INTEL_VGA_DEVICE(0x27a2),
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INTEL_VGA_DEVICE(0x27ae),
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INTEL_VGA_DEVICE(0x2972),
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INTEL_VGA_DEVICE(0x2982),
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INTEL_VGA_DEVICE(0x2992),
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INTEL_VGA_DEVICE(0x29a2),
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INTEL_VGA_DEVICE(0x29b2),
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INTEL_VGA_DEVICE(0x29c2),
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INTEL_VGA_DEVICE(0x29d2),
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INTEL_VGA_DEVICE(0x2a02),
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INTEL_VGA_DEVICE(0x2a12),
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INTEL_VGA_DEVICE(0x2a42),
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INTEL_VGA_DEVICE(0x2e02),
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INTEL_VGA_DEVICE(0x2e12),
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INTEL_VGA_DEVICE(0x2e22),
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INTEL_VGA_DEVICE(0x2e32),
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INTEL_VGA_DEVICE(0x2e42),
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INTEL_VGA_DEVICE(0xa001),
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INTEL_VGA_DEVICE(0xa011),
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INTEL_VGA_DEVICE(0x35e8),
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INTEL_VGA_DEVICE(0x0042),
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INTEL_VGA_DEVICE(0x0046),
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const static struct intel_device_info intel_i830_info = {
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.is_i8xx = 1, .is_mobile = 1,
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};
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const static struct intel_device_info intel_845g_info = {
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.is_i8xx = 1,
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};
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const static struct intel_device_info intel_i85x_info = {
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.is_i8xx = 1, .is_mobile = 1,
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};
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const static struct intel_device_info intel_i865g_info = {
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.is_i8xx = 1,
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};
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const static struct intel_device_info intel_i915g_info = {
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.is_i915g = 1, .is_i9xx = 1,
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};
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const static struct intel_device_info intel_i915gm_info = {
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.is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
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};
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const static struct intel_device_info intel_i945g_info = {
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.is_i9xx = 1, .has_hotplug = 1,
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};
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const static struct intel_device_info intel_i945gm_info = {
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.is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_i965g_info = {
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.is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
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};
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const static struct intel_device_info intel_i965gm_info = {
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.is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
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.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_g33_info = {
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.is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_g45_info = {
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.is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
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.has_pipe_cxsr = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_gm45_info = {
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.is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
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.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
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.has_pipe_cxsr = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_pineview_info = {
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.is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
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.has_pipe_cxsr = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_ironlake_d_info = {
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.is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
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.has_pipe_cxsr = 1,
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_ironlake_m_info = {
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.is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
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.need_gfx_hws = 1, .has_rc6 = 1,
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.has_hotplug = 1,
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};
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const static struct pci_device_id pciidlist[] = {
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INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
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INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
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INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
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INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
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INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
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INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
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INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
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INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
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INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
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INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
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INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
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INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
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INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
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INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
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INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
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INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
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INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
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INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
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INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
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INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
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INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
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INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
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INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
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INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
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INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
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INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
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INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
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INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
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INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
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INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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{0, 0, 0}
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};
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@ -172,9 +172,30 @@ struct drm_i915_display_funcs {
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struct intel_overlay;
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struct intel_device_info {
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u8 is_mobile : 1;
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u8 is_i8xx : 1;
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u8 is_i915g : 1;
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u8 is_i9xx : 1;
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u8 is_i945gm : 1;
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u8 is_i965g : 1;
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u8 is_i965gm : 1;
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u8 is_g33 : 1;
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u8 need_gfx_hws : 1;
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u8 is_g4x : 1;
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u8 is_pineview : 1;
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u8 is_ironlake : 1;
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u8 has_fbc : 1;
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u8 has_rc6 : 1;
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u8 has_pipe_cxsr : 1;
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u8 has_hotplug : 1;
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};
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typedef struct drm_i915_private {
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struct drm_device *dev;
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const struct intel_device_info *info;
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int has_gem;
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void __iomem *regs;
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@ -983,67 +1004,33 @@ extern void g4x_disable_fbc(struct drm_device *dev);
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extern int i915_wrap_ring(struct drm_device * dev);
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extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_I830(dev) ((dev)->pci_device == 0x3577)
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#define IS_845G(dev) ((dev)->pci_device == 0x2562)
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#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
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#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
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#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
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#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
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#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
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#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
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#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
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(dev)->pci_device == 0x27AE)
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#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
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(dev)->pci_device == 0x2982 || \
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(dev)->pci_device == 0x2992 || \
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(dev)->pci_device == 0x29A2 || \
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(dev)->pci_device == 0x2A02 || \
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(dev)->pci_device == 0x2A12 || \
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(dev)->pci_device == 0x2A42 || \
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(dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22 || \
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(dev)->pci_device == 0x2E32 || \
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(dev)->pci_device == 0x2E42 || \
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(dev)->pci_device == 0x0042 || \
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(dev)->pci_device == 0x0046)
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#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
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(dev)->pci_device == 0x2A12)
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#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
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#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22 || \
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(dev)->pci_device == 0x2E32 || \
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(dev)->pci_device == 0x2E42 || \
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IS_GM45(dev))
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#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
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#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
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#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
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#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
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(dev)->pci_device == 0x29B2 || \
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(dev)->pci_device == 0x29D2 || \
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(IS_PINEVIEW(dev)))
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#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
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#define IS_I830(dev) ((dev)->pci_device == 0x3577)
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#define IS_845G(dev) ((dev)->pci_device == 0x2562)
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#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
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#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
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#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
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#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
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#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
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#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
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#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
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#define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
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#define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
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#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
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#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
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#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
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#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
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#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
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#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
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#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
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#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
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#define IS_IRONLAKE(dev) (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev))
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#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
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#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
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#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
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#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
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IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
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IS_IRONLAKE(dev))
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#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
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#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
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IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
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IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
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#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
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IS_IRONLAKE(dev))
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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* rows, which changed the alignment requirements and fence programming.
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*/
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@ -1055,17 +1042,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
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#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
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!IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
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#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
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#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
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/* dsparb controlled by hw only */
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#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
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#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
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#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
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#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
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(IS_I9XX(dev) || IS_GM45(dev)) && \
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!IS_PINEVIEW(dev) && \
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!IS_IRONLAKE(dev))
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#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
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#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
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#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
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#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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