staging/rdma/hfi1: Correct TWSI reset
Change the TWSI reset function so it will stop the reset once the lines are in an expected state. Reviewed-by: Easwar Hariharan <easwar.hariharan@intel.com> Reviewed-by: Dean Luick <dean.luick@intel.com> Signed-off-by: Pablo Cacho <pablo.cacho@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Dean Luick
Doug Ledford
Родитель
0096765be0
Коммит
cfe3e656d8
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@ -5,7 +5,7 @@
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2015 Intel Corporation.
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -18,7 +18,7 @@
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*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation.
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -106,7 +106,6 @@ int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"I2C write interface reset failed\n");
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ret = -EIO;
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goto done;
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}
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@ -179,7 +178,6 @@ int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"I2C read interface reset failed\n");
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ret = -EIO;
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goto done;
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}
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@ -213,7 +211,7 @@ int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"QSFP write interface reset failed\n");
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mutex_unlock(&ppd->dd->qsfp_i2c_mutex);
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return -EIO;
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return ret;
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}
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while (count < len) {
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@ -279,7 +277,7 @@ int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"QSFP read interface reset failed\n");
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mutex_unlock(&ppd->dd->qsfp_i2c_mutex);
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return -EIO;
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return ret;
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}
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while (count < len) {
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@ -5,7 +5,7 @@
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2015 Intel Corporation.
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -18,7 +18,7 @@
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*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation.
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -136,6 +136,19 @@ static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit)
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i2c_wait_for_writes(dd, target);
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}
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static u8 scl_in(struct hfi1_devdata *dd, u32 target, int wait)
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{
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u32 read_val, mask;
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mask = QSFP_HFI0_I2CCLK;
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/* SCL is meant to be bare-drain, so never set "OUT", just DIR */
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hfi1_gpio_mod(dd, target, 0, 0, mask);
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read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
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if (wait)
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i2c_wait_for_writes(dd, target);
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return (read_val & mask) >> GPIO_SCL_NUM;
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}
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static void sda_out(struct hfi1_devdata *dd, u32 target, u8 bit)
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{
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u32 mask;
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@ -274,13 +287,12 @@ static void stop_cmd(struct hfi1_devdata *dd, u32 target)
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/**
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* hfi1_twsi_reset - reset I2C communication
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* @dd: the hfi1_ib device
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* returns 0 if ok, -EIO on error
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*/
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int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target)
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{
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int clock_cycles_left = 9;
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int was_high = 0;
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u32 pins, mask;
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u32 mask;
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/* Both SCL and SDA should be high. If not, there
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* is something wrong.
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@ -294,43 +306,23 @@ int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target)
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*/
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hfi1_gpio_mod(dd, target, 0, 0, mask);
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/*
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* Clock nine times to get all listeners into a sane state.
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* If SDA does not go high at any point, we are wedged.
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* One vendor recommends then issuing START followed by STOP.
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* we cannot use our "normal" functions to do that, because
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* if SCL drops between them, another vendor's part will
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* wedge, dropping SDA and keeping it low forever, at the end of
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* the next transaction (even if it was not the device addressed).
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* So our START and STOP take place with SCL held high.
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/* Check if SCL is low, if it is low then we have a slave device
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* misbehaving and there is not much we can do.
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*/
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if (!scl_in(dd, target, 0))
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return -EIO;
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/* Check if SDA is low, if it is low then we have to clock SDA
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* up to 9 times for the device to release the bus
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*/
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while (clock_cycles_left--) {
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if (sda_in(dd, target, 0))
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return 0;
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scl_out(dd, target, 0);
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scl_out(dd, target, 1);
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/* Note if SDA is high, but keep clocking to sync slave */
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was_high |= sda_in(dd, target, 0);
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}
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if (was_high) {
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/*
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* We saw a high, which we hope means the slave is sync'd.
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* Issue START, STOP, pause for T_BUF.
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*/
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pins = hfi1_gpio_mod(dd, target, 0, 0, 0);
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if ((pins & mask) != mask)
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dd_dev_err(dd, "GPIO pins not at rest: %d\n",
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pins & mask);
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/* Drop SDA to issue START */
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udelay(1); /* Guarantee .6 uSec setup */
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sda_out(dd, target, 0);
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udelay(1); /* Guarantee .6 uSec hold */
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/* At this point, SCL is high, SDA low. Raise SDA for STOP */
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sda_out(dd, target, 1);
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udelay(TWSI_BUF_WAIT_USEC);
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}
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return !was_high;
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return -EIO;
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}
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#define HFI1_TWSI_START 0x100
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@ -7,7 +7,7 @@
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2015 Intel Corporation.
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -20,7 +20,7 @@
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*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation.
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -54,8 +54,9 @@
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struct hfi1_devdata;
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/* Bit position of SDA pin in ASIC_QSFP* registers */
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/* Bit position of SDA/SCL pins in ASIC_QSFP* registers */
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#define GPIO_SDA_NUM 1
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#define GPIO_SCL_NUM 0
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/* these functions must be called with qsfp_lock held */
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int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target);
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