phy: mediatek: hdmi: mt2701: use common helper to access registers
Use MediaTek phy's common helper to access registers, then we can remove hdmi's I/O helpers. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220920090038.15133-9-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Chunfeng Yun
Vinod Koul
Родитель
a98d935eac
Коммит
cff81a618a
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@ -5,6 +5,7 @@
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*/
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#include "phy-mtk-hdmi.h"
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#include "phy-mtk-io.h"
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#define HDMI_CON0 0x00
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#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0)
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@ -49,20 +50,21 @@
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static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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void __iomem *base = hdmi_phy->regs;
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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usleep_range(80, 100);
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return 0;
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}
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@ -70,20 +72,21 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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void __iomem *base = hdmi_phy->regs;
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
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usleep_range(80, 100);
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}
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@ -97,6 +100,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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void __iomem *base = hdmi_phy->regs;
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u32 pos_div;
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if (rate <= 64000000)
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@ -106,37 +110,25 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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else
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pos_div = 1;
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1),
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RG_HTPLL_IC_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1),
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RG_HTPLL_IR_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div),
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RG_HDMITX_TX_POSDIV_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1),
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RG_HTPLL_FBKSEL_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19),
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RG_HTPLL_FBKDIV_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2),
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RG_HTPLL_DIVEN_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc),
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RG_HTPLL_BP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2),
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RG_HTPLL_BC_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1),
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RG_HTPLL_BR_MASK);
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);
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mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);
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mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3),
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RG_HDMITX_PRED_IBIAS_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28),
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RG_HDMITX_DRV_IMP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa),
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RG_HDMITX_DRV_IBIAS_MASK);
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mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP);
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mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
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mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28);
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mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);
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mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);
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return 0;
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}
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@ -184,37 +176,41 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
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static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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void __iomem *base = hdmi_phy->regs;
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mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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usleep_range(80, 100);
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}
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static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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void __iomem *base = hdmi_phy->regs;
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
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usleep_range(80, 100);
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}
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