drm/i915/dp: Fix dsc bpp calculations, v5.
There was a integer wraparound when mode_clock became too high, and we didn't correct for the FEC overhead factor when dividing, with the calculations breaking at HBR3. As a result our calculated bpp was way too high, and the link width limitation never came into effect. Print out the resulting bpp calcululations as a sanity check, just in case we ever have to debug it later on again. We also used the wrong factor for FEC. While bspec mentions 2.4%, all the calculations use 1/0.972261, and the same ratio should be applied to data M/N as well, so use it there when FEC is enabled. This fixes the FIFO underrun we are seeing with FEC enabled. Changes since v2: - Handle fec_enable in intel_link_compute_m_n, so only data M/N is adjusted. (Ville) - Fix initial hardware readout for FEC. (Ville) Changes since v3: - Remove bogus fec_to_mode_clock. (Ville) Changes since v4: - Use the correct register for icl. (Ville) - Split hw readout to a separate patch. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes:d9218c8f6c("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC") Cc: <stable@vger.kernel.org> # v5.0+ Cc: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190925082110.17439-1-maarten.lankhorst@linux.intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (cherry picked from commited06efb801) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Maarten Lankhorst
Rodrigo Vivi
Родитель
54ecb8f702
Коммит
cffb4c3ea3
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@ -7261,7 +7261,7 @@ retry:
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pipe_config->fdi_lanes = lane;
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intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
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link_bw, &pipe_config->fdi_m_n, false);
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link_bw, &pipe_config->fdi_m_n, false, false);
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ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
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if (ret == -EDEADLK)
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@ -7508,11 +7508,15 @@ void
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intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
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int pixel_clock, int link_clock,
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struct intel_link_m_n *m_n,
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bool constant_n)
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bool constant_n, bool fec_enable)
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{
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m_n->tu = 64;
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u32 data_clock = bits_per_pixel * pixel_clock;
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compute_m_n(bits_per_pixel * pixel_clock,
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if (fec_enable)
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data_clock = intel_dp_mode_to_fec_clock(data_clock);
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m_n->tu = 64;
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compute_m_n(data_clock,
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link_clock * nlanes * 8,
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&m_n->gmch_m, &m_n->gmch_n,
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constant_n);
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@ -414,7 +414,7 @@ enum phy_fia {
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void intel_link_compute_m_n(u16 bpp, int nlanes,
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int pixel_clock, int link_clock,
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struct intel_link_m_n *m_n,
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bool constant_n);
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bool constant_n, bool fec_enable);
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bool is_ccs_modifier(u64 modifier);
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void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
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u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
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@ -78,8 +78,8 @@
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#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
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#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
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/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
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#define DP_DSC_FEC_OVERHEAD_FACTOR 976
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/* DP DSC FEC Overhead factor = 1/(0.972261) */
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#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
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/* Compliance test status bits */
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#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
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@ -494,6 +494,97 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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return 0;
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}
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u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
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{
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return div_u64(mul_u32_u32(mode_clock, 1000000U),
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DP_DSC_FEC_OVERHEAD_FACTOR);
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}
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static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
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u32 mode_clock, u32 mode_hdisplay)
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{
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u32 bits_per_pixel, max_bpp_small_joiner_ram;
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int i;
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/*
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* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
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* (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
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* for SST -> TimeSlotsPerMTP is 1,
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* for MST -> TimeSlotsPerMTP has to be calculated
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*/
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bits_per_pixel = (link_clock * lane_count * 8) /
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intel_dp_mode_to_fec_clock(mode_clock);
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DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
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/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
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max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
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DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
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/*
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* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
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* check, output bpp from small joiner RAM check)
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*/
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bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
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/* Error out if the max bpp is less than smallest allowed valid bpp */
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if (bits_per_pixel < valid_dsc_bpp[0]) {
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DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
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bits_per_pixel, valid_dsc_bpp[0]);
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return 0;
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}
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/* Find the nearest match in the array of known BPPs from VESA */
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for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
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if (bits_per_pixel < valid_dsc_bpp[i + 1])
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break;
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}
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bits_per_pixel = valid_dsc_bpp[i];
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/*
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* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
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* fractional part is 0
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*/
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return bits_per_pixel << 4;
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}
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static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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int mode_clock, int mode_hdisplay)
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{
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u8 min_slice_count, i;
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int max_slice_width;
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if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
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min_slice_count = DIV_ROUND_UP(mode_clock,
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DP_DSC_MAX_ENC_THROUGHPUT_0);
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else
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min_slice_count = DIV_ROUND_UP(mode_clock,
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DP_DSC_MAX_ENC_THROUGHPUT_1);
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max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
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if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
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DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
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max_slice_width);
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return 0;
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}
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/* Also take into account max slice width */
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min_slice_count = min_t(u8, min_slice_count,
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DIV_ROUND_UP(mode_hdisplay,
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max_slice_width));
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/* Find the closest match to the valid slice count values */
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for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
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if (valid_dsc_slicecount[i] >
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drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
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false))
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break;
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if (min_slice_count <= valid_dsc_slicecount[i])
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return valid_dsc_slicecount[i];
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}
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DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
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return 0;
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}
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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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@ -2226,7 +2317,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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adjusted_mode->crtc_clock,
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pipe_config->port_clock,
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&pipe_config->dp_m_n,
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constant_n);
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constant_n, pipe_config->fec_enable);
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if (intel_connector->panel.downclock_mode != NULL &&
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dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
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@ -2236,7 +2327,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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intel_connector->panel.downclock_mode->clock,
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pipe_config->port_clock,
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&pipe_config->dp_m2_n2,
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constant_n);
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constant_n, pipe_config->fec_enable);
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}
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if (!HAS_DDI(dev_priv))
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@ -4323,91 +4414,6 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
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DP_DPRX_ESI_LEN;
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}
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u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
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int mode_clock, int mode_hdisplay)
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{
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u16 bits_per_pixel, max_bpp_small_joiner_ram;
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int i;
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/*
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* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
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* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
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* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
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* for MST -> TimeSlotsPerMTP has to be calculated
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*/
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bits_per_pixel = (link_clock * lane_count * 8 *
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DP_DSC_FEC_OVERHEAD_FACTOR) /
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mode_clock;
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/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
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max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
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mode_hdisplay;
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/*
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* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
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* check, output bpp from small joiner RAM check)
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*/
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bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
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/* Error out if the max bpp is less than smallest allowed valid bpp */
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if (bits_per_pixel < valid_dsc_bpp[0]) {
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DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
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return 0;
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}
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/* Find the nearest match in the array of known BPPs from VESA */
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for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
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if (bits_per_pixel < valid_dsc_bpp[i + 1])
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break;
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}
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bits_per_pixel = valid_dsc_bpp[i];
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/*
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* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
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* fractional part is 0
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*/
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return bits_per_pixel << 4;
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}
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u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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int mode_clock,
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int mode_hdisplay)
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{
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u8 min_slice_count, i;
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int max_slice_width;
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if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
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min_slice_count = DIV_ROUND_UP(mode_clock,
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DP_DSC_MAX_ENC_THROUGHPUT_0);
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else
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min_slice_count = DIV_ROUND_UP(mode_clock,
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DP_DSC_MAX_ENC_THROUGHPUT_1);
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max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
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if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
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DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
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max_slice_width);
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return 0;
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}
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/* Also take into account max slice width */
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min_slice_count = min_t(u8, min_slice_count,
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DIV_ROUND_UP(mode_hdisplay,
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max_slice_width));
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/* Find the closest match to the valid slice count values */
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for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
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if (valid_dsc_slicecount[i] >
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drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
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false))
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break;
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if (min_slice_count <= valid_dsc_slicecount[i])
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return valid_dsc_slicecount[i];
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}
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DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
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return 0;
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}
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static void
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intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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@ -102,10 +102,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
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bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
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bool
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intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
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u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
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int mode_clock, int mode_hdisplay);
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u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
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int mode_hdisplay);
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bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
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bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
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@ -118,4 +114,6 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
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return ~((1 << lane_count) - 1) & 0xf;
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}
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u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
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#endif /* __INTEL_DP_H__ */
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@ -81,7 +81,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
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adjusted_mode->crtc_clock,
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crtc_state->port_clock,
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&crtc_state->dp_m_n,
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constant_n);
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constant_n, crtc_state->fec_enable);
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crtc_state->dp_m_n.tu = slots;
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return 0;
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