PCI: qcom: Add support for MSM8996 PCIe controller
Add support for the MSM8996/APQ8096 PCIe controller. MSM8996 supports Gen 1/2, one lane, 3 PCIe root complexes with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. Add a post_init callback to qcom_pcie_ops, as the PCIe pipe clocks are only setup after the phy is powered on. It also adds an ltssm_enable callback as it is very much different from other supported SoCs in the driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
This commit is contained in:
Srinivas Kandagatla
Bjorn Helgaas
Родитель
1001354ca3
Коммит
d0491fc39b
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@ -7,6 +7,7 @@
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- "qcom,pcie-ipq8064" for ipq8064
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- "qcom,pcie-apq8064" for apq8064
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- "qcom,pcie-apq8084" for apq8084
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- "qcom,pcie-msm8996" for msm8996 or apq8096
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- reg:
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Usage: required
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@ -92,6 +93,17 @@
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- "aux" Auxiliary (AUX) clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- clock-names:
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Usage: required for msm8996/apq8096
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pipe" Pipe Clock driving internal logic
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- "aux" Auxiliary (AUX) clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- resets:
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Usage: required
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Value type: <prop-encoded-array>
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@ -115,7 +127,7 @@
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- "core" Core reset
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- power-domains:
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Usage: required for apq8084
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Usage: required for apq8084 and msm8996/apq8096
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Value type: <prop-encoded-array>
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Definition: A phandle and power domain specifier pair to the
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power domain which is responsible for collapsing
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@ -36,11 +36,17 @@
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#include "pcie-designware.h"
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#define PCIE20_PARF_SYS_CTRL 0x00
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#define PCIE20_PARF_PHY_CTRL 0x40
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#define PCIE20_PARF_PHY_REFCLK 0x4C
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#define PCIE20_PARF_DBI_BASE_ADDR 0x168
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#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
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#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
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#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
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#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
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#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
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#define PCIE20_PARF_LTSSM 0x1B0
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#define PCIE20_PARF_SID_OFFSET 0x234
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#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
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#define PCIE20_ELBI_SYS_CTRL 0x04
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#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
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@ -72,9 +78,18 @@ struct qcom_pcie_resources_v1 {
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struct regulator *vdda;
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};
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struct qcom_pcie_resources_v2 {
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struct clk *aux_clk;
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struct clk *master_clk;
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struct clk *slave_clk;
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struct clk *cfg_clk;
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struct clk *pipe_clk;
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};
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union qcom_pcie_resources {
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struct qcom_pcie_resources_v0 v0;
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struct qcom_pcie_resources_v1 v1;
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struct qcom_pcie_resources_v2 v2;
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};
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struct qcom_pcie;
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@ -82,7 +97,9 @@ struct qcom_pcie;
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struct qcom_pcie_ops {
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int (*get_resources)(struct qcom_pcie *pcie);
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int (*init)(struct qcom_pcie *pcie);
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int (*post_init)(struct qcom_pcie *pcie);
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void (*deinit)(struct qcom_pcie *pcie);
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void (*ltssm_enable)(struct qcom_pcie *pcie);
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};
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struct qcom_pcie {
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@ -116,17 +133,35 @@ static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
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return dw_handle_msi_irq(pp);
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}
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static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
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static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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if (dw_pcie_link_up(&pcie->pp))
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return 0;
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/* enable link training */
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val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
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writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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}
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static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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/* enable link training */
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val = readl(pcie->parf + PCIE20_PARF_LTSSM);
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val |= BIT(8);
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writel(val, pcie->parf + PCIE20_PARF_LTSSM);
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}
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static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
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{
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if (dw_pcie_link_up(&pcie->pp))
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return 0;
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/* Enable Link Training state machine */
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if (pcie->ops->ltssm_enable)
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pcie->ops->ltssm_enable(pcie);
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return dw_pcie_wait_for_link(&pcie->pp);
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}
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@ -421,6 +456,113 @@ err_res:
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return ret;
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}
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static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct device *dev = pcie->pp.dev;
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res->aux_clk = devm_clk_get(dev, "aux");
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if (IS_ERR(res->aux_clk))
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return PTR_ERR(res->aux_clk);
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res->cfg_clk = devm_clk_get(dev, "cfg");
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if (IS_ERR(res->cfg_clk))
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return PTR_ERR(res->cfg_clk);
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res->master_clk = devm_clk_get(dev, "bus_master");
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if (IS_ERR(res->master_clk))
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return PTR_ERR(res->master_clk);
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res->slave_clk = devm_clk_get(dev, "bus_slave");
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if (IS_ERR(res->slave_clk))
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return PTR_ERR(res->slave_clk);
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res->pipe_clk = devm_clk_get(dev, "pipe");
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if (IS_ERR(res->pipe_clk))
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return PTR_ERR(res->pipe_clk);
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return 0;
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}
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static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct device *dev = pcie->pp.dev;
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u32 val;
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int ret;
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ret = clk_prepare_enable(res->aux_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable aux clock\n");
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return ret;
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}
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ret = clk_prepare_enable(res->cfg_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable cfg clock\n");
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goto err_cfg_clk;
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}
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ret = clk_prepare_enable(res->master_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable master clock\n");
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goto err_master_clk;
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}
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ret = clk_prepare_enable(res->slave_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable slave clock\n");
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goto err_slave_clk;
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}
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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val &= ~BIT(0);
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writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
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/* change DBI base address */
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writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
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/* MAC PHY_POWERDOWN MUX DISABLE */
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val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
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val &= ~BIT(29);
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writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
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val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
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val |= BIT(4);
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writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
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val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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val |= BIT(31);
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writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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return 0;
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err_slave_clk:
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clk_disable_unprepare(res->master_clk);
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err_master_clk:
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clk_disable_unprepare(res->cfg_clk);
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err_cfg_clk:
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clk_disable_unprepare(res->aux_clk);
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return ret;
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}
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static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct device *dev = pcie->pp.dev;
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int ret;
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ret = clk_prepare_enable(res->pipe_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable pipe clock\n");
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return ret;
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}
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return 0;
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}
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static int qcom_pcie_link_up(struct pcie_port *pp)
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{
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struct qcom_pcie *pcie = to_qcom_pcie(pp);
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@ -429,6 +571,17 @@ static int qcom_pcie_link_up(struct pcie_port *pp)
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return !!(val & PCI_EXP_LNKSTA_DLLLA);
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}
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static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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clk_disable_unprepare(res->pipe_clk);
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clk_disable_unprepare(res->slave_clk);
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clk_disable_unprepare(res->master_clk);
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clk_disable_unprepare(res->cfg_clk);
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clk_disable_unprepare(res->aux_clk);
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}
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static void qcom_pcie_host_init(struct pcie_port *pp)
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{
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struct qcom_pcie *pcie = to_qcom_pcie(pp);
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@ -444,6 +597,9 @@ static void qcom_pcie_host_init(struct pcie_port *pp)
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if (ret)
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goto err_deinit;
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if (pcie->ops->post_init)
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pcie->ops->post_init(pcie);
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dw_pcie_setup_rc(pp);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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@ -487,12 +643,22 @@ static const struct qcom_pcie_ops ops_v0 = {
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.get_resources = qcom_pcie_get_resources_v0,
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.init = qcom_pcie_init_v0,
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.deinit = qcom_pcie_deinit_v0,
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.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
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};
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static const struct qcom_pcie_ops ops_v1 = {
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.get_resources = qcom_pcie_get_resources_v1,
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.init = qcom_pcie_init_v1,
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.deinit = qcom_pcie_deinit_v1,
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.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
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};
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static const struct qcom_pcie_ops ops_v2 = {
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.get_resources = qcom_pcie_get_resources_v2,
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.init = qcom_pcie_init_v2,
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.post_init = qcom_pcie_post_init_v2,
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.deinit = qcom_pcie_deinit_v2,
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.ltssm_enable = qcom_pcie_v2_ltssm_enable,
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};
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static int qcom_pcie_probe(struct platform_device *pdev)
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@ -572,6 +738,7 @@ static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
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{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
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{ .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
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{ .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },
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{ }
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};
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