clocksource/drivers/stm32: Convert the driver to timer_of primitives
Convert the driver to use the timer_of() helpers. This allows the removal of a custom private structure, factors out and simplifies the code. [Daniel Lezcano]: Respin against the critical fix patch and massaged the changelog. Tested-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1515418139-23276-12-git-send-email-daniel.lezcano@linaro.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Benjamin Gaignard
Ingo Molnar
Родитель
e0aeca3d8c
Коммит
d04af4908a
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@ -269,6 +269,7 @@ config CLKSRC_STM32
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bool "Clocksource for STM32 SoCs" if !ARCH_STM32
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depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
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select CLKSRC_MMIO
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select TIMER_OF
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config CLKSRC_MPS2
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bool "Clocksource for MPS2 SoCs" if COMPILE_TEST
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@ -16,6 +16,9 @@
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include "timer-of.h"
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#define TIM_CR1 0x00
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#define TIM_DIER 0x0c
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@ -34,162 +37,118 @@
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#define TIM_EGR_UG BIT(0)
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struct stm32_clock_event_ddata {
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struct clock_event_device evtdev;
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unsigned periodic_top;
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void __iomem *base;
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};
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static int stm32_clock_event_shutdown(struct clock_event_device *evtdev)
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static int stm32_clock_event_shutdown(struct clock_event_device *clkevt)
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{
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struct stm32_clock_event_ddata *data =
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container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
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void *base = data->base;
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struct timer_of *to = to_timer_of(clkevt);
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writel_relaxed(0, timer_of_base(to) + TIM_CR1);
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writel_relaxed(0, base + TIM_CR1);
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return 0;
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}
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static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)
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static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt)
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{
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struct stm32_clock_event_ddata *data =
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container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
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void *base = data->base;
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struct timer_of *to = to_timer_of(clkevt);
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writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR);
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writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
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writel_relaxed(data->periodic_top, base + TIM_ARR);
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writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1);
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return 0;
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}
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static int stm32_clock_event_set_next_event(unsigned long evt,
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struct clock_event_device *evtdev)
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struct clock_event_device *clkevt)
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{
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struct stm32_clock_event_ddata *data =
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container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
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struct timer_of *to = to_timer_of(clkevt);
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writel_relaxed(evt, data->base + TIM_ARR);
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writel_relaxed(evt, timer_of_base(to) + TIM_ARR);
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writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,
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data->base + TIM_CR1);
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timer_of_base(to) + TIM_CR1);
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return 0;
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}
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static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
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{
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struct stm32_clock_event_ddata *data = dev_id;
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struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(clkevt);
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writel_relaxed(0, data->base + TIM_SR);
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writel_relaxed(0, timer_of_base(to) + TIM_SR);
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data->evtdev.event_handler(&data->evtdev);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static struct stm32_clock_event_ddata clock_event_ddata = {
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.evtdev = {
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.name = "stm32 clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.set_state_shutdown = stm32_clock_event_shutdown,
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.set_state_periodic = stm32_clock_event_set_periodic,
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.set_state_oneshot = stm32_clock_event_shutdown,
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.tick_resume = stm32_clock_event_shutdown,
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.set_next_event = stm32_clock_event_set_next_event,
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.rating = 200,
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},
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};
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static int __init stm32_clockevent_init(struct device_node *np)
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static void __init stm32_clockevent_init(struct timer_of *to)
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{
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struct stm32_clock_event_ddata *data = &clock_event_ddata;
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struct clk *clk;
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struct reset_control *rstc;
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unsigned long rate, max_delta;
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int irq, ret, bits, prescaler = 1;
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unsigned long max_delta;
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int prescaler;
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data = kmemdup(&clock_event_ddata, sizeof(*data), GFP_KERNEL);
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if (!data)
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to->clkevt.name = "stm32_clockevent";
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to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
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to->clkevt.set_state_shutdown = stm32_clock_event_shutdown;
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to->clkevt.set_state_periodic = stm32_clock_event_set_periodic;
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to->clkevt.set_state_oneshot = stm32_clock_event_shutdown;
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to->clkevt.tick_resume = stm32_clock_event_shutdown;
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to->clkevt.set_next_event = stm32_clock_event_set_next_event;
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/* Detect whether the timer is 16 or 32 bits */
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writel_relaxed(~0U, timer_of_base(to) + TIM_ARR);
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max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR);
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if (max_delta == ~0U) {
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prescaler = 1;
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to->clkevt.rating = 250;
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} else {
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prescaler = 1024;
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to->clkevt.rating = 100;
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}
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writel_relaxed(0, timer_of_base(to) + TIM_ARR);
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writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
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writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
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writel_relaxed(0, timer_of_base(to) + TIM_SR);
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writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER);
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/* Adjust rate and period given the prescaler value */
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to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler);
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to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
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clockevents_config_and_register(&to->clkevt,
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timer_of_rate(to), 0x1, max_delta);
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pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
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to->np, max_delta == UINT_MAX ? 32 : 16);
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}
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static int __init stm32_timer_init(struct device_node *node)
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{
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struct reset_control *rstc;
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struct timer_of *to;
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int ret;
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to = kzalloc(sizeof(*to), GFP_KERNEL);
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if (!to)
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return -ENOMEM;
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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pr_err("failed to get clock for clockevent (%d)\n", ret);
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goto err_clk_get;
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}
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to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
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to->of_irq.handler = stm32_clock_event_handler;
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("failed to enable timer clock for clockevent (%d)\n",
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ret);
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goto err_clk_enable;
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}
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ret = timer_of_init(node, to);
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if (ret)
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goto err;
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rate = clk_get_rate(clk);
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rstc = of_reset_control_get(np, NULL);
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rstc = of_reset_control_get(node, NULL);
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if (!IS_ERR(rstc)) {
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reset_control_assert(rstc);
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reset_control_deassert(rstc);
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}
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data->base = of_iomap(np, 0);
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if (!data->base) {
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ret = -ENXIO;
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pr_err("failed to map registers for clockevent\n");
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goto err_iomap;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -EINVAL;
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pr_err("%pOF: failed to get irq.\n", np);
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goto err_get_irq;
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}
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/* Detect whether the timer is 16 or 32 bits */
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writel_relaxed(~0U, data->base + TIM_ARR);
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max_delta = readl_relaxed(data->base + TIM_ARR);
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if (max_delta == ~0U) {
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prescaler = 1;
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bits = 32;
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} else {
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prescaler = 1024;
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bits = 16;
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}
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writel_relaxed(0, data->base + TIM_ARR);
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writel_relaxed(prescaler - 1, data->base + TIM_PSC);
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writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR);
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writel_relaxed(0, data->base + TIM_SR);
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writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER);
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data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ);
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clockevents_config_and_register(&data->evtdev,
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DIV_ROUND_CLOSEST(rate, prescaler),
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0x1, max_delta);
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ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,
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"stm32 clockevent", data);
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if (ret) {
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pr_err("%pOF: failed to request irq.\n", np);
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goto err_get_irq;
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}
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pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
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np, bits);
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return ret;
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err_get_irq:
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iounmap(data->base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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err_clk_get:
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kfree(data);
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stm32_clockevent_init(to);
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return 0;
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err:
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kfree(to);
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return ret;
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}
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TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init);
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TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);
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