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clk: sunxi-ng: Add A33 CCU support 

This commit introduces the clocks found in the Allwinner A33 CCU.

Since this SoC is very similar to the A23, and we share a significant share
of the DTSI, the clock IDs that are going to be used will also be shared
with the A23, hence the name of the various header files.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Maxime Ripard 2016-08-24 14:10:15 +02:00
Родитель aa15233517
Коммит d05c748bd7
7 изменённых файлов: 1071 добавлений и 0 удалений
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1
Documentation/devicetree/bindings/clock/sunxi-ccu.txt
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@ -4,6 +4,7 @@ Allwinner Clock Control Unit Binding
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
- reg: Must contain the registers base address and length

12
drivers/clk/sunxi-ng/Kconfig
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@ -65,6 +65,18 @@ config SUN6I_A31_CCU
select SUNXI_CCU_PHASE
default MACH_SUN6I
config SUN8I_A33_CCU
bool "Support for the Allwinner A33 CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_MULT
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
select SUNXI_CCU_NKMP
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
default MACH_SUN8I
config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV

1
drivers/clk/sunxi-ng/Makefile
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@ -19,4 +19,5 @@ obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
# SoC support
obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o

63
drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h Normal file
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@ -0,0 +1,63 @@
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CCU_SUN8I_A23_A33_H_
#define _CCU_SUN8I_A23_A33_H_
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
#define CLK_PLL_CPUX 0
#define CLK_PLL_AUDIO_BASE 1
#define CLK_PLL_AUDIO 2
#define CLK_PLL_AUDIO_2X 3
#define CLK_PLL_AUDIO_4X 4
#define CLK_PLL_AUDIO_8X 5
#define CLK_PLL_VIDEO 6
#define CLK_PLL_VIDEO_2X 7
#define CLK_PLL_VE 8
#define CLK_PLL_DDR0 9
#define CLK_PLL_PERIPH 10
#define CLK_PLL_PERIPH_2X 11
#define CLK_PLL_GPU 12
#define CLK_PLL_MIPI 13
#define CLK_PLL_HSIC 14
#define CLK_PLL_DE 15
#define CLK_PLL_DDR1 16
#define CLK_PLL_DDR 17
/* The CPUX clock is exported */
#define CLK_AXI 19
#define CLK_AHB1 20
#define CLK_APB1 21
#define CLK_APB2 22
/* All the bus gates are exported */
/* The first part of the mod clocks is exported */
#define CLK_DRAM 79
/* Some more module clocks are exported */
#define CLK_MBUS 95
/* And the last module clocks are exported */
#define CLK_NUMBER (CLK_ATS + 1)
#endif /* _CCU_SUN8I_A23_A33_H_ */

780
drivers/clk/sunxi-ng/ccu-sun8i-a33.c Normal file
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@ -0,0 +1,780 @@
/*
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun8i-a23-a33.h"
static struct ccu_nkmp pll_cpux_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
&ccu_nkmp_ops,
0),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* We don't have any need for the variable divider for now, so we just
* hardcode it to match with the clock names
*/
#define SUN8I_A33_PLL_AUDIO_REG 0x008
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
"osc24M", 0x028,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The MIPI PLL has 2 modes: "MIPI" and "HDMI".
*
* The MIPI mode is a standard NKM-style clock. The HDMI mode is an
* integer / fractional clock with switchable multipliers and dividers.
* This is not supported here. We hardcode the PLL to MIPI mode.
*/
#define SUN8I_A33_PLL_MIPI_REG 0x040
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
"pll-video", 0x040,
8, 4, /* N */
4, 2, /* K */
0, 4, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
"osc24M", 0x044,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/* TODO: Fix N */
static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
"osc24M", 0x04c,
8, 6, /* N */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x050, 16, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.variable_prediv = {
.index = 3,
.shift = 6,
.width = 2,
},
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph" , "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
0x064, BIT(25), 0);
static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
0x064, BIT(26), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
0x06c, BIT(20), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), 0);
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0x0b4, 16, 2, BIT(31), 0);
/* TODO: the parent for most of the USB clocks is not known */
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
0x0cc, BIT(11), 0);
static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
0x0f4, 0, 4, CLK_IS_CRITICAL);
static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
0x0f8, 16, 1, 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
0x100, BIT(16), 0);
static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
0x100, BIT(24), 0);
static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
0x100, BIT(26), 0);
static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
"pll-gpu", "pll-de" };
static const u8 de_table[] = { 0, 2, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
de_parents, de_table,
0x104, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
de_parents, de_table,
0x10c, 0, 4, 24, 3, BIT(31), 0);
static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
"pll-mipi" };
static const u8 lcd_ch0_table[] = { 0, 2, 4 };
static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
lcd_ch0_parents, lcd_ch0_table,
0x118, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
static const u8 lcd_ch1_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
lcd_ch1_parents, lcd_ch1_table,
0x12c, 0, 4, 24, 2, BIT(31), 0);
static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
"pll-mipi", "pll-ve" };
static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
csi_sclk_parents, csi_sclk_table,
0x134, 16, 4, 24, 3, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
"osc24M" };
static const u8 csi_mclk_table[] = { 0, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
csi_mclk_parents, csi_mclk_table,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), 0);
static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
0x140, BIT(30), 0);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
"pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
static const u8 dsi_sclk_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
dsi_sclk_parents, dsi_sclk_table,
0x168, 16, 4, 24, 2, BIT(31), 0);
static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
static const u8 dsi_dphy_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table,
0x168, 0, 4, 8, 2, BIT(15), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
de_parents, de_table,
0x180, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), 0);
static const char * const ats_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
0x1b0, 0, 3, 24, 2, BIT(31), 0);
static struct ccu_common *sun8i_a33_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
&pll_periph_clk.common,
&pll_gpu_clk.common,
&pll_mipi_clk.common,
&pll_hsic_clk.common,
&pll_de_clk.common,
&pll_ddr1_clk.common,
&pll_ddr_clk.common,
&cpux_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&bus_mipi_dsi_clk.common,
&bus_ss_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ehci_clk.common,
&bus_ohci_clk.common,
&bus_ve_clk.common,
&bus_lcd_clk.common,
&bus_csi_clk.common,
&bus_de_fe_clk.common,
&bus_de_be_clk.common,
&bus_gpu_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_drc_clk.common,
&bus_sat_clk.common,
&bus_codec_clk.common,
&bus_pio_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_hsic_clk.common,
&usb_hsic_12M_clk.common,
&usb_ohci_clk.common,
&dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_drc_clk.common,
&dram_de_fe_clk.common,
&dram_de_be_clk.common,
&de_be_clk.common,
&de_fe_clk.common,
&lcd_ch0_clk.common,
&lcd_ch1_clk.common,
&csi_sclk_clk.common,
&csi_mclk_clk.common,
&ve_clk.common,
&ac_dig_clk.common,
&ac_dig_4x_clk.common,
&avs_clk.common,
&mbus_clk.common,
&dsi_sclk_clk.common,
&dsi_dphy_clk.common,
&drc_clk.common,
&gpu_clk.common,
&ats_clk.common,
};
/* We hardcode the divider to 4 for now */
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
"pll-periph", 1, 2, 0);
static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
"pll-video", 1, 2, 0);
static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
.hws = {
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
[CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_SS] = &bus_ss_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
[CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
[CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_DRC] = &bus_drc_clk.common.hw,
[CLK_BUS_SAT] = &bus_sat_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
[CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
[CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
[CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
[CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
[CLK_DRC] = &drc_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_ATS] = &ats_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_BUS_SS] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_LCD] = { 0x2c4, BIT(4) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
[RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_DRC] = { 0x2c4, BIT(25) },
[RST_BUS_SAT] = { 0x2c4, BIT(26) },
[RST_BUS_LVDS] = { 0x2c8, BIT(0) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2C0] = { 0x2d4, BIT(0) },
[RST_BUS_I2C1] = { 0x2d4, BIT(1) },
[RST_BUS_I2C2] = { 0x2d4, BIT(2) },
[RST_BUS_UART0] = { 0x2d4, BIT(16) },
[RST_BUS_UART1] = { 0x2d4, BIT(17) },
[RST_BUS_UART2] = { 0x2d4, BIT(18) },
[RST_BUS_UART3] = { 0x2d4, BIT(19) },
[RST_BUS_UART4] = { 0x2d4, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
.ccu_clks = sun8i_a33_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a33_ccu_clks),
.hw_clks = &sun8i_a33_hw_clks,
.resets = sun8i_a33_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
};
static void __init sun8i_a33_ccu_setup(struct device_node *node)
{
void __iomem *reg;
u32 val;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
pr_err("%s: Could not map the clock registers\n",
of_node_full_name(node));
return;
}
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
/* Force PLL-MIPI to MIPI mode */
val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
val &= ~BIT(16);
writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
}
CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
sun8i_a33_ccu_setup);

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include/dt-bindings/clock/sun8i-a23-a33-ccu.h Normal file
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/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define CLK_CPUX 18
#define CLK_BUS_MIPI_DSI 23
#define CLK_BUS_SS 24
#define CLK_BUS_DMA 25
#define CLK_BUS_MMC0 26
#define CLK_BUS_MMC1 27
#define CLK_BUS_MMC2 28
#define CLK_BUS_NAND 29
#define CLK_BUS_DRAM 30
#define CLK_BUS_HSTIMER 31
#define CLK_BUS_SPI0 32
#define CLK_BUS_SPI1 33
#define CLK_BUS_OTG 34
#define CLK_BUS_EHCI 35
#define CLK_BUS_OHCI 36
#define CLK_BUS_VE 37
#define CLK_BUS_LCD 38
#define CLK_BUS_CSI 39
#define CLK_BUS_DE_BE 40
#define CLK_BUS_DE_FE 41
#define CLK_BUS_GPU 42
#define CLK_BUS_MSGBOX 43
#define CLK_BUS_SPINLOCK 44
#define CLK_BUS_DRC 45
#define CLK_BUS_SAT 46
#define CLK_BUS_CODEC 47
#define CLK_BUS_PIO 48
#define CLK_BUS_I2S0 49
#define CLK_BUS_I2S1 50
#define CLK_BUS_I2C0 51
#define CLK_BUS_I2C1 52
#define CLK_BUS_I2C2 53
#define CLK_BUS_UART0 54
#define CLK_BUS_UART1 55
#define CLK_BUS_UART2 56
#define CLK_BUS_UART3 57
#define CLK_BUS_UART4 58
#define CLK_NAND 59
#define CLK_MMC0 60
#define CLK_MMC0_SAMPLE 61
#define CLK_MMC0_OUTPUT 62
#define CLK_MMC1 63
#define CLK_MMC1_SAMPLE 64
#define CLK_MMC1_OUTPUT 65
#define CLK_MMC2 66
#define CLK_MMC2_SAMPLE 67
#define CLK_MMC2_OUTPUT 68
#define CLK_SS 69
#define CLK_SPI0 70
#define CLK_SPI1 71
#define CLK_I2S0 72
#define CLK_I2S1 73
#define CLK_USB_PHY0 74
#define CLK_USB_PHY1 75
#define CLK_USB_HSIC 76
#define CLK_USB_HSIC_12M 77
#define CLK_USB_OHCI 78
#define CLK_DRAM_VE 80
#define CLK_DRAM_CSI 81
#define CLK_DRAM_DRC 82
#define CLK_DRAM_DE_FE 83
#define CLK_DRAM_DE_BE 84
#define CLK_DE_BE 85
#define CLK_DE_FE 86
#define CLK_LCD_CH0 87
#define CLK_LCD_CH1 88
#define CLK_CSI_SCLK 89
#define CLK_CSI_MCLK 90
#define CLK_VE 91
#define CLK_AC_DIG 92
#define CLK_AC_DIG_4X 93
#define CLK_AVS 94
#define CLK_DSI_SCLK 96
#define CLK_DSI_DPHY 97
#define CLK_DRC 98
#define CLK_GPU 99
#define CLK_ATS 100
#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */

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include/dt-bindings/reset/sun8i-a23-a33-ccu.h Normal file
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/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_
#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_MBUS 3
#define RST_BUS_MIPI_DSI 4
#define RST_BUS_SS 5
#define RST_BUS_DMA 6
#define RST_BUS_MMC0 7
#define RST_BUS_MMC1 8
#define RST_BUS_MMC2 9
#define RST_BUS_NAND 10
#define RST_BUS_DRAM 11
#define RST_BUS_HSTIMER 12
#define RST_BUS_SPI0 13
#define RST_BUS_SPI1 14
#define RST_BUS_OTG 15
#define RST_BUS_EHCI 16
#define RST_BUS_OHCI 17
#define RST_BUS_VE 18
#define RST_BUS_LCD 19
#define RST_BUS_CSI 20
#define RST_BUS_DE_BE 21
#define RST_BUS_DE_FE 22
#define RST_BUS_GPU 23
#define RST_BUS_MSGBOX 24
#define RST_BUS_SPINLOCK 25
#define RST_BUS_DRC 26
#define RST_BUS_SAT 27
#define RST_BUS_LVDS 28
#define RST_BUS_CODEC 29
#define RST_BUS_I2S0 30
#define RST_BUS_I2S1 31
#define RST_BUS_I2C0 32
#define RST_BUS_I2C1 33
#define RST_BUS_I2C2 34
#define RST_BUS_UART0 35
#define RST_BUS_UART1 36
#define RST_BUS_UART2 37
#define RST_BUS_UART3 38
#define RST_BUS_UART4 39
#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */