[SCSI] pm80xx: Firmware logging support.
Supports below logging facilities, Inbound outbound queues dump. Non fatal dump in case of IO failures. Fatal dump in case of firmware failure. [jejb: checkpatch spacing fixes] Signed-off-by: Anandkumar.Santhanam@pmcs.com Reviewed-by: Jack Wang <jinpu.wang@profitbricks.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Anand Kumar Santhanam
James Bottomley
Родитель
279094079a
Коммит
d078b5117f
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@ -308,6 +308,84 @@ static ssize_t pm8001_ctl_aap_log_show(struct device *cdev,
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return str - buf;
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}
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static DEVICE_ATTR(aap_log, S_IRUGO, pm8001_ctl_aap_log_show, NULL);
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/**
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* pm8001_ctl_ib_queue_log_show - Out bound Queue log
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* @cdev:pointer to embedded class device
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* @buf: the buffer returned
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* A sysfs 'read-only' shost attribute.
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*/
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static ssize_t pm8001_ctl_ib_queue_log_show(struct device *cdev,
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struct device_attribute *attr, char *buf)
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{
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struct Scsi_Host *shost = class_to_shost(cdev);
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struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
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struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
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int offset;
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char *str = buf;
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int start = 0;
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#define IB_MEMMAP(c) \
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(*(u32 *)((u8 *)pm8001_ha-> \
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memoryMap.region[IB].virt_ptr + \
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pm8001_ha->evtlog_ib_offset + (c)))
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for (offset = 0; offset < IB_OB_READ_TIMES; offset++) {
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if (pm8001_ha->chip_id != chip_8001)
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str += sprintf(str, "0x%08x\n", IB_MEMMAP(start));
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else
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str += sprintf(str, "0x%08x\n", IB_MEMMAP(start));
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start = start + 4;
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}
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pm8001_ha->evtlog_ib_offset += SYSFS_OFFSET;
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if ((((pm8001_ha->evtlog_ib_offset) % (PM80XX_IB_OB_QUEUE_SIZE)) == 0)
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&& (pm8001_ha->chip_id != chip_8001))
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pm8001_ha->evtlog_ib_offset = 0;
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if ((((pm8001_ha->evtlog_ib_offset) % (PM8001_IB_OB_QUEUE_SIZE)) == 0)
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&& (pm8001_ha->chip_id == chip_8001))
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pm8001_ha->evtlog_ib_offset = 0;
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return str - buf;
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}
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static DEVICE_ATTR(ib_log, S_IRUGO, pm8001_ctl_ib_queue_log_show, NULL);
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/**
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* pm8001_ctl_ob_queue_log_show - Out bound Queue log
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* @cdev:pointer to embedded class device
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* @buf: the buffer returned
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* A sysfs 'read-only' shost attribute.
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*/
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static ssize_t pm8001_ctl_ob_queue_log_show(struct device *cdev,
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struct device_attribute *attr, char *buf)
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{
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struct Scsi_Host *shost = class_to_shost(cdev);
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struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
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struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
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int offset;
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char *str = buf;
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int start = 0;
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#define OB_MEMMAP(c) \
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(*(u32 *)((u8 *)pm8001_ha-> \
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memoryMap.region[OB].virt_ptr + \
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pm8001_ha->evtlog_ob_offset + (c)))
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for (offset = 0; offset < IB_OB_READ_TIMES; offset++) {
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if (pm8001_ha->chip_id != chip_8001)
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str += sprintf(str, "0x%08x\n", OB_MEMMAP(start));
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else
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str += sprintf(str, "0x%08x\n", OB_MEMMAP(start));
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start = start + 4;
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}
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pm8001_ha->evtlog_ob_offset += SYSFS_OFFSET;
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if ((((pm8001_ha->evtlog_ob_offset) % (PM80XX_IB_OB_QUEUE_SIZE)) == 0)
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&& (pm8001_ha->chip_id != chip_8001))
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pm8001_ha->evtlog_ob_offset = 0;
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if ((((pm8001_ha->evtlog_ob_offset) % (PM8001_IB_OB_QUEUE_SIZE)) == 0)
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&& (pm8001_ha->chip_id == chip_8001))
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pm8001_ha->evtlog_ob_offset = 0;
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return str - buf;
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}
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static DEVICE_ATTR(ob_log, S_IRUGO, pm8001_ctl_ob_queue_log_show, NULL);
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/**
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* pm8001_ctl_bios_version_show - Bios version Display
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* @cdev:pointer to embedded class device
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@ -377,6 +455,43 @@ static ssize_t pm8001_ctl_iop_log_show(struct device *cdev,
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}
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static DEVICE_ATTR(iop_log, S_IRUGO, pm8001_ctl_iop_log_show, NULL);
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/**
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** pm8001_ctl_fatal_log_show - fatal error logging
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** @cdev:pointer to embedded class device
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** @buf: the buffer returned
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**
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** A sysfs 'read-only' shost attribute.
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**/
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static ssize_t pm8001_ctl_fatal_log_show(struct device *cdev,
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struct device_attribute *attr, char *buf)
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{
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u32 count;
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count = pm80xx_get_fatal_dump(cdev, attr, buf);
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return count;
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}
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static DEVICE_ATTR(fatal_log, S_IRUGO, pm8001_ctl_fatal_log_show, NULL);
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/**
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** pm8001_ctl_gsm_log_show - gsm dump collection
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** @cdev:pointer to embedded class device
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** @buf: the buffer returned
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**A sysfs 'read-only' shost attribute.
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**/
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static ssize_t pm8001_ctl_gsm_log_show(struct device *cdev,
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struct device_attribute *attr, char *buf)
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{
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u32 count;
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count = pm8001_get_gsm_dump(cdev, SYSFS_OFFSET, buf);
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return count;
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}
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static DEVICE_ATTR(gsm_log, S_IRUGO, pm8001_ctl_gsm_log_show, NULL);
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#define FLASH_CMD_NONE 0x00
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#define FLASH_CMD_UPDATE 0x01
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#define FLASH_CMD_SET_NVMD 0x02
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@ -636,6 +751,8 @@ struct device_attribute *pm8001_host_attrs[] = {
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&dev_attr_update_fw,
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&dev_attr_aap_log,
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&dev_attr_iop_log,
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&dev_attr_fatal_log,
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&dev_attr_gsm_log,
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&dev_attr_max_out_io,
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&dev_attr_max_devices,
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&dev_attr_max_sg_list,
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@ -643,6 +760,8 @@ struct device_attribute *pm8001_host_attrs[] = {
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&dev_attr_logging_level,
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&dev_attr_host_sas_address,
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&dev_attr_bios_version,
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&dev_attr_ib_log,
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&dev_attr_ob_log,
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NULL,
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};
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@ -55,5 +55,9 @@
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#define FAIL_OUT_MEMORY 0x000c00
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#define FLASH_IN_PROGRESS 0x001000
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#define IB_OB_READ_TIMES 256
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#define SYSFS_OFFSET 1024
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#define PM80XX_IB_OB_QUEUE_SIZE (32 * 1024)
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#define PM8001_IB_OB_QUEUE_SIZE (16 * 1024)
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#endif /* PM8001_CTL_H_INCLUDED */
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@ -102,7 +102,8 @@ enum memory_region_num {
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NVMD, /* NVM device */
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DEV_MEM, /* memory for devices */
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CCB_MEM, /* memory for command control block */
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FW_FLASH /* memory for fw flash update */
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FW_FLASH, /* memory for fw flash update */
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FORENSIC_MEM /* memory for fw forensic data */
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};
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#define PM8001_EVENT_LOG_SIZE (128 * 1024)
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@ -5001,6 +5001,89 @@ pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
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return rc;
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}
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ssize_t
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pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
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{
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u32 value, rem, offset = 0, bar = 0;
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u32 index, work_offset, dw_length;
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u32 shift_value, gsm_base, gsm_dump_offset;
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char *direct_data;
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struct Scsi_Host *shost = class_to_shost(cdev);
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struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
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struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
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direct_data = buf;
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gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
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/* check max is 1 Mbytes */
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if ((length > 0x100000) || (gsm_dump_offset & 3) ||
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((gsm_dump_offset + length) > 0x1000000))
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return 1;
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if (pm8001_ha->chip_id == chip_8001)
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bar = 2;
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else
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bar = 1;
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work_offset = gsm_dump_offset & 0xFFFF0000;
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offset = gsm_dump_offset & 0x0000FFFF;
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gsm_dump_offset = work_offset;
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/* adjust length to dword boundary */
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rem = length & 3;
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dw_length = length >> 2;
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for (index = 0; index < dw_length; index++) {
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if ((work_offset + offset) & 0xFFFF0000) {
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if (pm8001_ha->chip_id == chip_8001)
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shift_value = ((gsm_dump_offset + offset) &
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SHIFT_REG_64K_MASK);
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else
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shift_value = (((gsm_dump_offset + offset) &
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SHIFT_REG_64K_MASK) >>
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SHIFT_REG_BIT_SHIFT);
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if (pm8001_ha->chip_id == chip_8001) {
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gsm_base = GSM_BASE;
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if (-1 == pm8001_bar4_shift(pm8001_ha,
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(gsm_base + shift_value)))
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return 1;
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} else {
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gsm_base = 0;
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if (-1 == pm80xx_bar4_shift(pm8001_ha,
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(gsm_base + shift_value)))
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return 1;
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}
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gsm_dump_offset = (gsm_dump_offset + offset) &
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0xFFFF0000;
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work_offset = 0;
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offset = offset & 0x0000FFFF;
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}
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value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
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0x0000FFFF);
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direct_data += sprintf(direct_data, "%08x ", value);
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offset += 4;
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}
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if (rem != 0) {
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value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
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0x0000FFFF);
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/* xfr for non_dw */
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direct_data += sprintf(direct_data, "%08x ", value);
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}
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/* Shift back to BAR4 original address */
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if (pm8001_ha->chip_id == chip_8001) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
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return 1;
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} else {
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if (-1 == pm80xx_bar4_shift(pm8001_ha, 0))
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return 1;
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}
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pm8001_ha->fatal_forensic_shift_offset += 1024;
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if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
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pm8001_ha->fatal_forensic_shift_offset = 0;
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return direct_data - buf;
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}
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int
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pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
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struct pm8001_device *pm8001_dev, u32 state)
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@ -1027,5 +1027,8 @@ struct set_dev_state_resp {
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#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
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#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
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#define GSM_BASE 0x4F0000
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#define SHIFT_REG_64K_MASK 0xffff0000
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#define SHIFT_REG_BIT_SHIFT 8
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#endif
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@ -347,6 +347,10 @@ static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
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/* Memory region for fw flash */
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pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
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pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
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pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
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pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
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pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
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for (i = 0; i < USI_MAX_MEMCNT; i++) {
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if (pm8001_mem_alloc(pm8001_ha->pdev,
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&pm8001_ha->memoryMap.region[i].virt_ptr,
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@ -132,6 +132,61 @@ struct pm8001_ioctl_payload {
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u8 *func_specific;
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};
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#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
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#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
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#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
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#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
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#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
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#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
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#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
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#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
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#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
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#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
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#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
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#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
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#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
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#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
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#define TYPE_GSM_SPACE 1
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#define TYPE_QUEUE 2
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#define TYPE_FATAL 3
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#define TYPE_NON_FATAL 4
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#define TYPE_INBOUND 1
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#define TYPE_OUTBOUND 2
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struct forensic_data {
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u32 data_type;
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union {
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struct {
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u32 direct_len;
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u32 direct_offset;
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void *direct_data;
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} gsm_buf;
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struct {
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u16 queue_type;
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u16 queue_index;
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u32 direct_len;
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void *direct_data;
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} queue_buf;
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struct {
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u32 direct_len;
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u32 direct_offset;
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u32 read_len;
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void *direct_data;
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} data_buf;
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};
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};
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/* bit31-26 - mask bar */
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#define SCRATCH_PAD0_BAR_MASK 0xFC000000
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/* bit25-0 - offset mask */
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#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
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/* if AAP error state */
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#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
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/* Inbound doorbell bit7 */
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#define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
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/* Inbound doorbell bit7 SPCV */
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#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
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#define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
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struct pm8001_dispatch {
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char *name;
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int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
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@ -346,6 +401,7 @@ union main_cfg_table {
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u32 phy_attr_table_offset;
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u32 port_recovery_timer;
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u32 interrupt_reassertion_delay;
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u32 fatal_n_non_fatal_dump; /* 0x28 */
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} pm80xx_tbl;
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};
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@ -420,6 +476,13 @@ struct pm8001_hba_info {
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struct pm8001_hba_memspace io_mem[6];
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struct mpi_mem_req memoryMap;
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struct encrypt encrypt_info; /* support encryption */
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struct forensic_data forensic_info;
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u32 fatal_bar_loc;
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u32 forensic_last_offset;
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u32 fatal_forensic_shift_offset;
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u32 forensic_fatal_step;
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u32 evtlog_ib_offset;
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u32 evtlog_ob_offset;
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void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
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void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
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void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
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@ -428,6 +491,7 @@ struct pm8001_hba_info {
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void __iomem *pspa_q_tbl_addr;
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/*MPI SAS PHY attributes Queue Config Table Addr*/
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void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
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void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
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union main_cfg_table main_cfg_tbl;
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union general_status_table gs_tbl;
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struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
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@ -634,6 +698,10 @@ int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
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int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
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u32 length, u8 *buf);
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int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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ssize_t pm80xx_get_fatal_dump(struct device *cdev,
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struct device_attribute *attr, char *buf);
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ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
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/* ctl shared API */
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extern struct device_attribute *pm8001_host_attrs[];
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@ -45,6 +45,228 @@
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#define SMP_DIRECT 1
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#define SMP_INDIRECT 2
|
||||
|
||||
|
||||
int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
|
||||
{
|
||||
u32 reg_val;
|
||||
unsigned long start;
|
||||
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
|
||||
/* confirm the setting is written */
|
||||
start = jiffies + HZ; /* 1 sec */
|
||||
do {
|
||||
reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
|
||||
} while ((reg_val != shift_value) && time_before(jiffies, start));
|
||||
if (reg_val != shift_value) {
|
||||
PM8001_FAIL_DBG(pm8001_ha,
|
||||
pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
|
||||
" = 0x%x\n", reg_val));
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
|
||||
const void *destination,
|
||||
u32 dw_count, u32 bus_base_number)
|
||||
{
|
||||
u32 index, value, offset;
|
||||
u32 *destination1;
|
||||
destination1 = (u32 *)destination;
|
||||
|
||||
for (index = 0; index < dw_count; index += 4, destination1++) {
|
||||
offset = (soffset + index / 4);
|
||||
if (offset < (64 * 1024)) {
|
||||
value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
|
||||
*destination1 = cpu_to_le32(value);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
ssize_t pm80xx_get_fatal_dump(struct device *cdev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct Scsi_Host *shost = class_to_shost(cdev);
|
||||
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
||||
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
|
||||
void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
|
||||
u32 status = 1;
|
||||
u32 accum_len , reg_val, index, *temp;
|
||||
unsigned long start;
|
||||
u8 *direct_data;
|
||||
char *fatal_error_data = buf;
|
||||
|
||||
pm8001_ha->forensic_info.data_buf.direct_data = buf;
|
||||
if (pm8001_ha->chip_id == chip_8001) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
|
||||
"Not supported for SPC controller");
|
||||
return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
|
||||
(char *)buf;
|
||||
}
|
||||
if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
|
||||
PM8001_IO_DBG(pm8001_ha,
|
||||
pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
|
||||
direct_data = (u8 *)fatal_error_data;
|
||||
pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
|
||||
pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
|
||||
pm8001_ha->forensic_info.data_buf.direct_offset = 0;
|
||||
pm8001_ha->forensic_info.data_buf.read_len = 0;
|
||||
|
||||
pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
|
||||
}
|
||||
|
||||
if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
|
||||
/* start to get data */
|
||||
/* Program the MEMBASE II Shifting Register with 0x00.*/
|
||||
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
|
||||
pm8001_ha->fatal_forensic_shift_offset);
|
||||
pm8001_ha->forensic_last_offset = 0;
|
||||
pm8001_ha->forensic_fatal_step = 0;
|
||||
pm8001_ha->fatal_bar_loc = 0;
|
||||
}
|
||||
/* Read until accum_len is retrived */
|
||||
accum_len = pm8001_mr32(fatal_table_address,
|
||||
MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
|
||||
PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
|
||||
accum_len));
|
||||
if (accum_len == 0xFFFFFFFF) {
|
||||
PM8001_IO_DBG(pm8001_ha,
|
||||
pm8001_printk("Possible PCI issue 0x%x not expected\n",
|
||||
accum_len));
|
||||
return status;
|
||||
}
|
||||
if (accum_len == 0 || accum_len >= 0x100000) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
|
||||
"%08x ", 0xFFFFFFFF);
|
||||
return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
|
||||
(char *)buf;
|
||||
}
|
||||
temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
|
||||
if (pm8001_ha->forensic_fatal_step == 0) {
|
||||
moreData:
|
||||
if (pm8001_ha->forensic_info.data_buf.direct_data) {
|
||||
/* Data is in bar, copy to host memory */
|
||||
pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
|
||||
pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
|
||||
pm8001_ha->forensic_info.data_buf.direct_len ,
|
||||
1);
|
||||
}
|
||||
pm8001_ha->fatal_bar_loc +=
|
||||
pm8001_ha->forensic_info.data_buf.direct_len;
|
||||
pm8001_ha->forensic_info.data_buf.direct_offset +=
|
||||
pm8001_ha->forensic_info.data_buf.direct_len;
|
||||
pm8001_ha->forensic_last_offset +=
|
||||
pm8001_ha->forensic_info.data_buf.direct_len;
|
||||
pm8001_ha->forensic_info.data_buf.read_len =
|
||||
pm8001_ha->forensic_info.data_buf.direct_len;
|
||||
|
||||
if (pm8001_ha->forensic_last_offset >= accum_len) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
|
||||
"%08x ", 3);
|
||||
for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->
|
||||
forensic_info.data_buf.direct_data,
|
||||
"%08x ", *(temp + index));
|
||||
}
|
||||
|
||||
pm8001_ha->fatal_bar_loc = 0;
|
||||
pm8001_ha->forensic_fatal_step = 1;
|
||||
pm8001_ha->fatal_forensic_shift_offset = 0;
|
||||
pm8001_ha->forensic_last_offset = 0;
|
||||
status = 0;
|
||||
return (char *)pm8001_ha->
|
||||
forensic_info.data_buf.direct_data -
|
||||
(char *)buf;
|
||||
}
|
||||
if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->
|
||||
forensic_info.data_buf.direct_data,
|
||||
"%08x ", 2);
|
||||
for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->
|
||||
forensic_info.data_buf.direct_data,
|
||||
"%08x ", *(temp + index));
|
||||
}
|
||||
status = 0;
|
||||
return (char *)pm8001_ha->
|
||||
forensic_info.data_buf.direct_data -
|
||||
(char *)buf;
|
||||
}
|
||||
|
||||
/* Increment the MEMBASE II Shifting Register value by 0x100.*/
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
|
||||
"%08x ", 2);
|
||||
for (index = 0; index < 256; index++) {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->
|
||||
forensic_info.data_buf.direct_data,
|
||||
"%08x ", *(temp + index));
|
||||
}
|
||||
pm8001_ha->fatal_forensic_shift_offset += 0x100;
|
||||
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
|
||||
pm8001_ha->fatal_forensic_shift_offset);
|
||||
pm8001_ha->fatal_bar_loc = 0;
|
||||
status = 0;
|
||||
return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
|
||||
(char *)buf;
|
||||
}
|
||||
if (pm8001_ha->forensic_fatal_step == 1) {
|
||||
pm8001_ha->fatal_forensic_shift_offset = 0;
|
||||
/* Read 64K of the debug data. */
|
||||
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
|
||||
pm8001_ha->fatal_forensic_shift_offset);
|
||||
pm8001_mw32(fatal_table_address,
|
||||
MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
|
||||
MPI_FATAL_EDUMP_HANDSHAKE_RDY);
|
||||
|
||||
/* Poll FDDHSHK until clear */
|
||||
start = jiffies + (2 * HZ); /* 2 sec */
|
||||
|
||||
do {
|
||||
reg_val = pm8001_mr32(fatal_table_address,
|
||||
MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
|
||||
} while ((reg_val) && time_before(jiffies, start));
|
||||
|
||||
if (reg_val != 0) {
|
||||
PM8001_FAIL_DBG(pm8001_ha,
|
||||
pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
|
||||
" = 0x%x\n", reg_val));
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Read the next 64K of the debug data. */
|
||||
pm8001_ha->forensic_fatal_step = 0;
|
||||
if (pm8001_mr32(fatal_table_address,
|
||||
MPI_FATAL_EDUMP_TABLE_STATUS) !=
|
||||
MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
|
||||
pm8001_mw32(fatal_table_address,
|
||||
MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
|
||||
goto moreData;
|
||||
} else {
|
||||
pm8001_ha->forensic_info.data_buf.direct_data +=
|
||||
sprintf(pm8001_ha->
|
||||
forensic_info.data_buf.direct_data,
|
||||
"%08x ", 4);
|
||||
pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
|
||||
pm8001_ha->forensic_info.data_buf.direct_len = 0;
|
||||
pm8001_ha->forensic_info.data_buf.direct_offset = 0;
|
||||
pm8001_ha->forensic_info.data_buf.read_len = 0;
|
||||
status = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
|
||||
(char *)buf;
|
||||
}
|
||||
|
||||
/**
|
||||
* read_main_config_table - read the configure table and save it.
|
||||
* @pm8001_ha: our hba card information
|
||||
|
|
@ -583,6 +805,9 @@ static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
|
|||
pm8001_ha->pspa_q_tbl_addr =
|
||||
base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
|
||||
0xFFFFFF);
|
||||
pm8001_ha->fatal_tbl_addr =
|
||||
base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
|
||||
0xFFFFFF);
|
||||
|
||||
PM8001_INIT_DBG(pm8001_ha,
|
||||
pm8001_printk("GST OFFSET 0x%x\n",
|
||||
|
|
|
|||
|
|
@ -1525,4 +1525,6 @@ typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
|
|||
#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
|
||||
#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
|
||||
|
||||
|
||||
#define MEMBASE_II_SHIFT_REGISTER 0x1010
|
||||
#endif
|
||||
|
|
|
|||
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