microsoft
/
WSL2-Linux-Kernel
зеркало из https://github.com/microsoft/WSL2-Linux-Kernel.git
1
0
Форкнуть 0
Код Задачи Пакеты Проекты Релизы Вики Активность

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits)
  [ARM] spelling fixes
  [ARM] at91_adc parenthesis balance
  [ARM] 4400/1: S3C24XX: Add high-speed MMC device definition
  [ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings
  [ARM] 4398/1: S3C2443: Fix watchdog IRQ number
  [ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity
  [ARM] 4396/1: S3C2443: Add missing HCLK clocks
  [ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines
  [ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu
  [ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts
  [ARM] ARMv6: add CPU_HAS_ASID configuration
  [ARM] integrator: fix pci_v3 compile error with DEBUG_LL
  [ARM] gic: Fix gic cascade irq handling
  [ARM] Silence OMAP kernel configuration warning
  [ARM] Update ARM syscalls
  [ARM] 4384/1: S3C2412/13 SPI registers offset correction
  [ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
  [ARM] 4382/1: iop13xx: fix msi support
  [ARM] Remove Integrator/CP SMP platform support
  [ARM] 4378/1: KS8695: Serial driver fix
  ...
This commit is contained in:
Linus Torvalds 2007-05-21 10:00:22 -07:00
Родитель dde33348e5 6cbdc8c535
Коммит d07b3c2532
81 изменённых файлов: 237 добавлений и 444 удалений
Показать статистику Скачать Patch файл Скачать Diff файл Показать все файлы Свернуть все файлы

1
arch/arm/Kconfig
Просмотреть файл

@ -287,6 +287,7 @@ config ARCH_IXP2000
config ARCH_IXP4XX config ARCH_IXP4XX
bool "IXP4xx-based" bool "IXP4xx-based"
depends on MMU depends on MMU
select GENERIC_GPIO
select GENERIC_TIME select GENERIC_TIME
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
help help

2
arch/arm/common/dmabounce.c
Просмотреть файл

@ -6,7 +6,7 @@
* copy data to/from buffers located outside the DMA region. This * copy data to/from buffers located outside the DMA region. This
* only works for systems in which DMA memory is at the bottom of * only works for systems in which DMA memory is at the bottom of
* RAM, the remainder of memory is at the top and the DMA memory * RAM, the remainder of memory is at the top and the DMA memory
* can be marked as ZONE_DMA. Anything beyond that such as discontigous * can be marked as ZONE_DMA. Anything beyond that such as discontiguous
* DMA windows will require custom implementations that reserve memory * DMA windows will require custom implementations that reserve memory
* areas at early bootup. * areas at early bootup.
* *

22
arch/arm/common/gic.c
Просмотреть файл

@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq)
* unmask it, in the same way we need to unmask an interrupt when * unmask it, in the same way we need to unmask an interrupt when
* we first enable it. * we first enable it.
* *
* The GIC has a seperate notion of "end of interrupt" to re-enable * The GIC has a separate notion of "end of interrupt" to re-enable
* an interrupt after handling, in order to support hardware * an interrupt after handling, in order to support hardware
* prioritisation. * prioritisation.
* *
@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
} }
#endif #endif
static void fastcall gic_handle_cascade_irq(unsigned int irq, static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
struct irq_desc *desc)
{ {
struct gic_chip_data *chip_data = get_irq_data(irq); struct gic_chip_data *chip_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq); struct irq_chip *chip = get_irq_chip(irq);
unsigned int cascade_irq; unsigned int cascade_irq, gic_irq;
unsigned long status; unsigned long status;
/* primary controller ack'ing */ /* primary controller ack'ing */
@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq,
status = readl(chip_data->cpu_base + GIC_CPU_INTACK); status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock); spin_unlock(&irq_controller_lock);
cascade_irq = (status & 0x3ff); gic_irq = (status & 0x3ff);
if (cascade_irq > 1020) if (gic_irq == 1023)
goto out; goto out;
if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
do_bad_IRQ(cascade_irq, desc);
goto out;
}
cascade_irq += chip_data->irq_offset; cascade_irq = gic_irq + chip_data->irq_offset;
generic_handle_irq(cascade_irq); if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out: out:
/* primary controller unmasking */ /* primary controller unmasking */

2
arch/arm/common/sharpsl_param.c
Просмотреть файл

@ -20,7 +20,7 @@
* typically including LCD parameters are loaded by the bootloader at the * typically including LCD parameters are loaded by the bootloader at the
* address PARAM_BASE. As the kernel will overwrite them, we need to store * address PARAM_BASE. As the kernel will overwrite them, we need to store
* them early in the boot process, then pass them to the appropriate drivers. * them early in the boot process, then pass them to the appropriate drivers.
* Not all devices use all paramaters but the format is common to all. * Not all devices use all parameters but the format is common to all.
*/ */
#ifdef CONFIG_ARCH_SA1100 #ifdef CONFIG_ARCH_SA1100
#define PARAM_BASE 0xe8ffc000 #define PARAM_BASE 0xe8ffc000

22
arch/arm/common/sharpsl_pm.c
Просмотреть файл

@ -153,7 +153,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
sharpsl_pm.battstat.mainbat_percent = percent; sharpsl_pm.battstat.mainbat_percent = percent;
} }
dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %d\n", voltage, dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
/* If battery is low. limit backlight intensity to save power. */ /* If battery is low. limit backlight intensity to save power. */
@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data)
} }
/* Charging Finished Interrupt (Not present on Corgi) */ /* Charging Finished Interrupt (Not present on Corgi) */
/* Can trigger at the same time as an AC staus change so /* Can trigger at the same time as an AC status change so
delay until after that has been processed */ delay until after that has been processed */
irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id) irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
{ {
@ -625,7 +625,7 @@ static int sharpsl_fatal_check(void)
} }
temp = get_select_val(buff); temp = get_select_val(buff);
dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %d\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT));
if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) || if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) ||
(!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt))) (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt)))
@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void)
static int sharpsl_off_charge_error(void) static int sharpsl_off_charge_error(void)
{ {
dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n"); dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
sharpsl_pm.machinfo->charge(0); sharpsl_pm.machinfo->charge(0);
sharpsl_pm_led(SHARPSL_LED_ERROR); sharpsl_pm_led(SHARPSL_LED_ERROR);
sharpsl_pm.charge_mode = CHRG_ERROR; sharpsl_pm.charge_mode = CHRG_ERROR;
@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void)
time = RCNR; time = RCNR;
while(1) { while(1) {
/* Check if any wakeup event had occured */ /* Check if any wakeup event had occurred */
if (sharpsl_pm.machinfo->charger_wakeup() != 0) if (sharpsl_pm.machinfo->charger_wakeup() != 0)
return 0; return 0;
/* Check for timeout */ /* Check for timeout */
if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
return 1; return 1;
if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) { if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n"); dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
sharpsl_pm.full_count++; sharpsl_pm.full_count++;
sharpsl_pm.machinfo->charge(0); sharpsl_pm.machinfo->charge(0);
mdelay(SHARPSL_CHARGE_WAIT_TIME); mdelay(SHARPSL_CHARGE_WAIT_TIME);
@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void)
time = RCNR; time = RCNR;
while(1) { while(1) {
/* Check if any wakeup event had occured */ /* Check if any wakeup event had occurred */
if (sharpsl_pm.machinfo->charger_wakeup() != 0) if (sharpsl_pm.machinfo->charger_wakeup() != 0)
return 0; return 0;
/* Check for timeout */ /* Check for timeout */
@ -774,6 +774,8 @@ static struct pm_ops sharpsl_pm_ops = {
static int __init sharpsl_pm_probe(struct platform_device *pdev) static int __init sharpsl_pm_probe(struct platform_device *pdev)
{ {
int ret;
if (!pdev->dev.platform_data) if (!pdev->dev.platform_data)
return -EINVAL; return -EINVAL;
@ -792,8 +794,10 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev)
sharpsl_pm.machinfo->init(); sharpsl_pm.machinfo->init();
device_create_file(&pdev->dev, &dev_attr_battery_percentage); ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
device_create_file(&pdev->dev, &dev_attr_battery_voltage); ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
if (ret != 0)
dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
apm_get_power_status = sharpsl_apm_get_power_status; apm_get_power_status = sharpsl_apm_get_power_status;

2
arch/arm/kernel/asm-offsets.c
Просмотреть файл

@ -85,7 +85,7 @@ int main(void)
DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
BLANK(); BLANK();
#if __LINUX_ARM_ARCH__ >= 6 #ifdef CONFIG_CPU_HAS_ASID
DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
BLANK(); BLANK();
#endif #endif

4
arch/arm/kernel/calls.S
Просмотреть файл

@ -357,6 +357,10 @@
/* 345 */ CALL(sys_getcpu) /* 345 */ CALL(sys_getcpu)
CALL(sys_ni_syscall) /* eventually epoll_pwait */ CALL(sys_ni_syscall) /* eventually epoll_pwait */
CALL(sys_kexec_load) CALL(sys_kexec_load)
CALL(sys_utimensat)
CALL(sys_signalfd)
/* 350 */ CALL(sys_timerfd)
CALL(sys_eventfd)
#ifndef syscalls_counted #ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted #define syscalls_counted

2
arch/arm/kernel/setup.c
Просмотреть файл

@ -918,7 +918,7 @@ static int c_show(struct seq_file *m, void *v)
if ((processor_id & 0x0008f000) == 0x00000000) { if ((processor_id & 0x0008f000) == 0x00000000) {
/* pre-ARM7 */ /* pre-ARM7 */
seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4); seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
} else { } else {
if ((processor_id & 0x0008f000) == 0x00007000) { if ((processor_id & 0x0008f000) == 0x00007000) {
/* ARM7 */ /* ARM7 */

2
arch/arm/kernel/sys_arm.c
Просмотреть файл

@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
EXPORT_SYMBOL(kernel_execve); EXPORT_SYMBOL(kernel_execve);
/* /*
* Since loff_t is a 64 bit type we avoid a lot of ABI hastle * Since loff_t is a 64 bit type we avoid a lot of ABI hassle
* with a different argument ordering. * with a different argument ordering.
*/ */
asmlinkage long sys_arm_fadvise64_64(int fd, int advice, asmlinkage long sys_arm_fadvise64_64(int fd, int advice,

2
arch/arm/lib/bitops.h
Просмотреть файл

@ -47,7 +47,7 @@
* @store: store instruction * @store: store instruction
* *
* Note: we can trivially conditionalise the store instruction * Note: we can trivially conditionalise the store instruction
* to avoid dirting the data cache. * to avoid dirtying the data cache.
*/ */
.macro testop, instr, store .macro testop, instr, store
add r1, r1, r0, lsr #3 add r1, r1, r0, lsr #3

8
arch/arm/mach-at91/board-carmeva.c
Просмотреть файл

@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
.pullup_pin = AT91_PIN_PD9, .pullup_pin = AT91_PIN_PD9,
}; };
/* FIXME: user dependend */ /* FIXME: user dependant */
// static struct at91_cf_data __initdata carmeva_cf_data = { // static struct at91_cf_data __initdata carmeva_cf_data = {
// .det_pin = AT91_PIN_PB0, // .det_pin = AT91_PIN_PB0,
// .rst_pin = AT91_PIN_PC5, // .rst_pin = AT91_PIN_PC5,
@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = {
.chip_select = 0, .chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000, .max_speed_hz = 10 * 1000 * 1000,
}, },
{ /* User accessable spi - cs1 (250KHz) */ { /* User accessible spi - cs1 (250KHz) */
.modalias = "spi-cs1", .modalias = "spi-cs1",
.chip_select = 1, .chip_select = 1,
.max_speed_hz = 250 * 1000, .max_speed_hz = 250 * 1000,
}, },
{ /* User accessable spi - cs2 (1MHz) */ { /* User accessible spi - cs2 (1MHz) */
.modalias = "spi-cs2", .modalias = "spi-cs2",
.chip_select = 2, .chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000, .max_speed_hz = 1 * 1000 * 1000,
}, },
{ /* User accessable spi - cs3 (10MHz) */ { /* User accessible spi - cs3 (10MHz) */
.modalias = "spi-cs3", .modalias = "spi-cs3",
.chip_select = 3, .chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000, .max_speed_hz = 10 * 1000 * 1000,

4
arch/arm/mach-h720x/cpu-h7202.c
Просмотреть файл

@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id)
} }
/* /*
* mask multiplexed timer irq's * mask multiplexed timer IRQs
*/ */
static void inline mask_timerx_irq (u32 irq) static void inline mask_timerx_irq (u32 irq)
{ {
@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq)
} }
/* /*
* unmask multiplexed timer irq's * unmask multiplexed timer IRQs
*/ */
static void inline unmask_timerx_irq (u32 irq) static void inline unmask_timerx_irq (u32 irq)
{ {

2
arch/arm/mach-imx/cpufreq.c
Просмотреть файл

@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
if(mpctl0) { if(mpctl0) {
CSCR |= CSCR_MPLL_RESTART; CSCR |= CSCR_MPLL_RESTART;
/* Wait until MPLL is stablized */ /* Wait until MPLL is stabilized */
while( CSCR & CSCR_MPLL_RESTART ); while( CSCR & CSCR_MPLL_RESTART );
imx_set_async_mode(); imx_set_async_mode();

8
arch/arm/mach-imx/dma.c
Просмотреть файл

@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch,
* The function setups DMA channel source and destination addresses for transfer * The function setups DMA channel source and destination addresses for transfer
* specified by provided parameters. The scatter-gather emulation is disabled, * specified by provided parameters. The scatter-gather emulation is disabled,
* because linear data block * because linear data block
* form the physical address range is transfered. * form the physical address range is transferred.
* Return value: if incorrect parameters are provided -%EINVAL. * Return value: if incorrect parameters are provided -%EINVAL.
* Zero indicates success. * Zero indicates success.
*/ */
@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
* or %DMA_MODE_WRITE from memory to the device * or %DMA_MODE_WRITE from memory to the device
* *
* The function setups DMA channel state and registers to be ready for transfer * The function sets up DMA channel state and registers to be ready for transfer
* specified by provided parameters. The scatter-gather emulation is set up * specified by provided parameters. The scatter-gather emulation is set up
* according to the parameters. * according to the parameters.
* *
@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
* *
* %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
* *
* Be carefull there and do not mistakenly mix source and target device * Be careful here and do not mistakenly mix source and target device
* port sizes constants, they are really different: * port sizes constants, they are really different:
* %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
* %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
/* /*
* The cleaning of @sg field would be questionable * The cleaning of @sg field would be questionable
* there, because its value can help to compute * there, because its value can help to compute
* remaining/transfered bytes count in the handler * remaining/transferred bytes count in the handler
*/ */
/*imx_dma_channels[i].sg = NULL;*/ /*imx_dma_channels[i].sg = NULL;*/

1
arch/arm/mach-integrator/Makefile
Просмотреть файл

@ -12,4 +12,3 @@ obj-$(CONFIG_LEDS) += leds.o
obj-$(CONFIG_PCI) += pci_v3.o pci.o obj-$(CONFIG_PCI) += pci_v3.o pci.o
obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o
obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

18
arch/arm/mach-integrator/core.c
Просмотреть файл

@ -257,23 +257,7 @@ integrator_timer_interrupt(int irq, void *dev_id)
*/ */
writel(1, TIMER1_VA_BASE + TIMER_INTCLR); writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
/* timer_tick();
* the clock tick routines are only processed on the
* primary CPU
*/
if (hard_smp_processor_id() == 0) {
timer_tick();
#ifdef CONFIG_SMP
smp_send_timer();
#endif
}
#ifdef CONFIG_SMP
/*
* this is the ARM equivalent of the APIC timer interrupt
*/
update_process_times(user_mode(get_irq_regs()));
#endif /* CONFIG_SMP */
write_sequnlock(&xtime_lock); write_sequnlock(&xtime_lock);

37
arch/arm/mach-integrator/headsmp.S
Просмотреть файл

@ -1,37 +0,0 @@
/*
* linux/arch/arm/mach-integrator/headsmp.S
*
* Copyright (c) 2003 ARM Limited
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__INIT
/*
* Integrator specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(integrator_secondary_startup)
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
ldr r6, [r6, r4]
pen: ldr r7, [r6]
cmp r7, r0
bne pen
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
1: .long .
.long phys_pen_release

1
arch/arm/mach-integrator/pci_v3.c
Просмотреть файл

@ -33,6 +33,7 @@
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/mach/pci.h> #include <asm/mach/pci.h>
#include <asm/irq_regs.h>
#include <asm/hardware/pci_v3.h> #include <asm/hardware/pci_v3.h>

204
arch/arm/mach-integrator/platsmp.c
Просмотреть файл

@ -1,204 +0,0 @@
/*
* linux/arch/arm/mach-cintegrator/platsmp.c
*
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/delay.h>
#include <asm/mmu_context.h>
#include <asm/ptrace.h>
#include <asm/smp.h>
extern void integrator_secondary_startup(void);
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
unsigned long __cpuinitdata phys_pen_release = 0;
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
* the primary core may have used a "cross call" soft interrupt
* to get this processor out of WFI in the BootMonitor - make
* sure that we are no longer being sent this soft interrupt
*/
smp_cross_call_done(cpumask_of_cpu(cpu));
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
secondary_scan_irqs();
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
pen_release = cpu;
flush_cache_all();
/*
* XXX
*
* This is a later addition to the booting protocol: the
* bootMonitor now puts secondary cores into WFI, so
* poke_milo() no longer gets the cores moving; we need
* to send a soft interrupt to wake the secondary core.
* Use smp_cross_call() for this, since there's little
* point duplicating the code here
*/
smp_cross_call(cpumask_of_cpu(cpu));
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
if (pen_release == -1)
break;
udelay(10);
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
static void __init poke_milo(void)
{
extern void secondary_startup(void);
/* nobody is to be released from the pen yet */
pen_release = -1;
phys_pen_release = virt_to_phys(&pen_release);
/*
* write the address of secondary startup into the system-wide
* flags register, then clear the bottom two bits, which is what
* BootMonitor is waiting for
*/
#if 1
#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
__raw_writel(virt_to_phys(integrator_secondary_startup),
(IO_ADDRESS(INTEGRATOR_HDR_BASE) +
CINTEGRATOR_HDR_FLAGSS_OFFSET));
#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
__raw_writel(3,
(IO_ADDRESS(INTEGRATOR_HDR_BASE) +
CINTEGRATOR_HDR_FLAGSC_OFFSET));
#endif
mb();
}
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
void __init smp_init_cpus(void)
{
unsigned int i, ncores = get_core_count();
for (i = 0; i < ncores; i++)
cpu_set(i, cpu_possible_map);
}
void __init smp_prepare_cpus(unsigned int max_cpus)
{
unsigned int ncores = get_core_count();
unsigned int cpu = smp_processor_id();
int i;
/* sanity check */
if (ncores == 0) {
printk(KERN_ERR
"Integrator/CP: strange CM count of 0? Default to 1\n");
ncores = 1;
}
if (ncores > NR_CPUS) {
printk(KERN_WARNING
"Integrator/CP: no. of cores (%d) greater than configured "
"maximum of %d - clipping\n",
ncores, NR_CPUS);
ncores = NR_CPUS;
}
/*
* start with some more config for the Boot CPU, now that
* the world is a bit more alive (which was not the case
* when smp_prepare_boot_cpu() was called)
*/
smp_store_cpu_info(cpu);
/*
* are we trying to boot more cores than exist?
*/
if (max_cpus > ncores)
max_cpus = ncores;
/*
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
for (i = 0; i < max_cpus; i++)
cpu_set(i, cpu_present_map);
/*
* Do we need any more CPUs? If so, then let them know where
* to start. Note that, on modern versions of MILO, the "poke"
* doesn't actually do anything until each individual core is
* sent a soft interrupt to get it out of WFI
*/
if (max_cpus > 1)
poke_milo();
}

54
arch/arm/mach-iop13xx/irq.c
Просмотреть файл

@ -30,77 +30,65 @@
/* INTCTL0 CP6 R0 Page 4 /* INTCTL0 CP6 R0 Page 4
*/ */
static inline u32 read_intctl_0(void) static u32 read_intctl_0(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
return val; return val;
} }
static inline void write_intctl_0(u32 val) static void write_intctl_0(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
} }
/* INTCTL1 CP6 R1 Page 4 /* INTCTL1 CP6 R1 Page 4
*/ */
static inline u32 read_intctl_1(void) static u32 read_intctl_1(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
return val; return val;
} }
static inline void write_intctl_1(u32 val) static void write_intctl_1(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
} }
/* INTCTL2 CP6 R2 Page 4 /* INTCTL2 CP6 R2 Page 4
*/ */
static inline u32 read_intctl_2(void) static u32 read_intctl_2(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
return val; return val;
} }
static inline void write_intctl_2(u32 val) static void write_intctl_2(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
} }
/* INTCTL3 CP6 R3 Page 4 /* INTCTL3 CP6 R3 Page 4
*/ */
static inline u32 read_intctl_3(void) static u32 read_intctl_3(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
return val; return val;
} }
static inline void write_intctl_3(u32 val) static void write_intctl_3(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
} }
/* INTSTR0 CP6 R0 Page 5 /* INTSTR0 CP6 R0 Page 5
*/ */
static inline u32 read_intstr_0(void) static void write_intstr_0(u32 val)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
return val;
}
static inline void write_intstr_0(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
} }
/* INTSTR1 CP6 R1 Page 5 /* INTSTR1 CP6 R1 Page 5
*/ */
static inline u32 read_intstr_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
return val;
}
static void write_intstr_1(u32 val) static void write_intstr_1(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@ -108,12 +96,6 @@ static void write_intstr_1(u32 val)
/* INTSTR2 CP6 R2 Page 5 /* INTSTR2 CP6 R2 Page 5
*/ */
static inline u32 read_intstr_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
return val;
}
static void write_intstr_2(u32 val) static void write_intstr_2(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@ -121,12 +103,6 @@ static void write_intstr_2(u32 val)
/* INTSTR3 CP6 R3 Page 5 /* INTSTR3 CP6 R3 Page 5
*/ */
static inline u32 read_intstr_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
return val;
}
static void write_intstr_3(u32 val) static void write_intstr_3(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@ -134,12 +110,6 @@ static void write_intstr_3(u32 val)
/* INTBASE CP6 R0 Page 2 /* INTBASE CP6 R0 Page 2
*/ */
static inline u32 read_intbase(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
return val;
}
static void write_intbase(u32 val) static void write_intbase(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@ -147,12 +117,6 @@ static void write_intbase(u32 val)
/* INTSIZE CP6 R2 Page 2 /* INTSIZE CP6 R2 Page 2
*/ */
static inline u32 read_intsize(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
return val;
}
static void write_intsize(u32 val) static void write_intsize(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));

18
arch/arm/mach-iop13xx/msi.c
Просмотреть файл

@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
/* IMIPR0 CP6 R8 Page 1 /* IMIPR0 CP6 R8 Page 1
*/ */
static inline u32 read_imipr_0(void) static u32 read_imipr_0(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
return val; return val;
} }
static inline void write_imipr_0(u32 val) static void write_imipr_0(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
} }
/* IMIPR1 CP6 R9 Page 1 /* IMIPR1 CP6 R9 Page 1
*/ */
static inline u32 read_imipr_1(void) static u32 read_imipr_1(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
return val; return val;
} }
static inline void write_imipr_1(u32 val) static void write_imipr_1(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
} }
/* IMIPR2 CP6 R10 Page 1 /* IMIPR2 CP6 R10 Page 1
*/ */
static inline u32 read_imipr_2(void) static u32 read_imipr_2(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
return val; return val;
} }
static inline void write_imipr_2(u32 val) static void write_imipr_2(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
} }
/* IMIPR3 CP6 R11 Page 1 /* IMIPR3 CP6 R11 Page 1
*/ */
static inline u32 read_imipr_3(void) static u32 read_imipr_3(void)
{ {
u32 val; u32 val;
asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
return val; return val;
} }
static inline void write_imipr_3(u32 val) static void write_imipr_3(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
} }
@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
write_msi_msg(irq, &msg); write_msi_msg(irq, &msg);
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
return irq; return 0;
} }

10
arch/arm/mach-iop13xx/pci.c
Просмотреть файл

@ -145,7 +145,7 @@ void iop13xx_map_pci_memory(void)
} }
} }
static inline int iop13xx_atu_function(int atu) static int iop13xx_atu_function(int atu)
{ {
int func = 0; int func = 0;
/* the function number depends on the value of the /* the function number depends on the value of the
@ -260,7 +260,7 @@ static int iop13xx_atux_pci_status(int clear)
* data. Note that the data dependency on %0 encourages an abort * data. Note that the data dependency on %0 encourages an abort
* to be detected before we return. * to be detected before we return.
*/ */
static inline u32 iop13xx_atux_read(unsigned long addr) static u32 iop13xx_atux_read(unsigned long addr)
{ {
u32 val; u32 val;
@ -388,7 +388,7 @@ static int iop13xx_atue_pci_status(int clear)
return err; return err;
} }
static inline int __init static int
iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{ {
WARN_ON(idsel != 0); WARN_ON(idsel != 0);
@ -402,7 +402,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
} }
} }
static inline u32 iop13xx_atue_read(unsigned long addr) static u32 iop13xx_atue_read(unsigned long addr)
{ {
u32 val; u32 val;
@ -990,7 +990,7 @@ void __init iop13xx_pci_init(void)
"imprecise external abort"); "imprecise external abort");
} }
/* intialize the pci memory space. handle any combination of /* initialize the pci memory space. handle any combination of
* atue and atux enabled/disabled * atue and atux enabled/disabled
*/ */
int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)

2
arch/arm/mach-iop32x/glantank.c
Просмотреть файл

@ -75,7 +75,7 @@ void __init glantank_map_io(void)
#define INTC IRQ_IOP32X_XINT2 #define INTC IRQ_IOP32X_XINT2
#define INTD IRQ_IOP32X_XINT3 #define INTD IRQ_IOP32X_XINT3
static inline int __init static int __init
glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
static int pci_irq_table[][4] = { static int pci_irq_table[][4] = {

4
arch/arm/mach-iop32x/iq31244.c
Просмотреть файл

@ -104,7 +104,7 @@ void __init iq31244_map_io(void)
/* /*
* EP80219/IQ31244 PCI. * EP80219/IQ31244 PCI.
*/ */
static inline int __init static int __init
ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;
@ -140,7 +140,7 @@ static struct hw_pci ep80219_pci __initdata = {
.map_irq = ep80219_pci_map_irq, .map_irq = ep80219_pci_map_irq,
}; };
static inline int __init static int __init
iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;

2
arch/arm/mach-iop32x/iq80321.c
Просмотреть файл

@ -72,7 +72,7 @@ void __init iq80321_map_io(void)
/* /*
* IQ80321 PCI. * IQ80321 PCI.
*/ */
static inline int __init static int __init
iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;

4
arch/arm/mach-iop32x/irq.c
Просмотреть файл

@ -21,12 +21,12 @@
static u32 iop32x_mask; static u32 iop32x_mask;
static inline void intctl_write(u32 val) static void intctl_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
} }
static inline void intstr_write(u32 val) static void intstr_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
} }

2
arch/arm/mach-iop32x/n2100.c
Просмотреть файл

@ -76,7 +76,7 @@ void __init n2100_map_io(void)
/* /*
* N2100 PCI. * N2100 PCI.
*/ */
static inline int __init static int __init
n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;

2
arch/arm/mach-iop33x/iq80331.c
Просмотреть файл

@ -55,7 +55,7 @@ static struct sys_timer iq80331_timer = {
/* /*
* IQ80331 PCI. * IQ80331 PCI.
*/ */
static inline int __init static int __init
iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;

2
arch/arm/mach-iop33x/iq80332.c
Просмотреть файл

@ -55,7 +55,7 @@ static struct sys_timer iq80332_timer = {
/* /*
* IQ80332 PCI. * IQ80332 PCI.
*/ */
static inline int __init static int __init
iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;

12
arch/arm/mach-iop33x/irq.c
Просмотреть файл

@ -22,32 +22,32 @@
static u32 iop33x_mask0; static u32 iop33x_mask0;
static u32 iop33x_mask1; static u32 iop33x_mask1;
static inline void intctl0_write(u32 val) static void intctl0_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
} }
static inline void intctl1_write(u32 val) static void intctl1_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
} }
static inline void intstr0_write(u32 val) static void intstr0_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
} }
static inline void intstr1_write(u32 val) static void intstr1_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
} }
static inline void intbase_write(u32 val) static void intbase_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
} }
static inline void intsize_write(u32 val) static void intsize_write(u32 val)
{ {
asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
} }

2
arch/arm/mach-ixp2000/enp2611.c
Просмотреть файл

@ -198,7 +198,7 @@ subsys_initcall(enp2611_pci_init);
/************************************************************************* /*************************************************************************
* ENP-2611 Machine Intialization * ENP-2611 Machine Initialization
*************************************************************************/ *************************************************************************/
static struct flash_platform_data enp2611_flash_platform_data = { static struct flash_platform_data enp2611_flash_platform_data = {
.map_name = "cfi_probe", .map_name = "cfi_probe",

4
arch/arm/mach-ixp2000/ixdp2x00.c
Просмотреть файл

@ -195,7 +195,7 @@ void __init ixdp2x00_map_io(void)
* instances of the kernel. So far so good. Peers on the PCI bus running * instances of the kernel. So far so good. Peers on the PCI bus running
* Linux is a common design in telecom systems. The problem is that instead * Linux is a common design in telecom systems. The problem is that instead
* of all the devices being controlled by a single host, different * of all the devices being controlled by a single host, different
* devices are controlles by different NPUs on the same bus, leading to * devices are controlled by different NPUs on the same bus, leading to
* multiple hosts on the bus. The exact bus layout looks like: * multiple hosts on the bus. The exact bus layout looks like:
* *
* Bus 0 * Bus 0
@ -211,7 +211,7 @@ void __init ixdp2x00_map_io(void)
* | | | | | * | | | | |
* ... Dev PMC Media Eth0 Eth1 ... * ... Dev PMC Media Eth0 Eth1 ...
* *
* The master controlls all but Eth1, which is controlled by the * The master controls all but Eth1, which is controlled by the
* slave. What this means is that the both the master and the slave * slave. What this means is that the both the master and the slave
* have to scan the bus, but only one of them can enumerate the bus. * have to scan the bus, but only one of them can enumerate the bus.
* In addition, after the bus is scanned, each kernel must remove * In addition, after the bus is scanned, each kernel must remove

6
arch/arm/mach-ixp2000/ixdp2x01.c
Просмотреть файл

@ -276,7 +276,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/* Device is located after first MB bridge */ /* Device is located after first MB bridge */
case 0x0008: case 0x0008:
if (tmp_bus == dev->bus) { if (tmp_bus == dev->bus) {
/* Device is located directy after first MB bridge */ /* Device is located directly after first MB bridge */
switch (devpin) { switch (devpin) {
case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
if (machine_is_ixdp2401()) if (machine_is_ixdp2401())
@ -299,7 +299,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
break; break;
case 0x0010: case 0x0010:
if (tmp_bus == dev->bus) { if (tmp_bus == dev->bus) {
/* Device is located directy after second MB bridge */ /* Device is located directly after second MB bridge */
/* Secondary bus of second bridge */ /* Secondary bus of second bridge */
switch (devpin) { switch (devpin) {
case DEVPIN(0, 1): /* DB#0 */ case DEVPIN(0, 1): /* DB#0 */
@ -348,7 +348,7 @@ int __init ixdp2x01_pci_init(void)
subsys_initcall(ixdp2x01_pci_init); subsys_initcall(ixdp2x01_pci_init);
/************************************************************************* /*************************************************************************
* IXDP2x01 Machine Intialization * IXDP2x01 Machine Initialization
*************************************************************************/ *************************************************************************/
static struct flash_platform_data ixdp2x01_flash_platform_data = { static struct flash_platform_data ixdp2x01_flash_platform_data = {
.map_name = "cfi_probe", .map_name = "cfi_probe",

2
arch/arm/mach-ixp2000/pci.c
Просмотреть файл

@ -102,7 +102,7 @@ int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
} }
/* /*
* We don't do error checks by callling clear_master_aborts() b/c the * We don't do error checks by calling clear_master_aborts() b/c the
* assumption is that the caller did a read first to make sure a device * assumption is that the caller did a read first to make sure a device
* exists. * exists.
*/ */

2
arch/arm/mach-ixp23xx/core.c
Просмотреть файл

@ -389,7 +389,7 @@ struct sys_timer ixp23xx_timer = {
/************************************************************************* /*************************************************************************
* IXP23xx Platform Initializaion * IXP23xx Platform Initialization
*************************************************************************/ *************************************************************************/
static struct resource ixp23xx_uart_resources[] = { static struct resource ixp23xx_uart_resources[] = {
{ {

2
arch/arm/mach-ixp4xx/gtwx5715-setup.c
Просмотреть файл

@ -1,7 +1,7 @@
/* /*
* arch/arm/mach-ixp4xx/gtwx5715-setup.c * arch/arm/mach-ixp4xx/gtwx5715-setup.c
* *
* Gemtek GTWX5715 (Linksys WRV54G) board settup * Gemtek GTWX5715 (Linksys WRV54G) board setup
* *
* Copyright (C) 2004 George T. Joseph * Copyright (C) 2004 George T. Joseph
* Derived from Coyote * Derived from Coyote

6
arch/arm/mach-lh7a40x/lcd-panel.h
Просмотреть файл

@ -126,7 +126,7 @@ static struct clcd_panel_extra lcd_panel_extra = {
*/ */
/* The full horozontal cycle (Th) is clock/360/400/450. */ /* The full horizontal cycle (Th) is clock/360/400/450. */
/* The full vertical cycle (Tv) is line/251/262/280. */ /* The full vertical cycle (Tv) is line/251/262/280. */
#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ #define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
@ -162,7 +162,7 @@ static struct clcd_panel lcd_panel = {
/* Logic Product Development LCD 6.4" VGA -10 */ /* Logic Product Development LCD 6.4" VGA -10 */
/* Sharp PN LQ64D343 */ /* Sharp PN LQ64D343 */
/* The full horozontal cycle (Th) is clock/750/800/900. */ /* The full horizontal cycle (Th) is clock/750/800/900. */
/* The full vertical cycle (Tv) is line/515/525/560. */ /* The full vertical cycle (Tv) is line/515/525/560. */
#define PIX_CLOCK_TARGET (28330000) #define PIX_CLOCK_TARGET (28330000)
@ -243,7 +243,7 @@ static struct clcd_panel lcd_panel = {
* (fdisk, e2fsck). And, at that speed the display may have a visible * (fdisk, e2fsck). And, at that speed the display may have a visible
* flicker. */ * flicker. */
/* The full horozontal cycle (Th) is clock/832/1056/1395. */ /* The full horizontal cycle (Th) is clock/832/1056/1395. */
#define PIX_CLOCK_TARGET (20000000) #define PIX_CLOCK_TARGET (20000000)
#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)

2
arch/arm/mach-ns9xxx/time.c
Просмотреть файл

@ -35,7 +35,7 @@ static unsigned long ns9xxx_timer_gettimeoffset(void)
{ {
/* return the microseconds which have passed since the last interrupt /* return the microseconds which have passed since the last interrupt
* was _serviced_. That is, if an interrupt is pending or the counter * was _serviced_. That is, if an interrupt is pending or the counter
* reloads, return one periode more. */ * reloads, return one period more. */
u32 counter1 = SYS_TR(0); u32 counter1 = SYS_TR(0);
int pending = SYS_ISR & (1 << IRQ_TIMER0); int pending = SYS_ISR & (1 << IRQ_TIMER0);

2
arch/arm/mach-omap1/Kconfig
Просмотреть файл

@ -38,7 +38,7 @@ config MACH_OMAP_H2
config MACH_OMAP_H3 config MACH_OMAP_H3
bool "TI H3 Support" bool "TI H3 Support"
depends on ARCH_OMAP1 && ARCH_OMAP16XX depends on ARCH_OMAP1 && ARCH_OMAP16XX
select GPIOEXPANDER_OMAP # select GPIOEXPANDER_OMAP
help help
TI OMAP 1710 H3 board support. Say Y here if you have such TI OMAP 1710 H3 board support. Say Y here if you have such
a board. a board.

2
arch/arm/mach-omap1/board-osk.c
Просмотреть файл

@ -385,7 +385,7 @@ static void __init osk_init(void)
/* Workaround for wrong CS3 (NOR flash) timing /* Workaround for wrong CS3 (NOR flash) timing
* There are some U-Boot versions out there which configure * There are some U-Boot versions out there which configure
* wrong CS3 memory timings. This mainly leads to CRC * wrong CS3 memory timings. This mainly leads to CRC
* or similiar errors if you use NOR flash (e.g. with JFFS2) * or similar errors if you use NOR flash (e.g. with JFFS2)
*/ */
if (EMIFS_CCS(3) != EMIFS_CS3_VAL) if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
EMIFS_CCS(3) = EMIFS_CS3_VAL; EMIFS_CCS(3) = EMIFS_CS3_VAL;

2
arch/arm/mach-omap1/board-palmte.c
Просмотреть файл

@ -7,7 +7,7 @@
* *
* Original version : Laurent Gonzalez * Original version : Laurent Gonzalez
* *
* Maintainters : http://palmtelinux.sf.net * Maintainers : http://palmtelinux.sf.net
* palmtelinux-developpers@lists.sf.net * palmtelinux-developpers@lists.sf.net
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify

2
arch/arm/mach-omap1/pm.c
Просмотреть файл

@ -438,7 +438,7 @@ void omap_pm_suspend(void)
omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
/* /*
* Reenable interrupts * Re-enable interrupts
*/ */
local_irq_enable(); local_irq_enable();

2
arch/arm/mach-omap2/clock.c
Просмотреть файл

@ -443,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
/* /*
* Check the DLL lock state, and return tue if running in unlock mode. * Check the DLL lock state, and return tue if running in unlock mode.
* This is needed to compenste for the shifted DLL value in unlock mode. * This is needed to compensate for the shifted DLL value in unlock mode.
*/ */
static u32 omap2_dll_force_needed(void) static u32 omap2_dll_force_needed(void)
{ {

4
arch/arm/mach-omap2/clock.h
Просмотреть файл

@ -338,7 +338,7 @@ struct prcm_config {
/* /*
* These represent optimal values for common parts, it won't work for all. * These represent optimal values for common parts, it won't work for all.
* As long as you scale down, most parameters are still work, they just * As long as you scale down, most parameters are still work, they just
* become sub-optimal. The RFR value goes in the oppisite direction. If you * become sub-optimal. The RFR value goes in the opposite direction. If you
* don't adjust it down as your clock period increases the refresh interval * don't adjust it down as your clock period increases the refresh interval
* will not be met. Setting all parameters for complete worst case may work, * will not be met. Setting all parameters for complete worst case may work,
* but may cut memory performance by 2x. Due to errata the DLLs need to be * but may cut memory performance by 2x. Due to errata the DLLs need to be
@ -384,7 +384,7 @@ struct prcm_config {
* Filling in table based on H4 boards and 2430-SDPs variants available. * Filling in table based on H4 boards and 2430-SDPs variants available.
* There are quite a few more rates combinations which could be defined. * There are quite a few more rates combinations which could be defined.
* *
* When multiple values are defiend the start up will try and choose the * When multiple values are defined the start up will try and choose the
* fastest one. If a 'fast' value is defined, then automatically, the /2 * fastest one. If a 'fast' value is defined, then automatically, the /2
* one should be included as it can be used. Generally having more that * one should be included as it can be used. Generally having more that
* one fast set does not make sense, as static timings need to be changed * one fast set does not make sense, as static timings need to be changed

10
arch/arm/mach-pxa/corgi_lcd.c
Просмотреть файл

@ -40,7 +40,7 @@
#define PICTRL_ADRS 0x06 #define PICTRL_ADRS 0x06
#define POLCTRL_ADRS 0x07 #define POLCTRL_ADRS 0x07
/* Resgister Bit Definitions */ /* Register Bit Definitions */
#define RESCTL_QVGA 0x01 #define RESCTL_QVGA 0x01
#define RESCTL_VGA 0x00 #define RESCTL_VGA 0x00
@ -55,11 +55,11 @@
#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ #define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ #define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ #define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ #define POWER0_COM_ON 0x08 /* COM Power Supply ON */
#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ #define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ #define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ #define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ #define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
#define PICTRL_INIT_STATE 0x01 #define PICTRL_INIT_STATE 0x01
@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data)
lcdtg_i2c_send_stop(base_data); lcdtg_i2c_send_stop(base_data);
} }
/* Set Phase Adjuct */ /* Set Phase Adjust */
static void lcdtg_set_phadadj(int mode) static void lcdtg_set_phadadj(int mode)
{ {
int adj; int adj;
@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode)
/* Signals output enable */ /* Signals output enable */
corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
/* Set Phase Adjuct */ /* Set Phase Adjust */
lcdtg_set_phadadj(mode); lcdtg_set_phadadj(mode);
/* Initialize for Input Signals from ATI */ /* Initialize for Input Signals from ATI */

2
arch/arm/mach-pxa/corgi_ssp.c
Просмотреть файл

@ -32,7 +32,7 @@ static struct corgissp_machinfo *ssp_machinfo;
* There are three devices connected to the SSP interface: * There are three devices connected to the SSP interface:
* 1. A touchscreen controller (TI ADS7846 compatible) * 1. A touchscreen controller (TI ADS7846 compatible)
* 2. An LCD contoller (with some Backlight functionality) * 2. An LCD contoller (with some Backlight functionality)
* 3. A battery moinitoring IC (Maxim MAX1111) * 3. A battery monitoring IC (Maxim MAX1111)
* *
* Each device uses a different speed/mode of communication. * Each device uses a different speed/mode of communication.
* *

2
arch/arm/mach-realview/localtimer.c
Просмотреть файл

@ -30,7 +30,7 @@ static unsigned long mpcore_timer_rate;
/* /*
* local_timer_ack: checks for a local timer interrupt. * local_timer_ack: checks for a local timer interrupt.
* *
* If a local timer interrupt has occured, acknowledge and return 1. * If a local timer interrupt has occurred, acknowledge and return 1.
* Otherwise, return 0. * Otherwise, return 0.
*/ */
int local_timer_ack(void) int local_timer_ack(void)

1
arch/arm/mach-s3c2410/mach-h1940.c
Просмотреть файл

@ -17,6 +17,7 @@
#include <linux/list.h> #include <linux/list.h>
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h> #include <linux/serial_core.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>

1
arch/arm/mach-s3c2410/mach-qt2410.c
Просмотреть файл

@ -27,6 +27,7 @@
#include <linux/list.h> #include <linux/list.h>
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/serial_core.h> #include <linux/serial_core.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>

4
arch/arm/mach-s3c2412/dma.c
Просмотреть файл

@ -59,8 +59,8 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
[DMACH_SPI1] = { [DMACH_SPI1] = {
.name = "spi1", .name = "spi1",
.channels = MAP(S3C2412_DMAREQSEL_SPI1TX), .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
}, },
[DMACH_UART0] = { [DMACH_UART0] = {
.name = "uart0", .name = "uart0",

9
arch/arm/mach-s3c2412/s3c2412.c
Просмотреть файл

@ -37,6 +37,7 @@
#include <asm/arch/regs-gpio.h> #include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-gpioj.h> #include <asm/arch/regs-gpioj.h>
#include <asm/arch/regs-dsc.h> #include <asm/arch/regs-dsc.h>
#include <asm/arch/regs-spi.h>
#include <asm/plat-s3c24xx/s3c2412.h> #include <asm/plat-s3c24xx/s3c2412.h>
#include <asm/plat-s3c24xx/cpu.h> #include <asm/plat-s3c24xx/cpu.h>
@ -74,6 +75,14 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
s3c_device_sdi.name = "s3c2412-sdi"; s3c_device_sdi.name = "s3c2412-sdi";
s3c_device_lcd.name = "s3c2412-lcd"; s3c_device_lcd.name = "s3c2412-lcd";
s3c_device_nand.name = "s3c2412-nand"; s3c_device_nand.name = "s3c2412-nand";
/* spi channel related changes, s3c2412/13 specific */
s3c_device_spi0.name = "s3c2412-spi";
s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
s3c_device_spi1.name = "s3c2412-spi";
s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
} }
/* s3c2412_idle /* s3c2412_idle

2
arch/arm/mach-s3c2440/mach-osiris.c
Просмотреть файл

@ -45,7 +45,7 @@
#include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h> #include <asm/plat-s3c24xx/cpu.h>
/* onboard perihpheral map */ /* onboard perihperal map */
static struct map_desc osiris_iodesc[] __initdata = { static struct map_desc osiris_iodesc[] __initdata = {
/* ISA IO areas (may be over-written later) */ /* ISA IO areas (may be over-written later) */

1
arch/arm/mach-s3c2440/mach-rx3715.c
Просмотреть файл

@ -19,6 +19,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/tty.h> #include <linux/tty.h>
#include <linux/console.h> #include <linux/console.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/serial_core.h> #include <linux/serial_core.h>
#include <linux/serial.h> #include <linux/serial.h>

22
arch/arm/mach-s3c2443/clock.c
Просмотреть файл

@ -746,6 +746,25 @@ static struct clk init_clocks[] = {
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD, .ctrlbit = S3C2443_HCLKCON_USBD,
}, {
.name = "hsmmc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "cfc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "ssmc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, { }, {
.name = "timers", .name = "timers",
.id = -1, .id = -1,
@ -791,7 +810,8 @@ static struct clk init_clocks[] = {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1, .id = -1,
.parent = &clk_usb_bus_host, .parent = &clk_usb_bus_host,
}, { .name = "ac97", }, {
.name = "ac97",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97, .ctrlbit = S3C2443_PCLKCON_AC97,

1
arch/arm/mach-s3c2443/mach-smdk2443.c
Просмотреть файл

@ -104,6 +104,7 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
static struct platform_device *smdk2443_devices[] __initdata = { static struct platform_device *smdk2443_devices[] __initdata = {
&s3c_device_wdt, &s3c_device_wdt,
&s3c_device_i2c, &s3c_device_i2c,
&s3c_device_hsmmc,
}; };
static void __init smdk2443_map_io(void) static void __init smdk2443_map_io(void)

4
arch/arm/mach-s3c2443/s3c2443.c
Просмотреть файл

@ -63,6 +63,10 @@ int __init s3c2443_init(void)
s3c_device_nand.name = "s3c2412-nand"; s3c_device_nand.name = "s3c2412-nand";
/* change WDT IRQ number */
s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
return sysdev_register(&s3c2443_sysdev); return sysdev_register(&s3c2443_sysdev);
} }

2
arch/arm/mach-sa1100/time.c
Просмотреть файл

@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void)
{ {
/* /*
* According to the manual we should be able to let RTTR be zero * According to the manual we should be able to let RTTR be zero
* and then a default diviser for a 32.768KHz clock is used. * and then a default divisor for a 32.768KHz clock is used.
* Apparently this doesn't work, at least for my SA1110 rev 5. * Apparently this doesn't work, at least for my SA1110 rev 5.
* If the clock divider is uninitialized then reset it to the * If the clock divider is uninitialized then reset it to the
* default value to get the 1Hz clock. * default value to get the 1Hz clock.

8
arch/arm/mm/Kconfig
Просмотреть файл

@ -351,6 +351,7 @@ config CPU_V6
select CPU_CACHE_V6 select CPU_CACHE_V6
select CPU_CACHE_VIPT select CPU_CACHE_VIPT
select CPU_CP15_MMU select CPU_CP15_MMU
select CPU_HAS_ASID
select CPU_COPY_V6 if MMU select CPU_COPY_V6 if MMU
select CPU_TLB_V6 if MMU select CPU_TLB_V6 if MMU
@ -376,6 +377,7 @@ config CPU_V7
select CPU_CACHE_V7 select CPU_CACHE_V7
select CPU_CACHE_VIPT select CPU_CACHE_VIPT
select CPU_CP15_MMU select CPU_CP15_MMU
select CPU_HAS_ASID
select CPU_COPY_V6 if MMU select CPU_COPY_V6 if MMU
select CPU_TLB_V6 if MMU select CPU_TLB_V6 if MMU
@ -498,6 +500,12 @@ config CPU_TLB_V6
endif endif
config CPU_HAS_ASID
bool
help
This indicates whether the CPU has the ASID register; used to
tag TLB and possibly cache entries.
config CPU_CP15 config CPU_CP15
bool bool
help help

2
arch/arm/mm/alignment.c
Просмотреть файл

@ -3,7 +3,7 @@
* *
* Copyright (C) 1995 Linus Torvalds * Copyright (C) 1995 Linus Torvalds
* Modifications for ARM processor (c) 1995-2001 Russell King * Modifications for ARM processor (c) 1995-2001 Russell King
* Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc. * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
* - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
* Copyright (C) 1996, Cygnus Software Technologies Ltd. * Copyright (C) 1996, Cygnus Software Technologies Ltd.
* *

2
arch/arm/mm/ioremap.c
Просмотреть файл

@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr)
#ifndef CONFIG_SMP #ifndef CONFIG_SMP
/* /*
* If this is a section based mapping we need to handle it * If this is a section based mapping we need to handle it
* specially as the VM subysystem does not know how to handle * specially as the VM subsystem does not know how to handle
* such a beast. We need the lock here b/c we need to clear * such a beast. We need the lock here b/c we need to clear
* all the mappings before the area can be reclaimed * all the mappings before the area can be reclaimed
* by someone else. * by someone else.

2
arch/arm/mm/mmu.c
Просмотреть файл

@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = {
}; };
/* /*
* These are useful for identifing cache coherency * These are useful for identifying cache coherency
* problems by allowing the cache or the cache and * problems by allowing the cache or the cache and
* writebuffer to be turned off. (Note: the write * writebuffer to be turned off. (Note: the write
* buffer should not be on and the cache off). * buffer should not be on and the cache off).

6
arch/arm/plat-iop/pci.c
Просмотреть файл

@ -86,10 +86,10 @@ static int iop3xx_pci_status(void)
/* /*
* Simply write the address register and read the configuration * Simply write the address register and read the configuration
* data. Note that the 4 nop's ensure that we are able to handle * data. Note that the 4 nops ensure that we are able to handle
* a delayed abort (in theory.) * a delayed abort (in theory.)
*/ */
static inline u32 iop3xx_read(unsigned long addr) static u32 iop3xx_read(unsigned long addr)
{ {
u32 val; u32 val;
@ -322,7 +322,7 @@ void __init iop3xx_atu_disable(void)
/* Flag to determine whether the ATU is initialized and the PCI bus scanned */ /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
int init_atu; int init_atu;
void iop3xx_pci_preinit(void) void __init iop3xx_pci_preinit(void)
{ {
if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
iop3xx_atu_disable(); iop3xx_atu_disable();

2
arch/arm/plat-omap/common.c
Просмотреть файл

@ -73,7 +73,7 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
} }
if (info != NULL) { if (info != NULL) {
/* Check the length as a lame attempt to check for /* Check the length as a lame attempt to check for
* binary inconsistancy. */ * binary inconsistency. */
if (len != NO_LENGTH_CHECK) { if (len != NO_LENGTH_CHECK) {
/* Word-align len */ /* Word-align len */
if (len & 0x03) if (len & 0x03)

2
arch/arm/plat-omap/dma.c
Просмотреть файл

@ -1172,7 +1172,7 @@ static void set_b1_regs(void)
break; break;
default: default:
BUG(); BUG();
return; /* Supress warning about uninitialized vars */ return; /* Suppress warning about uninitialized vars */
} }
if (omap_dma_in_1510_mode()) { if (omap_dma_in_1510_mode()) {

6
arch/arm/plat-omap/sram.c
Просмотреть файл

@ -59,8 +59,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
/* /*
* Depending on the target RAMFS firewall setup, the public usable amount of * Depending on the target RAMFS firewall setup, the public usable amount of
* SRAM varies. The default accessable size for all device types is 2k. A GP * SRAM varies. The default accessible size for all device types is 2k. A GP
* device allows ARM11 but not other initators for full size. This * device allows ARM11 but not other initiators for full size. This
* functionality seems ok until some nice security API happens. * functionality seems ok until some nice security API happens.
*/ */
static int is_sram_locked(void) static int is_sram_locked(void)
@ -71,7 +71,7 @@ static int is_sram_locked(void)
type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
if (type == GP_DEVICE) { if (type == GP_DEVICE) {
/* RAMFW: R/W access to all initators for all qualifier sets */ /* RAMFW: R/W access to all initiators for all qualifier sets */
if (cpu_is_omap242x()) { if (cpu_is_omap242x()) {
__raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */

2
arch/arm/plat-omap/usb.c
Просмотреть файл

@ -177,7 +177,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
/* NOTE: SPEED and SUSP aren't configured here. OTG hosts /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
* may be able to use I2C requests to set those bits along * may be able to use I2C requests to set those bits along
* with VBUS switching and overcurrent detction. * with VBUS switching and overcurrent detection.
*/ */
if (cpu_class_is_omap1() && nwires != 6) if (cpu_class_is_omap1() && nwires != 6)

5
arch/arm/plat-s3c24xx/common-smdk.c
Просмотреть файл

@ -18,6 +18,7 @@
#include <linux/list.h> #include <linux/list.h>
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
@ -29,6 +30,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
@ -192,6 +194,9 @@ void __init smdk_machine_init(void)
s3c2410_gpio_setpin(S3C2410_GPF6, 1); s3c2410_gpio_setpin(S3C2410_GPF6, 1);
s3c2410_gpio_setpin(S3C2410_GPF7, 1); s3c2410_gpio_setpin(S3C2410_GPF7, 1);
if (machine_is_smdk2443())
smdk_nand_info.twrph0 = 50;
s3c_device_nand.dev.platform_data = &smdk_nand_info; s3c_device_nand.dev.platform_data = &smdk_nand_info;
platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));

35
arch/arm/plat-s3c24xx/devs.c
Просмотреть файл

@ -33,6 +33,7 @@
#include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h> #include <asm/plat-s3c24xx/cpu.h>
#include <asm/arch/regs-spi.h>
/* Serial port registrations */ /* Serial port registrations */
@ -402,6 +403,36 @@ struct platform_device s3c_device_sdi = {
EXPORT_SYMBOL(s3c_device_sdi); EXPORT_SYMBOL(s3c_device_sdi);
/* High-speed MMC/SD */
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C2443_PA_HSMMC,
.end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3C2443_HSMMC,
.end = IRQ_S3C2443_HSMMC,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct platform_device s3c_device_hsmmc = {
.name = "s3c-sdhci",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
/* SPI (0) */ /* SPI (0) */
static struct resource s3c_spi0_resource[] = { static struct resource s3c_spi0_resource[] = {
@ -437,8 +468,8 @@ EXPORT_SYMBOL(s3c_device_spi0);
static struct resource s3c_spi1_resource[] = { static struct resource s3c_spi1_resource[] = {
[0] = { [0] = {
.start = S3C24XX_PA_SPI + 0x20, .start = S3C24XX_PA_SPI + S3C2410_SPI1,
.end = S3C24XX_PA_SPI + 0x20 + 0x1f, .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {

2
arch/arm/plat-s3c24xx/dma.c
Просмотреть файл

@ -1153,7 +1153,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
* *
* hwcfg: the value for xxxSTCn register, * hwcfg: the value for xxxSTCn register,
* bit 0: 0=increment pointer, 1=leave pointer * bit 0: 0=increment pointer, 1=leave pointer
* bit 1: 0=soucre is AHB, 1=soucre is APB * bit 1: 0=source is AHB, 1=source is APB
* *
* devaddr: physical address of the source * devaddr: physical address of the source
*/ */

1
arch/arm/plat-s3c24xx/pm-simtec.c
Просмотреть файл

@ -18,6 +18,7 @@
#include <linux/list.h> #include <linux/list.h>
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/device.h> #include <linux/device.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>

2
arch/arm/plat-s3c24xx/pm.c
Просмотреть файл

@ -555,7 +555,7 @@ static int s3c2410_pm_enter(suspend_state_t state)
__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
/* call cpu specific preperation */ /* call cpu specific preparation */
pm_cpu_prep(); pm_cpu_prep();

4
drivers/serial/serial_ks8695.c
Просмотреть файл

@ -301,11 +301,11 @@ static int ks8695uart_startup(struct uart_port *port)
retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port); retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port);
if (retval) if (retval)
return err_ls; goto err_ls;
retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port); retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port);
if (retval) if (retval)
return err_ms; goto err_ms;
return 0; return 0;

2
include/asm-arm/arch-at91/at91_adc.h
Просмотреть файл

@ -55,7 +55,7 @@
#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */ #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
#define AT91_ADC_DATA (0x3ff) #define AT91_ADC_DATA (0x3ff)
#endif #endif

18
include/asm-arm/arch-integrator/smp.h
Просмотреть файл

@ -1,18 +0,0 @@
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware.h>
#include <asm/io.h>
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
extern void secondary_scan_irqs(void);
#endif

2
include/asm-arm/arch-s3c2410/irqs.h
Просмотреть файл

@ -124,7 +124,7 @@
#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */ #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)

2
include/asm-arm/arch-s3c2410/regs-spi.h
Просмотреть файл

@ -12,6 +12,8 @@
#ifndef __ASM_ARCH_REGS_SPI_H #ifndef __ASM_ARCH_REGS_SPI_H
#define __ASM_ARCH_REGS_SPI_H #define __ASM_ARCH_REGS_SPI_H
#define S3C2410_SPI1 (0x20)
#define S3C2412_SPI1 (0x100)
#define S3C2410_SPCON (0x00) #define S3C2410_SPCON (0x00)

2
include/asm-arm/io.h
Просмотреть файл

@ -259,9 +259,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
#define BIOVEC_MERGEABLE(vec1, vec2) \ #define BIOVEC_MERGEABLE(vec1, vec2) \
((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
#ifdef CONFIG_MMU
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(unsigned long addr, size_t size); extern int valid_phys_addr_range(unsigned long addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
#endif
/* /*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem * Convert a physical pointer to a virtual kernel pointer for /dev/mem

4
include/asm-arm/mmu.h
Просмотреть файл

@ -4,13 +4,13 @@
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
typedef struct { typedef struct {
#if __LINUX_ARM_ARCH__ >= 6 #ifdef CONFIG_CPU_HAS_ASID
unsigned int id; unsigned int id;
#endif #endif
unsigned int kvm_seq; unsigned int kvm_seq;
} mm_context_t; } mm_context_t;
#if __LINUX_ARM_ARCH__ >= 6 #ifdef CONFIG_CPU_HAS_ASID
#define ASID(mm) ((mm)->context.id & 255) #define ASID(mm) ((mm)->context.id & 255)
#else #else
#define ASID(mm) (0) #define ASID(mm) (0)

2
include/asm-arm/mmu_context.h
Просмотреть файл

@ -20,7 +20,7 @@
void __check_kvm_seq(struct mm_struct *mm); void __check_kvm_seq(struct mm_struct *mm);
#if __LINUX_ARM_ARCH__ >= 6 #ifdef CONFIG_CPU_HAS_ASID
/* /*
* On ARMv6, we have the following structure in the Context ID: * On ARMv6, we have the following structure in the Context ID:

1
include/asm-arm/plat-s3c24xx/devs.h
Просмотреть файл

@ -29,6 +29,7 @@ extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi; extern struct platform_device s3c_device_sdi;
extern struct platform_device s3c_device_hsmmc;
extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1; extern struct platform_device s3c_device_spi1;

10
include/asm-arm/unistd.h
Просмотреть файл

@ -373,6 +373,10 @@
#define __NR_getcpu (__NR_SYSCALL_BASE+345) #define __NR_getcpu (__NR_SYSCALL_BASE+345)
/* 346 for epoll_pwait */ /* 346 for epoll_pwait */
#define __NR_kexec_load (__NR_SYSCALL_BASE+347) #define __NR_kexec_load (__NR_SYSCALL_BASE+347)
#define __NR_utimensat (__NR_SYSCALL_BASE+348)
#define __NR_signalfd (__NR_SYSCALL_BASE+349)
#define __NR_timerfd (__NR_SYSCALL_BASE+350)
#define __NR_eventfd (__NR_SYSCALL_BASE+351)
/* /*
* The following SWIs are ARM private. * The following SWIs are ARM private.
@ -433,5 +437,11 @@
*/ */
#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
/*
* Unimplemented (or alternatively implemented) syscalls
*/
#define __IGNORE_sync_file_range 1
#define __IGNORE_fadvise64_64 1
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
#endif /* __ASM_ARM_UNISTD_H */ #endif /* __ASM_ARM_UNISTD_H */