ASoC: rt5651: Remove is_sys_clk_from_pll()
is_sys_clk_from_pll() is used as a snd_soc_dapm_route.connected callback, checking RT5651_GBL_CLK to determine if the sys-clk is PLL1 and thus the PWR_PLL bit in reg PWR_ANLG2 must be set. RT5651_GBL_CLK is changed by rt5651_set_dai_sysclk(), which gets called by the pre_pmu / post_pmd functions of the "Platform Clock" dapm-supply. This creates an ordering issue, during a dapm transition first all connected() callbacks are called to build a list of supplies to enable and then the complete list is walked to enable the supplies. Since the connected() check happens before enabling any supplies, is_sys_clk_from_pll() ends up deciding if the PWR_PLL bit should be set based on the state the "Platform Clock" supply had *before* the transition. This sometimes results in PWR_PLL being off, even though *after* the transition PLL1 is configured as sys-clk. This commit removes is_sys_clk_from_pll() instead simply setting / clearing PWR_PLL in rt5651_set_dai_sysclk() based on the selected sys-clk, which fixes this and as a bonus results in a nice cleanup. Tested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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5f293d4354
Коммит
d082174c99
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@ -398,20 +398,6 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
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return idx;
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}
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static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
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struct snd_soc_dapm_widget *sink)
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{
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struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
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unsigned int val;
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val = snd_soc_component_read32(component, RT5651_GLB_CLK);
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val &= RT5651_SCLK_SRC_MASK;
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if (val == RT5651_SCLK_SRC_PLL1)
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return 1;
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else
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return 0;
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}
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/* Digital Mixer */
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static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
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SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
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@ -883,8 +869,6 @@ static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
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SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
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11, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
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RT5651_PWR_PLL_BIT, 0, NULL, 0),
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/* Input Side */
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SND_SOC_DAPM_SUPPLY("JD Power", RT5651_PWR_ANLG2,
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RT5651_PWM_JD_M_BIT, 0, NULL, 0),
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@ -1167,7 +1151,6 @@ static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
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{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
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{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
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{"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
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{"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
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{"Stereo1 Filter", NULL, "ADC ASRC"},
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{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
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@ -1177,7 +1160,6 @@ static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
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{"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
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{"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
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{"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
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{"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
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{"Stereo2 Filter", NULL, "ADC ASRC"},
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{"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
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@ -1244,10 +1226,8 @@ static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
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{"PDM R Mux", "DD MIX", "DAC MIXR"},
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{"DAC L1", NULL, "Stereo DAC MIXL"},
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{"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
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{"DAC L1", NULL, "DAC L1 Power"},
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{"DAC R1", NULL, "Stereo DAC MIXR"},
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{"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
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{"DAC R1", NULL, "DAC R1 Power"},
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{"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
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@ -1443,6 +1423,7 @@ static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
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struct snd_soc_component *component = dai->component;
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struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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unsigned int reg_val = 0;
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unsigned int pll_bit = 0;
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if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
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return 0;
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@ -1453,6 +1434,7 @@ static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
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break;
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case RT5651_SCLK_S_PLL1:
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reg_val |= RT5651_SCLK_SRC_PLL1;
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pll_bit |= RT5651_PWR_PLL;
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break;
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case RT5651_SCLK_S_RCCLK:
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reg_val |= RT5651_SCLK_SRC_RCCLK;
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@ -1461,6 +1443,8 @@ static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
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dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
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RT5651_PWR_PLL, pll_bit);
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snd_soc_component_update_bits(component, RT5651_GLB_CLK,
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RT5651_SCLK_SRC_MASK, reg_val);
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rt5651->sysclk = freq;
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